Showing papers on "Control reconfiguration published in 1990"

Implementing fault-tolerant services using the state machine approach: a tutorial

Abstract: The state machine approach is a general method for implementing fault-tolerant services in distributed systems. This paper reviews the approach and describes protocols for two different failure models—Byzantine and fail stop. Systems reconfiguration techniques for removing faulty components and integrating repaired components are also discussed.

Fault-tolerant computing: fundamental concepts

Abstract: The basic concepts of fault-tolerant computing are reviewed, focusing on hardware. Failures, faults, and errors in digital systems are examined, and measures of dependability, which dictate and evaluate fault-tolerance strategies for different classes of applications, are defined. The elements of fault-tolerance strategies are identified, and various strategies are reviewed. They are: error detection, masking, and correction; error detection and correction codes; self-checking logic; module replication for error detection and masking; protocol and timing checks; fault containment; reconfiguration and repair; and system recovery. >

Implementation of heuristic search strategies for distribution feeder reconfiguration

Abstract: A method for feeder reconfiguration with the potential for handling realistic operating constraints is presented. The approach taken is to set up a decision tree to represent the various switching operations available. A best-first tree searching strategy, based on heuristics, is used to evaluate the various alternatives. Switching options which could result in overloads, voltage problems, or other operating constraints, such as those associated with system protection, are quickly eliminated as possibilities. The development of a rule-based system aimed at the reduction of the search space is presented as a means of implementing the above strategy. An example is used to illustrate the concepts described. >

Broad-band ATM network architecture based on virtual paths

Abstract: Broadband transport techniques and network architectures based on the virtual path concept are examined. ATM (asynchronous transfer mode) techniques, when coupled with recent technological innovations, are expected to pave the way for future universal transport networks. The virtual path concept, which exploits the ATM's capabilities, is proposed to construct an efficient and economic network. The concept matches current and anticipated technological trends well. Characteristics and implementation techniques of virtual paths are discussed. Advantages of the virtual path concept and its impact on the transport network architecture are demonstrated. The virtual path strategy is also shown to provide efficiently for networks with dynamic reconfiguration capability which will enhance network performance. Some basic analytical results on the dynamic control effects of virtual paths are provided. >

Restructurable control using proportional-integral implicit model following

Abstract: Studies of a proportional-integral implicit modelfollowing control law are presented. The research focuses on the ability of the control law to recover the performance of a failed system to its pre-failure level. Properties of the implicit model-following strategy are examined, and conditions for control reconfiguration are stated. The control law is applied to the lateral-directional model of a fighter aircraft, and control restructuring is shown for changes in control and system matrices. It is concluded that the implicit-model following scheme is a good candidate for control reconfiguration.

State Feedback Assisted Classical Control: An Incremental Approach to Control Modernization of Existing and Future Nuclear Reactors and Power Plants

Abstract: A new control concept, state feedback assisted classical control, is described. The concept incorporates a classical output feedback control system as an easily understood inner control loop and ca...

Algorithm-based fault tolerance on a hypercube multiprocessor

Abstract: The design of fault-tolerant hypercube multiprocessor architecture is discussed. The authors propose the detection and location of faulty processors concurrently with the actual execution of parallel applications on the hypercube using a novel scheme of algorithm-based error detection. System-level error detection mechanisms have been implemented for three parallel applications on a 16-processor Intel iPSC hypercube multiprocessor: matrix multiplication, Gaussian elimination, and fast Fourier transform. Schemes for other applications are under development. Extensive studies have been done of error coverage of the system-level error detection schemes in the presence of finite-precision arithmetic, which affects the system-level encodings. Two reconfiguration schemes are proposed that allow the authors to isolate and replace faulty processors with spare processors. >

A taxonomy of reconfiguration techniques for fault-tolerant processor arrays

Abstract: Focuses on the characterization and classification of reconfiguration techniques. The techniques are differentiated according to the type of redundancy (time or hardware), allocation of redundancy (local or global), replacement unit, (processor or a set of processors), switching domain (global or local), and switching implementation (switching element, bus, or network). Typical techniques from four major classes-set switching, processor switching, local redundancy, and time redundancy-are reviewed. The proposed taxonomy can be used as a guide for future research in design and analysis of reconfiguration schemes. >

Reconfigurable signal processor

Abstract: An interconnection scheme among the processing elements ("PEs") of a multiprocessor computing architecture realizes, through PE reconfiguration, both fault tolerance and a wide variety of different processing topologies including binary trees and linear systolic arrays. By using a novel variant on a tree expansion scheme, the invention also allows for arbitrary up-sizing of the PE count to build virtually any size of tree network, with each size exhibiting same high degree of fault tolerance and reconfigurability. The invention may be practiced with 4-port PEs arrayed in a module comprising a 4×4 board-mounted PE lattice. Each PE has four physical ports, which connect to the similar ports of its lattice neighbors. Each PE has an internal capability to be configured to route signals to or from any of its neighbors. Thus, for tree topologies, any of the four neighbors of a given PE may be selected as the parent of the given PE; and any or all of the remaining three neighboring PEs may be selected as the child(ren) PEs. The PE ports are configured under the control of a remote host, which establishes an initial desired PE topology. The operability of the PEs is tested, and information on faulty PEs or communications paths is used to enable or disable nodes as necessary by revising the PE port configurations. The nodes thus are reorganized and can run or continue running, on a degraded basis.

Optimal loss reduction of distributed networks

Abstract: A novel algorithm for the network reconfiguration of power distribution systems is presented. An optimal loss reduction is accomplished to maintain acceptable voltage at customer loads as well as to assure sufficient conductor and substation current capacity to handle load requirements. The success of the algorithm depends directly upon the straightforward and highly-efficient solution of the quadratic cost transshipment problem. The proposed algorithm completely eliminates the need for matrix operations and executes all operations directly on a graph of the distribution system. >

Efficient algorithms for reconfiguration in VLSI/WSI arrays

Abstract: The issue of developing efficient algorithms for reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources is discussed The models discussed consist of a set of identical processors embedded in a flexible interconnection structure that is configured in the form of a rectangular grid An array grid model based on single-track switches is considered An efficient polynomial time algorithm is proposed for determining feasible reconfigurations for an array with a given distribution of faulty processors In the process, it is shown that the set of conditions in the reconfigurability theorem is not necessary A polynomial time algorithm is developed for finding feasible reconfigurations in an augmented single-track model and in array grid models with multiple-track switches >

Practical application and implementation of distributed system-level diagnosis theory

Abstract: A DSD (distributed self-diagnosing) project that consists of the implementation of a distributed self-diagnosis algorithm and its application to distributed computer networks is presented. The EVENT-SELF algorithm presented combines the rigor associated with theoretical results with the resource limitations associated with actual systems. Resource limitations identified in real systems include available message capacity for the communication network and limited processor execution speed. The EVENT-SELF algorithm differs from previously published algorithms by adopting an event-driven approach to self-diagnosability. Algorithm messages are reduced to those messages required to indicate changes in system those messages required to indicate changes in system state. Practical issues regarding the CMU-ECE DSD implementation are considered. These issues include the reconfiguration of the testing subnetwork for environments in which processors can be added and removed. One of the goals of this work is to utilize the developed CMU-ECE DSD system as an experimental test-bed environment for distributed applications. >

Control systems with rate and magnitude saturation for neutrally stable open loop systems

Abstract: A systematic methodology for the design of control systems with multiple saturations in control magnitude and rate is introduced. A supervisor loop is introduced. When the references and/or disturbances are small enough not to cause saturations, the system operates linearly as designed. When the signals are large enough to cause saturations, the control law is modified in such a way as to preserve, to the extent possible, the behavior of the linear control design. It is shown that the operator error governor can be used to design control systems when the controls saturate in magnitude and rate. The main benefits of the methodology are that it leads to controllers with the following properties: the signals that the modified compensator produces never cause saturation; possible integrators or slow dynamics in the compensator never windup; the closed-loop system has inherent stability properties; and the online computation required to implement the control system is feasible. An example is used to illustrate the methodology and its benefits. >

Reconfigurable flight control via multiple model adaptive control methods

Abstract: A multiple model adaptive control (MMAC) algorithm with seven elemental command generator tracker proportional-plus-integral Kalman filter controllers (designed for an aircraft functioning correctly, for one of three failed sensors, or for one of three failed actuators) demonstrates consistently effective reconfiguration capabilities when subjected to hard and soft failures of sensors or actuators. Performance can be enhanced considerably by use of maximum a posteriori versus Bayesian form of the MMAC (or a modified combination of both), alternate commutation of the MMAC hypothesis probabilities, and reduction of identification ambiguities through scalar residual monitoring. This latter additional voting technique provides unequivocal declarations that a particular sensor has or has not failed, and it may be used to supplant the MMAC methodology for sensor failures. >

The GPA machine: a generally partitionable MSIMD architecture

Abstract: The GPA machine, a massively parallel, multiple single-instruction-stream-multiple-data-stream (MSIMD) system is described. Its distinguishing characteristics is the generality of its partitioning capabilities. Like the PASM system it can be dynamically reconfigured to operate as one or more independent SIMD machines. However, unlike PASM, the only constraint placed on partitioning is that an individual processing element is a member of at most one partition. This capability allows for reconfiguration based on the run-time status of dynamic data structures and for partitioning of disconnected and overlapping data structures. Significant speedups are expected from operating on data structures in place; copying of data to a newly configured partition is unnecessary. The GPA system consists of N processing-element/RAM pairs and an interconnection network providing access to and from P control processors or microcontrollers. With current technologies, values for N and P of 64K and 16, respectively, are feasible. >

Flexible asynchronous transfer mode networks utilizing virtual paths

Abstract: The effect of virtual paths in ATM (asynchronous transfer mode) networks is investigated. The virtual path concept has been proposed as the key technique in enhancing network performance. The impact of the virtual path scheme on transport network architecture and systems is demonstrated in comparison to the digital path scheme in STM-based networks. One of the outstanding virtual path benefits, increased network flexibility, is highlighted. It is shown that dynamic network reconfiguration capability is effectively provided with the virtual path scheme. Some analytical results on the adaptive virtual path bandwidth control effects for multimedia traffic are provided. >

Exploiting replication in distributed systems

Abstract: Techniques are examined for replicating data and execution in directly distributed systems: systems in which multiple processes interact directly with one another while continuously respecting constraints on their joint behavior Directly distributed systems are often required to solve difficult problems, ranging from management of replicated data to dynamic reconfiguration in response to failures It is shown that these problems reduce to more primitive, order-based consistency problems, which can be solved using primitives such as the reliable broadcast protocols Moreover, given a system that implements reliable broadcast primitives, a flexible set of high-level tools can be provided for building a wide variety of directly distributed application programs

On designing and reconfiguring k-fault-tolerant tree architectures

Abstract: A general approach to designing tree structured multiprocessors with optimal or near-optimal fault tolerance properties is developed. A multiprocessor architecture with a static interconnection network is represented by a graph whose nodes are processors and whose edges are interprocessor communication links. The design of k-fault-tolerant (FT) trees for arbitrary k is considered, with the primary goal of minimizing the number of spare nodes and edges. Also presented are strategies for reconfiguring a k-FT supergraph of a tree T around faults to obtain a fault-free tree isomorphic to T. A systematic methodology is presented for designing k-FT nonhomogeneous symmetry d-ary trees based on a concept termed node covering. The designs are shown to be optimal when k >

Geometric Phases, and Optimal Reconfiguration for Multibody Systems

Abstract: Relative Motion in a system of coupled rigid bodies can yield global reorientation (or phase shift). We give a formula to compute such a phase shift and interpret the same in geometric terms. The theory of connections in principal bundles provides the proper setting for questions of the type addressed in this paper. A related optimal control problem leads to singular riemannian geometry.

System for testing adaptor card upon power up and having disablement, enablement, and reconfiguration options

Abstract: A data processing system such as a personal computer includes a plurality of expansion connectors for receiving adapter cards. A non-volatile memory stores programmable option select (POS) data that is stored when the system is configured. A Power On Self Test (POST) operation is performed during which adapters are checked to determine if any have been added, moved or removed, since a previous system configuration. If any have been so altered, the system may be placed in operation with all adapters enabled except for those which were altered.

Method and apparatus for reconfiguring interconnections between switching system functional units

Abstract: An illustrative method and structural arrangement for reconfiguration of switching system functional units where although the distributed control entities and the distributed switch units of a switching system are in fixed association, the association between peripheral circuits and the control and switch units is not fixed. Rather a group of peripheral circuits is connectable to at least first and second ones of the distributed switch units. When the group of peripheral circuits is connected to the first distributed switch unit, the control unit associated with the first distributed switch unit processes calls to and from the group of peripheral circuits. When the group of peripheral circuits is connected to the second distributed switch unit in response to a reconfiguration signal, the control unit associated with the second distributed switch unit processes calls to and from the group. In particular embodiments, the selective connection of the group of peripheral circuits to different distributed switch units is effected by an interconnection arrangement used to interconnect the switching system and a multiplex of communication circuits from a transmission facility. In one embodiment the interconnection arrangement is implemented using a digital access and crossconnect system (DACS), and in a second embodiment, using a plurality of add/drop multiplexers interconnected in a fiber ring.

User activated memory programming authorization in a selective call receiver

Abstract: A selective call receiver (12) with memory (78) is described for use in a system (10) providing user initiated alteration of the content of the memory (78) using reconfiguration information transmitted from an external source (20). The receiver (12) comprises a circuit for generating a user activated programming authorization signal (82), a receiver (54) for receiving the transmitted reconfiguration information, and a circuit (58) for altering the content of the memory (78) in response to the received reconfiguration information only in the presence of the user activated programming authorization signal.

Dynamic network reconfiguration technique for directed-token expanded-address LAN

Abstract: Additional nodes beyond those permitted by the size of the address field of a standard network operating protocol, may be added to a directed token LAN, and the added nodes may be automatically and dynamically configured or reconfigured into a token passing loop. The added nodes, referred to as enhanced nodes, interoperably combine a standard reconfiguration sequence of a standard network operational protocol with an enhanced reconfiguration sequence of an enhanced protocol in order to send tokens to establish the next active nodes of the network and thereby establish the token passing loop through all of the standard and enhanced nodes.

Kinematic methods for automated fixture reconfiguration planning

Abstract: A kinematic method is developed to analyze the workholding condition by evaluating the motion stops corresponding to the reciprocal screw motions within a given fixture configuration. More significantly, the method can be used to compare the relative quality of two or more configurations in terms of the overall kinematic constraint. Graphically based methods are then developed which can be used to synthesize a fixture layout configuration for a given 3-D workpart geometric model. A CAD system is used to demonstrate the techniques for automated fixture layout planning. The results of this work have been applied directly to a set of modular fixture elements for sheet metal workparts. For simple geometries, the fixture configurations chosen with the motion stop method agree well with the intuitive choices an engineer would make. However, for complicated geometries, these methods provide analysis and synthesis solutions which would not otherwise be possible. >

The full-use-of-suitable-spares (FUSS) approach to hardware reconfiguration for fault-tolerant processor arrays

Abstract: A general approach to hardware recognition is proposed for VLSI/WSI fault-tolerant processor arrays. The technique, called full use of suitable spares (FUSS), uses an indicator vector, the surplus vector, to guide the replacement of faulty processors within an array. Analytical study of the general FUSS algorithm shows that there is a linear relationship between the array size and the area of interconnect required for reconfiguration to be 100% successful. In an instance of FUSS, called simple FUSS, reconfiguration is done by shifting up to or down the surplus vector's entries. The surplus vector is progressively updated after each column is reconfigured. The reconfiguration is successful when the surplus vector becomes null. Simple FUSS is discussed in detail and evaluated. Simulations show that when the number of faulty processors is equal to that of space processors, simple FUSS can achieve a probability of survival as high as 99%. >

Strategies for reconfiguring hypercubes under faults

Abstract: The design of two reconfiguration strategies for hypercube multicomputer architectures under failures is discussed. The first scheme uses spare processors attached to certain processors in the hypercube by means of a novel embedding technique. The second approach places spare processors between specific links in the hypercube. Both schemes involve the mapping of logical links of a virtual hypercube onto a set of physical links in the final reconfigured hypercube and hence suffer some performance degradation. >