Showing papers on "Data flow diagram published in 1987"

The program dependence graph and its use in optimization

Abstract: In this paper we present an intermediate program representation, called the program dependence graph (PDG), that makes explicit both the data and control dependences for each operation in a program. Data dependences have been used to represent only the relevant data flow relationships of a program. Control dependences are introduced to analogously represent only the essential control flow relationships of a program. Control dependences are derived from the usual control flow graph. Many traditional optimizations operate more efficiently on the PDG. Since dependences in the PDG connect computationally related parts of the program, a single walk of these dependences is sufficient to perform many optimizations. The PDG allows transformations such as vectorization, that previously required special treatment of control dependence, to be performed in a manner that is uniform for both control and data dependences. Program transformations that require interaction of the two dependence types can also be easily handled with our representation. As an example, an incremental approach to modifying data dependences resulting from branch deletion or loop unrolling is introduced. The PDG supports incremental optimization, permitting transformations to be triggered by one another and applied only to affected dependences.

Synchronous data flow

Abstract: Data flow is a natural paradigm for describing DSP applications for concurrent implementation on parallel hardware. Data flow programs for signal processing are directed graphs where each node represents a function and each arc represents a signal path. Synchronous data flow (SDF) is a special case of data flow (either atomic or large grain) in which the number of data samples produced or consumed by each node on each invocation is specified a priori. Nodes can be scheduled statically (at compile time) onto single or parallel programmable processors so the run-time overhead usually associated with data flow evaporates. Multiple sample rates within the same system are easily and naturally handled. Conditions for correctness of SDF graph are explained and scheduling algorithms are described for homogeneous parallel processors sharing memory. A preliminary SDF software system for automatically generating assembly language code for DSP microcomputers is described. Two new efficiency techniques are introduced, static buffering and an extension to SDF to efficiently implement conditionals.

Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing

Abstract: Large grain data flow (LGDF) programming is natural and convenient for describing digital signal processing (DSP) systems, but its runtime overhead is costly in real time or cost-sensitive applications. In some situations, designers are not willing to squander computing resources for the sake of programmer convenience. This is particularly true when the target machine is a programmable DSP chip. However, the runtime overhead inherent in most LGDF implementations is not required for most signal processing systems because such systems are mostly synchronous (in the DSP sense). Synchronous data flow (SDF) differs from traditional data flow in that the amount of data produced and consumed by a data flow node is specified a priori for each input and output. This is equivalent to specifying the relative sample rates in signal processing system. This means that the scheduling of SDF nodes need not be done at runtime, but can be done at compile time (statically), so the runtime overhead evaporates. The sample rates can all be different, which is not true of most current data-driven digital signal processing programming methodologies. Synchronous data flow is closely related to computation graphs, a special case of Petri nets. This self-contained paper develops the theory necessary to statically schedule SDF programs on single or multiple processors. A class of static (compile time) scheduling algorithms is proven valid, and specific algorithms are given for scheduling SDF systems onto single or multiple processors.

A Test Design Methodology for Protocol Testing

Abstract: Communication protocol testing can be done with a test architecture consisting of remote Lower Tester and local Upper Tester processes. For real protocols, tests can be designed based on the formal specification of the protocol which uses an extended finite state machine model. The specification is transformed into a simpler form consisting of normal form transitions. It can then be modeled by a control and a data flow graph. The graphs are decomposed into subtours and data flow functions, respectively. Tests are designed by considering parameter variations of the input primitives of each data flow function and determining the expected outputs. The methodology gives complete test coverage of all data flow functions and control paths in the specification. Functional fault models are proposed for functions that are not formally specified.

Method for compiling a master task definition data set for defining the logical data flow of a distributed processing network

Abstract: A compiler method is disclosed which defines a data flow for a specific complex function to be executed on a plurality of data processing elements in a distributed processing system, by means of defining a plurality of control blocks which are associated with each task. The control blocks are in relocatable code so that they may be associated with any one of several similar types of data processing elements within the distributed processing network. The control blocks include local operating system control blocks, token control, post and wait control blocks, and processing element task execution control blocks. The use of the distributed processing system compiler method enables the quick and easy implementation of complex functions having interdependent processing tasks in a distributed processing system.

Dataflow processing element, multiprocessor, and processes

Abstract: A novel computer design that is capable of utilizing large numbers of very large scale integrated (VLSI) circuit chips as a basis for efficient high performance computation. This design is a static dataflow architecture of the type in which a plurality of data flow processing elements (110) communicate externally by means of input/output circuitry (128), and internally by means of packets sent through a routing network (124) via paths (122). The routing network (124) implements a transmission path from any processing element to any other processing element. This design effects processing element transactions on data according to a distribution of instructions that is at most partially ordered. These instructions correspond to the nodes of a directed graph in which any pair of nodes connected by an arc corresponds to a predecessor-successor pair of instructions. Generally each predecessor instruction has one or more successor instructions, and each successor instruction has one or more predecessor instructions. In accordance with the present invention, these instructions include associations of execution components and enable components identified by instruction indices.

Pipeline interleaved programmable DSP's: Synchronous data flow programming

Abstract: In the companion paper [1], a programmable architecture for digital signal processing is proposed that requires the partitioning of a signal processing task into multiple programs that execute concurrently. In this paper, a synchronous dataflow programming method is proposed for programming this architecture, and programming examples are given. Because of its close connection with block diagrams, data flow programming is natural and convenient for describing digital signal processing (DSP) systems. Synchronous dataflow is a special case of data flow (large grain or atomic) in which the number of tokens consumed or produced each time a node is invoked is specified for each input or output of each node. A node (or block) is asynchronous if these numbers cannot be specified a priori. A program described as a synchronous data flow graph can be mapped onto parallel processors at compile time (statically), so the run time overhead usually associated With data flow implementations evaporates. Synchronous data flow is therefore an appropriate paradigm for programming high-performance real-time applications on a parallel processor like the processors in the companion paper. The sample rates can all be different, which is not true of most current data-driven digital signal processing programming methodologies. Synchronous data flow is closely related to computation graphs, a special case of Petri nets. In this paper, we outline the programming methodology by illustrating how nodes are defined, how data passed between nodes are buffered, and how a compiler can map the nodes onto parallel processors. We give an example of a typically complicated unstructured application: a voiceband data modem. For this example, using a natural partition of the program into functional blocks, the scheduler is able to use up to seven parallel processors with 100 percent utilization. Beyond seven processors, the utilization drops because the scheduler is limited by a recursive computation, the equalizer tap update loop. No attempt has been made to modify the algorithms or their description to make them better suited for parallel execution. This example, therefore, illustrates that modest amounts of concurrency can be effectively used without particular effort on the part of the programmer.

Incorporating Data Flow Ideas into von Neumann Processors for Parallel Execution

Abstract: The issues of memory latency, synchronization, and distribution costs in multiprocessors are reviewed. The approaches taken by conventional and data flow architectures are contrasted in relation to these issues. It is pointed out that each approach fits well for a certain situation and that it is possible to have a common framework in which the two execution models can be mixed to suit the situation. An architecture is sketched by describing a few extensions to a conventional processor. While existing programs run without much change, it is shown that improvements could be made by using the new features to tolerate memory latency and to exploit more parallelism. It is shown that data flow graphs can be executed on this to exploit as much parallelism as a data flow architecture could. It is argued that such a testbed will provide for a selective translation of program segments into the appropriate execution model. A fast context switching hardware is presumed for this architecture.

Pipeline interleaved programmable DSP's: Architecture

Abstract: Programmable processors specialized to intensive numerical computation and real-time signal processing are often deeply pipelined. The ensuing gain in throughput is moderated by the difficulty of efficiently programming such processors. Techniques for overcoming this difficulty are effective only for modest amounts of pipelining. This paper proposes applying an old but rarely used architectural approach to the design of single-chip signal processors so that the potential benefits of extensive pipelining can be fully realized. The architectural approach is to interleave multiple processes (or programs) through a single deeply pipelined processor in such a way that the disadvantages of deep pipelining disappear. Instead, the user is faced with the need to construct programs that can execute as concurrent processes. The main advantage is that much more pipelining can be used without aggravating the programming. A specific experimental architecture is outlined. The solution offered is a "system solution" in that architectural performance is considered along with programmability and ease of use. In the companion paper, data flow programming is suggested so that algorithms can be automatically partitioned for concurrent execution. Data flow provides a natural environment in which to build signal processing programs and can be supported efficiently in an architecture of the type described here.

A fully abstract semantics for data flow nets

Abstract: Two semantic models for data flow nets are given. The first model is an intuitive, operational model. This model has an important drawback: it is not compositional. An example given in [Brock & Ackerman 1981] shows the non-compositionality of our model. There exist two nets that have the same semantics, but when they are placed in a specific context, the semantics of the resulting nets differ. The second one is obtained by adding information to the first model. The amount of information is enough to make it compositional. Moreover, we show that we have added the minimal amount of information to make the model compositional: the second model is fully abstract with respect to the equivalence generated by the first model. To be more specific: the first model describes the semantics a data flow net as a function from (tuples of) sequences of tokens to sets of (tuples of) sequences of tokens. The second one maps a data flow net to a function from (tuples of) infinite sequences of finite words tO sets of (tuples of) infinite sequences of finite words.

A metamodel of information flow: a tool to support information systems theory

Abstract: In this paper an axiomatic, fundamental metamodel of data flow is constructed. The components of the metamodel are the states along the flow of data: physical events, language (data), stored data, human data processing, and decision making. Transfers from one state to another are performed by functions: coding, keying, processing, perceptions, and human acting. The entire flow is evaluated by a value function. Each of the states and functions is rigorously described by means of definitions, axioms, and theorems. The main purpose of the metamodel is to provide a common framework for various models in MIS and consequently to remedy the "Tower of Babel" syndrome prevailing in this area. The way the metamodel can be used to develop other models in MIS is explained in the last part of the paper.

A fully abstract semantics for data flow nets

Abstract: Two semantic models for data flow nets are given. The first model is an intuitive, operational model. This model has an important drawback: it is not compositional. An example given in [Brock & Ackerman 1981] shows the non-compositionality of our model. There exist two nets that have the same semantics, but when they are placed in a specific context, the semantics of the resulting nets differ. The second one is obtained by adding information to the first model. The amount of information is enough to make it compositional. Moreover, we show that we have added the minimal amount of information to make the model compositional: the second model is fully abstract with respect to the equivalence generated by the first model. To be more specific: the first model describes the semantics a data flow net as a function from (tuples of) sequences of tokens to sets of (tuples of) sequences of tokens. The second one maps a data flow net to a function from (tuples of) infinite sequences of finite words tO sets of (tuples of) infinite sequences of finite words.

AIDA—a dynamic data flow anomaly detection system for Pascal programs

Abstract: This paper presents a description of, and experience in using, AIDA, an automated instrumentation system to perform data flow analysis for Pascal programs. AIDA is capable of detecting not only data flow anomalies, but also certain kinds of errors. It is a useful software testing and development tool for Pascal programs. The associated implementation problems and their solutions are presented.

Multi-processor including data flow accelerator module

Abstract: An accelerator module for a data flow computer includes an intelligent memory The module is added to a multiprocessor arrangement and uses a shared tagged memory architecture in the data flow computer The intelligent memory module assigns locations for holding data values in correspondence with arcs leading to a node in a data dependency graph Each primitive computation is associated with a corresponding memory cell, including a number of slots for operands needed to execute a primitive computation, a primitive identifying pointer, and linking slots for distributing the result of the cell computation to other cells requiring that result as an operand Circuitry is provided for utilizing tag bits to determine automatically when all operands required by a processor are available and for scheduling the primitive for execution in a queue Each memory cell of the module may be associated with any of the primitives, and the particular primitive to be executed by the processor associated with the cell is identified by providing an index, such as the cell number for the primitive, to the primitive lookup table of starting addresses The module thus serves to perform functions previously performed by a number of sections of data flow architectures and coexists with conventional shared memory therein A multiprocessing system including the module operates in a hybrid mode, wherein the same processing modules are used to perform some processing in a sequential mode, under immediate control of an operating system, while performing other processing in a data flow mode

An incremental algorithm for software analysis

Abstract: In programming environments aimed at “industrial strength” software development, there is a need for software tools which facilitate both design and maintenance. These tools should encourage experimentation with different system configurations which enable designers to a priori estimate the associated system complexity and judge the ease of accommodating enhancements. Maintainers should be able to check straightforwardly the ramifications of system changes due to enhancements or “bug fixes”. With interprocedural data flow information about the definition and use of global variables and parameters in a software system, tools can be built to perform these tasks.For large, complex systems, efficient methods for interprocedural analysis are necessarily incremental, as a software system is a dynamically evolving entity. Incremental algorithms update current information about a system in response to a change rather than re-calculating the information by re-analyzing the entire system. This paper reports our development of a general purpose incremental data flow analysis algorithm, which is applicable to both intraprocedural and interprocedural domains. It is based on interval analysis, a technique whose observed performance is linear for most programs; under reasonable assumptions about program flow graphs this linearity can be verified [20].

Method for concurrent execution of primitive operations by dynamically assigning operations based upon computational marked graph and availability of data

Abstract: Computationally complex primitive operations of an algorithm are executed concurrently in a plurality of functional units under the control of an assignment manager. The algorithm is preferably defined as a computationally marked graph contianing data status edges (paths) corresponding to each of the data flow edges. The assignment manager assigns primitive operations to the functional units and monitors completion of the primitive operations to determine data availability using the computational marked graph of the algorithm. All data accessing of the primitive operations is performed by the functional units independently of the assignment manager.

Control Flow and Data Flow: concepts of distributed programming

Abstract: On the Nature of Computing Science.- I. Operational Models of Distributed Systems.- Distributed Systems, Partial Orderings of Events, and Event Structures.- On Mixed Computation: Informal Account of the Strict and Polyvariant Computational Schemes.- II. Abstract Modelling of Distributed Systems.- Notes on Communicating Sequential Processes.- Lectures on a Calculus for Communicating Systems.- Extensional Behaviour of Concurrent, Nondeterministic, Communicating Systems.- III. Hardware as Distributed Systems.- The Architecture of Parallel Computers.- Data Flow Computation.- Concurrent Computations and VLSI Circuits.- IV. Design and Verification of Distributed Systems.- Proving Correctness of CSP Programs, a Tutorial.- Real Time Clocks versus Virtual Clocks.- The Image Construction in Computerized Axial Tomography.- Derivation of a Termination Detection Algorithm for Distributed Computations.- The Distributed Snapshot of K. M. Chandy and L. Lamport.- A Simple Fix Point Argument without the Restriction to Continuity.

MELDing data flow and object-oriented programming

Abstract: MELD combines concepts from data flow and object-oriented programming languages in a unique approach to tool reusability. MELD provides three units of abstraction — equations, classes and features — that together allow sufficient options for granularity and encapsulation to support the implementation of reusable tools and the composition of existing tools in parallel (i.e., interleaved) as well as in series.

Data flow and data structure modeling for database requirements determination: a comparative study

Abstract: This study investigated, in an experimental setting, the existence, nature and causes of the differences in the completeness of logical data specifications generated by professional systems analysts having training and experience in the use of one of two modeling approaches. The approach used primarily modeled either the data flows or the data structure of an object system. The systems analysts were asked to analyze a case and to generate logical file specifications which were evaluated for completeness. The results of the study indicate that the data structure analysts produced logical data specifications which contained a greater number of entity views and attributes than those of the data flow analysts. Data flow analysts had greater difficulty with the concepts involved in specifying logical data specifications and consequently derived less complete data specifications than data structure analysts.

A unified resource management and execution control mechanism for data flow machines

Abstract: This paper presents a unified resource management and execution control mechanism for data flow machines. The mechanism integrates load control, depth-first execution control, cache memory control and a load balancing mechanism. All of these mechanisms are controlled by such basic information as the number of active state processes, Na. In data flow machines, synchronization among processes is an essential hardware function. Hence, Na can easily be detected by the hardware.Load control and depth-first execution control make it possible to execute a program with a designated degree of parallelism, and depth-first order. A cache memory of data flow processors in multiprocessing environments can be realized by using load and depth-first execution controls together with a deterministic replacement algorithm, i.e. replacement of only waiting state processes. A new load balancing method called group load balancing is also presented to evaluate the above mentioned mechanisms in multiprocessor environments.These unified control mechanisms are evaluated on a register transfer level simulator for a list-processing oriented data flow machine.

Mapping data flow programs on a VLSI array of processors

Abstract: With the advent of VLSI, relatively large processing arrays may be realized in a single VLSI chip Such regularly structured arrays take considerably less time to design and test, and fault-tolerance can easily be introduced into them However, only a few computational algorithms which can effectively use such regular arrays have been developed so farWe present an approach to mapping arbitrary algorithms, expressed as programs in a data flow language, onto a regular array of data-driven processors implemented by a number of VLSI chips Each chip contains a number of processors, interconnected by a set of regular paths, and connected to processors in other similar chips to form a large array This array is thus tailored to perform a specific computational task, as an attached processor in a larger systemThe data flow program is first translated into a graph representation, the data flow graph, which is then mapped onto a finite but (theoretically) unbounded array of identical processors Each node in the graph represents an operation which can be performed by an individual processor in the array Therefore, the mapping operation consists of assigning nodes in the graph to processors in the array, and defining the connections between the processors according to the arcs in the graph The last step consists of partitioning the unbounded array into a number of segments, to account for the number of processors which fit in a single VLSI chip

Affect-chaining in program flow analysis applied to queries of programs

Abstract: This thesis presents how program flow analysis methods can be used to help the programmer understand data flow and data dependencies in programs. The design and implementation of an interactive que ...

A data-driven model for a subset of logic programming

Abstract: There is a direct correspondence between semantic networks and a subset of logic programs, restricted only to binary predicates. The advantage of the latter is that it can describe not only the nodes and arcs comprising a semantic net, but also the data-retrieval operations applied to such nets. The main objective of this paper is to present a data-driven model of computation that permits this subset of logic programs to be executed on a highly parallel computer architecture. We demonstrate how logic programs may be converted into collections of data-flow graphs in which resolution is viewed as a process of finding matches between certain graph templates and portions of the data-flow graphs. This graph fitting process is carried out by messages propagating asynchronously through the data-flow graph; thus computation is entirely data driven, without the need for any centralized control and centralized memory. This permits a potentially large number of independent processing elements to cooperate in solving a given query.

Mentat: An object-oriented macro data flow system

Abstract: Mentat is an object-oriented macro data flow system designed to facilitate parallelism in distributed systems. Its underlying model of computation is the macro data flow model. The Macro data flow model is similar to the traditional, large grain data flow model with two differences: (1) Some macro actors are persistent actors that maintain state information between firings; (2) Program graphs are dynamic. Macro data flow programs are represented by dynamic structures called future lists that may be constructed and modified at run time. This paper discusses the motivation of the macro data flow model; the relationship between objects, actors, and tokens; the use of future lists; extensions to the programming language C++ for writing macro data flow programs; and the structure of a virtual macro data flow machine for executing macro data flow programs.

Method and device for real-time processing of a sequenced data flow, and application to the processing of digital video signals representing a video image

Abstract: The invention relates to a method and a device for real-time processing of a sequenced data flow, especially representing a video image. At each sequence, an arithmetic and logic unit generates and stores a histogram signal representing the significance of the data at various levels; a microcontroller reads the histogram signal, extracts Gauss functions which are characteristic of the latter, selects, from these functions, one or more functions which are representative of class and extracts the minimum and maximum levels of each selected function. Comparison means derive a class membership signal on the basis of these minimum and maximum levels. The method of the invention works in real time on the flow of data sequence by sequence, has the benefit of very short response times and may be implemented by means of a simple device possessing storage memories of moderate capacity.