Showing papers on "Decimal published in 2007"

A New Family of High.Performance Parallel Decimal Multipliers

Abstract: This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry-save multioperand addition that uses a novel BCD-4221 recoding for decimal digits. It significantly improves the area and latency of the partial product reduction tree with respect to previous proposals. We also present three schemes for fast and efficient generation of partial products in parallel. The recoding of the BCD-8421 multiplier operand into minimally redundant signed-digit radix-10, radix-4 and radix-5 representations using new recoders reduces the complexity of partial product generation. In addition, SD radix-4 and radix-5 recodings allow the reuse of a conventional parallel binary radix-4 multiplier to perform combined binary/decimal multiplications. Evaluation results show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix-8 parallel binary multipliers and other representative alternatives for decimal multiplication.

IBM POWER6 accelerators: VMX and DFU

Abstract: The IBM POWER6™ microprocessor core includes two accelerators for increasing performance of specific workloads. The vector multimedia extension (VMX) provides a vector acceleration of graphic and scientific workloads. It provides single instructions that work on multiple data elements. The instructions separate a 128-bit vector into different components that are operated on concurrently. The decimal floating-point unit (DFU) provides acceleration of commercial workloads, more specifically, financial transactions. It provides a new number system that performs implicit rounding to decimal radix points, a feature essential to monetary transactions. The IBM POWER™ processor instruction set is substantially expanded with the addition of these two accelerators. The VMX architecture contains 176 instructions, while the DFU architecture adds 54 instructions to the base architecture. The IEEE 754R Binary Floating-Point Arithmetic Standard defines decimal floating-point formats, and the POWER6 processor--on which a substantial amount of area has been devoted to increasing performance of both scientific and commercial workloads--is the first commercial hardware implementation of this format.

Binary-coded decimal digit multipliers

Abstract: With the growing popularity of decimal computer arithmetic in scientific, commercial, financial and Internet-based applications, hardware realisation of decimal arithmetic algorithms is gaining more importance. Hardware decimal arithmetic units now serve as an integral part of some recently commercialised general purpose processors, where complex decimal arithmetic operations, such as multiplication, have been realised by rather slow iterative hardware algorithms. However, with the rapid advances in very large scale integration (VLSI) technology, semi- and fully parallel hardware decimal multiplication units are expected to evolve soon. The dominant representation for decimal digits is the binary-coded decimal (BCD) encoding. The BCD-digit multiplier can serve as the key building block of a decimal multiplier, irrespective of the degree of parallelism. A BCD-digit multiplier produces a two-BCD digit product from two input BCD digits. We provide a novel design for the latter, showing some advantages in BCD multiplier implementations.

Decimal floating-point in z9: an implementation and testing perspective

Abstract: Although decimal arithmetic is widely used in commercial and financial applications, the related computations are handled in software. As a result, applications that use decimal data may experience performance degradations. Use of the newly defined decimal floating-point (DFP) format instead of binary floating-point is expected to significantly improve the performance of such applications. System z9TM is the first IBM machine to support the DFP instructions. We present an overview of this implementation and provide some measurement of the performance gained using hardware assists. Various tools and techniques employed for the DFP verification on unit, element, and system levels are presented in detail. Several groups within IBM collaborated on the verification of the new DFP facility, using a common reference model to predict DFP results.

Irrational Numbers: The Gap between Formal and Intuitive Knowledge

Abstract: This report focuses on prospective secondary mathematics teachers’ understanding of irrational numbers. Various dimensions of participants’ knowledge regarding the relation between the two sets, rational and irrational, are examined. Three issues are addressed: richness and density of numbers, the fitting of rational and irrational numbers on the real number line, and operations amongst the elements of the two sets. The results indicate that there are inconsistencies between participants’ intuitions and their formal and algorithmic knowledge. Explanations used by the vast majority of participants relied primarily on considering the infinite non-repeating decimal representations of irrationals, which provided a limited access to issues mentioned above.

Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach

Abstract: Decimal arithmetic has been revived in recent years due to the large amount of data in commercial applications. We consider the problem of multioperand parallel decimal addition with an approach that uses binary arithmetic, suggested by the adoption of binary-coded decimal (BCD) numbers. This involves corrections in order to obtain the BCD result or a binary-to-decimal (BD) conversion. We adopt the latter approach, which is particularly efficient for a large number of addends. Conversion requires a relatively small area and can afford fast operation. The BD conversion moreover allows an easy alignment of the sums of adjacent columns. We treat the design of BCD digit adders using fast carry-free adders and the conversion problem through a known parallel scheme using elementary conversion cells. Spreadsheets have been developed for adding several BCD digits and for simulating the BD conversion as a design tool.

A parallel IEEE P754 decimal floating-point multiplier

Abstract: Decimal floating-point multiplication is important in many commercial applications including banking, tax calculation, currency conversion, and other financial areas. This paper presents a fully parallel decimal floating-point multiplier compliant with the recent draft of the IEEE P754 Standard for Floating-point Arithmetic (IEEE P754). The novelty of the design is that it is the first parallel decimal floating-point multiplier offering low latency and high throughput. This design is based on a previously published parallel fixed-point decimal multiplier which uses alternate decimal digit encodings to reduce area and delay. The fixed-point design is extended to support floating-point multiplication by adding several components including exponent generation, rounding, shifting, and exception handling. Area and delay estimates are presented that show a significant latency and throughput improvement with a substantial increase in area as compared to the only published IEEE P754 compliant sequential floating-point multiplier. To the best of our knowledge, this is the first publication to present a fully parallel decimal floating-point multiplier that complies with IEEE P754.

Decimal Floating-Point Multiplication Via Carry-Save Addition

Abstract: Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents the design of a decimal floating-point multiplier that complies with specifications for decimal multiplication given in the draft revision of the IEEE 754 standard for floating-point arithmetic (IEEE 754R). This multiplier extends a previously published decimal fixed- point multiplier design by adding several features including exponent generation, sticky bit generation, shifting of the intermediate product, rounding, and exception detection and handling. The core of the decimal multiplication algorithm is an iterative scheme of partial product accumulation employing decimal carry-save addition to reduce the critical path delay. Novel features of the proposed multiplier include support for decimal floating-point numbers, on-the- fly generation of the sticky bit, early estimation of the shift amount, and efficient decimal rounding. Area and delay estimates are provided for a verified Verilog register transfer level model of the multiplier.

Reduced Delay BCD Adder

Abstract: Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 times slower than binary arithmetic implemented in hardware. Therefore, hardware support for decimal arithmetic is required. In this paper, a reduced delay binary coded decimal (BCD) adder is proposed. The proposed adder improves the delay of BCD addition by increasing parallelism. On the critical-path of the proposed BCD adder, there are two 4-bit binary adders, a carry network, one AND gate, and one OR gate. To make area and delay comparison, the proposed adder and previously proposed five decimal adders are implemented in VHDL and synthesized using 0.18 micron TSMC ASIC library. Synthesis results obtained for 64-bit addition (16 decimal digits) show that the proposed BCD adder has the shortest delay (1.40 ns). Furthermore, it requires less area than previously proposed three decimal adders.

Irrational numbers on the number line – where are they?

Abstract: This paper reports part of an ongoing investigation into the understanding of irrational numbers by prospective secondary school teachers. It focuses on the representation of irrational numbers as points on a number line. In a written questionnaire, followed by a clinical interview, participants were asked to indicate the exact location of the square root of 5 on a number line. The results suggest confusion between irrational numbers and their decimal approximation and overwhelming reliance on the latter. Pedagogical suggestions are discussed.

A Decimal Floating-Point Divider Using Newton---Raphson Iteration

Abstract: Increasing chip densities and transistor counts provide more room for designers to add functionality for important application domains into future microprocessors. As a result of rapid growth in financial, commercial, and Internet-based applications, hardware support for decimal floating-point arithmetic is now being considered by various computer manufacturers and specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic (IEEE P754). In this paper, we presents an efficient arithmetic algorithm and hardware design for decimal floating-point division. The design uses an efficient piecewise linear approximation, a modified Newton---Raphson iteration, a specialized rounding technique, and a simplified decimal incrementer and decrementer. Synthesis results show that a 64-bit (16-digit) implementation of the decimal divider, which is compliant with the current version of IEEE P754, has an estimated critical path delay of 0.69 ns (around 13 FO4 inverter delays) when implemented using LSI Logic's 0.11 micron Gflx-P standard cell library.

Power6 Decimal Divide

Abstract: The IEEE 754-R floating-point standard has defined the arithmetic and encodings of the new decimal floating-point format. The C and C++ standards as well as other language standards have proposed a new data type to help programmers exploit the performance of this new hardware format. The IBM Power6 microprocessor will soon release the first hardware implementation of this decimal floating-point format. A discussion of how the decimal division operation is implemented in high frequency BCD hardware and a comparison to other division methods is provided. This implementation reuses some popular binary division algorithms such as prescaling and non-restoring division to reduce the amount of additional hardware. Novel twists are applied to these algorithms to adapt them for BCD formatted numbers.

Elementary Mathematics Pedagogical Content Knowledge: Powerful Ideas for Teachers

Abstract: Most chapters include "Preview," "Chapter Review," "Self-Check," "Selected References, "Online Activities" and "Activities and Exercises" Introduction Chapter 1: The changing landscape of elementary mathematics teaching and learning A distinction between conceptual knowledge and procedural knowledge Problem-focused teaching Communication in a mathematics classroom Reasoning Patterns and Change Mathematical connections Chapter 2: The Powerful ideas: Composition, Decomposition, Relationships, Representation, and Context 39 Composition Decomposition Relationships Representation Context Chapter 3: Powerful ideas related to the number system What is counting? (How Many?) What are numbers? How do we represent numbers? What is a number system? How have number systems developed differently in the past (and what's so special about today's number system?) The idea of base Basic Digits and Place Value Composition Chapter 4: Powerful ideas related to arithmetic Addition and Subtraction Multiplication Division Chapter 5: Powerful ideas related to geometry What is geometry? Why learn geometry? Why do people have difficulty with geometry? Spatial visualization and properties of shapes Translations, Rotations, Reflections (or Slides, Turns, and Flips) Similarity and Congruence Reasoning about types of shapes Deduction Chapter 6: Powerful ideas related to parts and wholes Reprise: One Whole or Many Parts? Decomposition and Partitioning What is the whole? (and Why does it matter?) Various meanings of fractions Equivalent Fractions and Simplest Form Adding and subtracting with fractions Multiplying with fractions Dividing with fractions Caution about a possible point of confusion Chapter 7: Powerful ideas related to the decimal numbers Relationship between decimal numbers and fractions Relationship between decimal numbers and place value concepts Special uses of decimal numbers: money and percent Arithmetic: Special concerns with decimal numbers Chapter 8: Powerful ideas related to measurement The concept of measurement Why does measurement matter? Linear measurement Linear measurement as compared with area measurement Measurement of volume Measurement of weight Measurement of time Units as standards The power of the metric system Uncertainty and degrees of precision Estimation Choosing the best measurement unit The use of formulas (or not?) Chapter 9: Powerful ideas related to data analysis Some general thoughts about statistics Posing statistical questions Collecting data Organizing and displaying data Measures of center The concept of distribution Descriptive Graphs Chapter 10: Powerful ideas related to probability What is probability? Finding the Number of Outcomes Some Problem Situations Formulas What about "Odds?" Some Common Misconceptions Chapter 11: Powerful ideas related to ratio and proportion Linear relationships Percent What about Non-linear Relationships Chapter 12: Powerful ideas related to reasoning Number sense Inductive reasoning Deductive reasoning The Yin and Yang of Using Inductive Reasoning and Deductive Reasoning Together Mathematical authority? Evaluation of mathematical thought Chapter 13: Powerful ideas related to algebra Basics of Algebra Functions Graphing Functions on the Coordinate System Non-linear Functions Appendix A: Explanations of Complex Formulas The Combinations Formula Cross-multiplication for Solving Proportions The Lattice Method of Multiplication Appendix B: Answers to Self-Check and Activities

A radix-10 SRT divider based on alternative BCD codings

Abstract: In this paper we present the algorithm and architecture a radix-10 floating-point divider based on an SRT non-restoring digit-by-digit algorithm. The algorithm uses conventional techniques developed to speed-up radix-2k division such as signed-digit (SD) redundant quotient and digit selection by constant comparison using a carry-save estimate of the partial remainder. To optimize area and latency for decimal, we include novel features such as the use of alternative BCD codings to represent decimal operands, estimates by truncation at any binary position inside a decimal digit, a single customized fast carry propagate decimal adder for partial remainder computation, initial odd multiple generation and final normalization with rounding, and register placement to exploit advanced high fanin mux-latch circuits. The rough area-delay estimations performed show that the proposed divider has a similar latency but less hardware complexity (1.3 area ratio) than a recently published high performance digit-by-digit implementation.

Hardware design of a Binary Integer Decimal-based floating-point adder

Abstract: Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P754). In this paper, we present a novel algorithm and hardware design for a DFP adder. The adder performs addition and subtraction on 64-bit operands that use the IEEE P754 binary encoding of DFP numbers, widely known as the binary integer decimal (BID) encoding. The BID adder uses a novel hardware component for decimal digit counting and an enhanced version of a previously published BID rounding unit. By adding more sophisticated control, operations are performed with variable latency to optimize for common cases. We show that a BID-based DFP adder design can be achieved with a modest area increase compared to a single 2-stage pipelined 64-bit fixed-point multiplier. Over 70% of the BID adderpsilas area is due the 64-bit fixed-point multiplier, which can be shared with a binary floating-point multiplier and hardware for other DFP operations. To our knowledge, this is the first hardware design for adding and subtracting IEEE P754 BID-encoded DFP numbers.

Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder

Abstract: The decimal arithmetic has been receiving an increased attention because of the growth of financial and scientific applications requiring high precision and increased computing power. This paper presents an efficient architecture for multi-digit decimal addition based on carry-free signed-digit numbers. In this study, the decimal adder architecture has been designed and synthesized using the TSMC 0.18mu technology. The synthesis results were compared to the existing decimal adders with respect to design area, delay and power consumption. These results show that proposed adder architecture improves the area-delay factor by 3 for a 32 digit adder.

Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format

Abstract: In view of increasing prominence of commercial, financial and Internet-based applications that process data in decimal format, there is a renewed interest in providing hardware support to handle decimal data. In this paper, a new architecture for efficient 1-digit decimal addition of binary coded decimal (BCD) operands, which is the core of high speed multi-operand adders and floating decimal-point arithmetic, is proposed. Based on this 1-digit BCD adder, novel architectures for higher order (n-digit) BCD adders such as ripple carry adder and carry look-ahead adder are derived. The proposed circuits are compared (both qualitatively as well as quantitatively) with the existing circuits in literature and are shown to perform better. Simulation results show that the proposed 1-digit BCD adder achieves an improvement of 40% in delay. The 16-digit BCD look-ahead adder using prefix logic is shown to perform at least 80% faster than the existing ripple carry one.

A New Look at Reversible Logic Implementation of Decimal Adder

Abstract: Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. This research proposes a new implementation of Binary Coded Decimal (BCD) adder in reversible logic. The design reduces the number of gates and garbage outputs compared to the existing BCD adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay.

Method and apparatus for decimal number multiplication using hardware for binary number operations

Abstract: According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding multiplication results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.

Evolving Digital Electronic Circuits for Real-Valued Function Generation using a Genetic Algorithm

Abstract: In this paper we describe experiments which attempt to evolve digital electronic circuits whose purpose is to implement real signals. As a convenience we chose to evolve mathematical functions i.e. the square-root and sine. Real numbers in the range 0.00-0.99 are encoded in binary using four bits per decimal place. The chromosome used is exactly modelled on the resources available on the Xilinx 6216 re-configurable Field Programmable Gate Array (FPGA), so that evolved circuit designs may be simply implemented on this target device. We investigated a number of ways of presenting examples to the circuit so that the target function might be learned, and also looked at two distinctly different fitness function definitions.

Solving Constraints on the Intermediate Result of Decimal Floating-Point Operations

Abstract: The draft revision of the IEEE Standard for Floating- Point Arithmetic (IEEE P754) includes a definition for decimal floating-point (FP) in addition to the widely used binary FP specification. The decimal standard raises new concerns with regard to the verification of hardware- and software-based designs. The verification process normally emphasizes intricate corner cases and uncommon events. The decimal format introduces several new classes of such events in addition to those characteristic of binary FP. Our work addresses the following problem: Given a decimal floating-point operation, a constraint on the intermediate result, and a constraint on the representation selected for the result, find random inputs for the operation that yield an intermediate result compatible with these specifications. The paper supplies efficient analytic solutions for addition and for some cases of multiplication and division. We provide probabilistic algorithms for the remaining cases. These algorithms prove to be efficient in the actual implementation.

Apparatus and method using compressed codes for comprising latitude/longitude information

Abstract: A new human interface scheme compresses geographical information, latitudes and longitudes, into a 10 symbols of 36 radices number systems which are based on 36s. It is to simplify the conventional representation of the latitudes and longitudes into much easier to be remembered and accessed by human beings, 10 symbols of 36 radices numbers, “Universal Geo Numbers”. The 5 symbols here can give the accuracy for latitudes and longitudes down to 5 meters which should be enough to accommodate the specifications for most geographic navigation related systems (i.e. GPS/GLONASS) and navigation equipments in the consumer market. The apparatus includes all means that comprise latitude/longitude information into the compressed codes for interfacing between human and machines. A technique for compressing latitude and longitude data into a compression code comprises the steps of: taking Latitude/longitude data in decimal format or converting all other formats into decimal format; adding 90 degrees to latitude values and 180 degrees to longitude values in order to shift them into the positive values; eliminating the decimal points and converting the latitude and longitude values in decimal into 5 symbols of 36 based numbers respectively; and interlacing these two numbers inverting a final format. The present invention further includes a decimator, an adder, a converter and an interlacer for performing the step of above method.

Masterpieces to Mathematics: Using Art to Teach Fraction, Decimal, and Percent Equivalents.

Abstract: dDeveloping visual models of rational numbers is critical in building an understanding of multiple and equivalent forms of rational numbers and the relationship among fractions, decimals, and percents. Historically, middle school students have had difficulty with rational numbers for a variety of reasons. Sowder and Schappelle (1995) state that middle school students spend little time with problems that relate fraction and decimal numbers. Often, fractions and decimals are taught separately without providing students the opportunity to make the connection, which stunts their ability to fully understand rational numbers. In addition, the National Research Council (NRC 2001) reports that “rational numbers are more complex than whole numbers, in part because they are represented in several ways” (p. 231) (e.g., common fractions and decimal fractions) and used in many ways (e.g., as parts of regions and sets, as ratios, as quotients). These topics also present a challenge for middle school students because they are likely to have few out-of-school experiences with rational numbers. Therefore, the NRC recommends that “teachers play a more active and direct role in providing relevant experiences to enhance students’ informal understanding and in helping them elaborate their informal understanding into a more formal network of concepts and procedures” (NRC 2001, p. 231). This article shares how students created their own Op Art (optical art), which was inspired by Ellsworth Kelly, and how they connected that work of art to rational numbers. By identifying colored portions of a grid, the students recognized fraction, decimal, and percent breakdowns of their own designs. Through visual and mathematical representations of rational numbers, they learned mathematics through the lens of an artist. Using Art to Teach Fraction, Decimal, and Percent Equivalents

3-in-1 barcode for identifying commodity

Abstract: A 3-in-1 barcode for identifying a commodity, involving a commercial cipher technology, is implemented through the following steps: acquiring a first and second group of data in the form of 13-digit decimal number that are input into a computer for being processed; determining whether the first group of data satisfies an EAN-13 encoding principle or not, and whether the second group of data satisfies an commodity flow number encoding principle or not, if yes, proceeding to the next step, otherwise, generating an error prompt; performing an encryption operation on the first group of data satisfying the EAN-13 encoding principle and the second group of data satisfying the commodity flow number encoding principle through a commercial cipher algorithm, and generating a 13-digit decimal verification code data; dividing the first group of data, the second group of data, and the verification code data into three rows by the computer; and storing and printing the 3-in-1 barcode divided into three rows by the computer, for machine identification. The advantage of the present invention lies in that the 3-in-1 barcode has a plain part and a cipher part, which is easily identified by both the users and consumers, and cannot be easily counterfeited and forged.

Processor support for decimal floating-point arithmetic

Abstract: Decimal data permeates society, as humans most commonly use base-ten numbers. Although microprocessors normally use base-two binary arithmetic to obtain faster execution times and simpler circuitry, binary numbers cannot represent decimal fractions exactly. This leads to large errors being accumulated after several decimal operations. Furthermore, binary floating-point arithmetic operations perform binary rounding instead of decimal rounding. Consequently, applications, such as financial, commercial, tax, and Internet-based applications, which are sensitive to representation and rounding errors, often require decimal arithmetic. Due to the increasing importance of and demand for decimal arithmetic, its formats and operations have been specified in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P754). Most decimal applications use software routines and binary arithmetic to emulate decimal operations. Although this approach eliminates errors due to converting between binary and decimal numbers and provides decimal rounding to mirror manual calculations, it results in long latencies for numerically intensive commercial applications. This is because software emulation of decimal floating-point (DFP) arithmetic has significant overhead due to function calls, dealing with decimal formats, operand alignment, decimal rounding, and special case and exception handling. This dissertation investigates processor support for decimal floating-point arithmetic. It first reviews recent progress in decimal arithmetic, including decimal encodings, the IEEE P754 Draft Standard, and software packages, hardware designs, and benchmark suites for decimal arithmetic. Next, this dissertation presents novel arithmetic algorithms and hardware designs for basic DFP operations, including DFP addition, subtraction, division, square root, and others. Most of the hardware designs presented in this dissertation are the first published designs compliant with the IEEE P754 Draft Standard. Finally, to study the performance impact of DFP instructions and hardware, this dissertation presents the first publicly available benchmark suite for DFP arithmetic. This benchmark suite, along with instruction set extensions and a decimal-enhanced processor simulator, are used to demonstrate that providing fast hardware support for DFP operations leads to significant performance benefits to DFP-intensive applications.

Testing D-Sequences for their Randomness

Abstract: This paper examines the randomness of d-sequences, which are decimal sequences to an arbitrary base. Our motivation is to check their suitability for application to cryptography, spread-spectrum systems and use as pseudorandom sequence.

On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--

Abstract: In digital signal processing, radixes other than two are often used for high-speed computation. In the computation for finance, decimal numbers are used instead of binary numbers. In such cases, radix converters are necessary. This paper considers design methods for binary to q-nary converters. It introduces a new design technique based on weighted-sum (WS) functions. The method computes a WS function for each digit by an LUT cascade and a binary adder, then adds adjacent digits with q-nary adders. A 16-bit binary to decimal converter is designed to show the method.

Motion vector detecting apparatus and method

Abstract: PROBLEM TO BE SOLVED: To provide a motion vector detecting apparatus capable of detecting a motion vector with an accuracy of decimal without increasing the power consumption and upsizing the circuit scale SOLUTION: The motion vector detecting apparatus includes a decimal accuracy motion vector detection section 104 and a motion vector detection control section 105 that detect a motion vector by using only pixel values stored in a searching region image data memory 102 in a decimal position image block comprising decimal position pixels located around integer position pixels included in an image block particularized by a motion vector with an accuracy of integer to select only the image block at decimal positions comprising decimal position pixels whose pixel values can be calculated and an image block at integer positions particularized by the motion vector with an accuracy of integer for searching objects COPYRIGHT: (C)2007,JPO&INPIT

DECIMAL and PLFaultCAT: From Product-Line Requirements to Product-Line Member Software Fault Trees

Abstract: PLFaultCAT is a tool for software fault tree analysis (SFTA) during product-line engineering. When linked with DECIMAL, a product-line requirements verification tool, the enhanced version of PLFaultCAT provides traceability between product- line requirements and SFTA hazards as well as semi-automated derivation of the SFTA for each new product-line system previously verified by DECIMAL. The combined tool reduces the effort needed to safely reuse requirements and customize the product-line SFTA as each new system is constructed.