Showing papers on "Delta-sigma modulation published in 1991"

A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion

Abstract: The authors examine the application of oversampling techniques to analog-to-digital conversion at rates exceeding 1 MHz. A cascaded multibit sigma-delta ( Sigma Delta ) modulator that substantially reduces the oversampling ratio required for 12-b conversion while avoiding stringent component matching requirements is introduced. Issues concerning the design and implementation of the modulator are presented. At a sampling rate of 50 MHz and an oversampling ratio of 24, an implementation of the modulator in a 1- mu m CMOS technology achieves a dynamic range of 74 dB at a Nyquist conversion rate of 2.1 MHz. The experimental modulator is a fully differential circuit that operates from a single 5-V power supply and does not require calibration or component trimming. >

A comparison of modulator networks for high-order oversampled Sigma Delta analog-to-digital converters

Abstract: After a discussion of the practical problem of comparing the relative performance of all known high-order modulator networks with respect to resolution, stability, input range, component sensitivities, finite amplifier gains, and bandwidths, equations are derived and verified by computer simulation that relate reduction in signal-to-noise ratio to component mismatch and finite amplifier gain, allowing designers to choose the best network for a particular application. A third-order, sigma-delta ( Sigma - Delta ) oversampled analog-to-digital (A/D) modulator network is presented. It shows improved performance in most respects over previous modulators. Although its theoretical performance in the absence of circuit nonidealities is below that of the triple first-order cascade network, when practical impairments such as finite amplifier gains and component mismatch are considered, it displays superior performance. Gain and offset errors are potentially lower for this network due to its ability to use a single capacitor for input signal and D/A feedback. A markedly reduced sensitivity to nonidealities for this network implies that monolithic circuits could be manufactured with better processing yields and hence lower unit costs. >

Multiaccumulator sigma-delta fractional-n synthesis

Abstract: A fractional-N synthesizer employing at least a second order sigma-delta modulator is disclosed. The most significant bits from the output accumulator (1011) of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider (103). Modulation to the synthesizer is introduced as part of the digital number input to the sigma-delta modulator and spurious signal output is realized by selection of a large number as the denominator of the fractional portion of the loop divider divisor.

Second-order sigma-delta modulation for digital-audio signal acquisition

Abstract: The authors compare the second-order sigma-delta ( Sigma Delta ) modulator to several alternative modulator architectures in the context of digital-audio signal acquisition. Design details and experimental results are presented for a 1 mu m CMOS implementation that does not require error correction or component trimming to achieve virtually ideal 16 b performance at a conversion rate of 50 kHz. The experimental modulator is a fully differential circuit that operates from a single 5 V power supply and does not require the use of precision sample-and-hold circuitry. With an oversampling ratio of 256 and a clock rate of 12.8 MHz, the modulator achieves a 98 dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 94 dB. Measurements and simulations of discrete noise peaks in the output spectrum that result from limit-cycle oscillations are also presented and discussed. >

Theory and practical implementation of a fifth-order sigma-delta A/D converter

Abstract: An 18-bit analog-to-digital converter integrated circuit has been designed which uses a fifth-order loop filter with an unusual loop topology. Implementation of the loop using differential switched-capacitor techniques is described. A one-step decimation filter with 115-dB stopband attenuation is used to remove out-of-band quantization noise. Preliminary measurements indicate a dynamic range of 105 dB, a number that is compatible with the requirements of professional digital audio

Dithering and its effects on sigma-delta and multistage sigma-delta modulation

Abstract: The spectrum of the quantization error in a dithered sigma-delta modulator is derived under the constraint that the dithering signal does not cause overload. The results apply to DC, sinusoidal, and more general quasi-stationary signals. It is shown in the case of a simple sigma-delta modulation that no-overload dithering can smooth the error spectrum and can make the quantization error asymptotically uncorrelated with the input. It does not, however, make the quantization error white. In the case of multistage sigma-delta modulation with the appropriate dithering, the quantization error becomes white, even for a system with only two stages. The signal-to-quantization-noise ratio (SQNR) is derived for sigma-delta and multistage sigma-delta oversampled analog-to-digital conversion with additive dithering. Simulation results, are presented to support the theoretical analysis. >

Bandpass implementation of the sigma-delta A-D conversion technique

Abstract: A new design of band-pass sigma-delta A-D converter is presented which can encode the signal at the intermediate frequency and then by digital post processing convert to baseband I and Q. The technique of band-pass sigma-delta conversion is described and a method for designing band-pass A-D converters from existing baseband modulator designs is given with an example to illustrate the theory. Practical results are described with the performance specified in conventional RF circuit terms. >

Bandpass sigma-delta analog-to-digital conversion

Abstract: The traditional low-pass sigma-delta ( Sigma Delta ) analog-to-digital converter is extended to the bandpass case. For input signals with small relative bandwidths, bandpass Sigma Delta converters offer high signal-to-noise ratios at significantly lower sampling rates than are required for low-pass Sigma Delta converters. A sixth-order single-ended switched-capacitor circuit, clocked at 3 MHz, is designed to convert bandpass signals centered at 455 kHz with 20-kHz bandwidth. Time-domain circuit simulations show that this modulator realizes a 94-dB signal-to-noise ratio for a half-scale input, giving roughly 16-b performance. >

Third-order cascaded sigma-delta modulators

Abstract: A sigma-delta modulator architecture wherein third-order noise shaping is achieved with relatively modest constraints on device matching is explored. The architecture is based on a cascade of a second-order modulator stage followed by a first-order stage, both using 1-b quantization. To improve the dynamic range, the input to the second stage is generated as an asymmetrically weighted error signal from the first stage. An analytical model for assessing the performance and device matching requirements of cascaded architectures is introduced, and computer simulations are used to verify the approximations made in this model. The analytical model is used to show that the proposed architecture offers performance comparable to other third-order cascaded sigma-delta modulator topologies, while being less sensitive to device matching errors. >

Sigma delta modulator

Abstract: A separate filter circuit is inserted between the D/A converter and the summing junction in the feedback path of a conventional sigma delta modulator. This additional filter allows control of the quantization noise transfer function profile independently of the forward signal transfer function. By proper tailoring of the transfer functions a third or higher order modulator can be constructed without instability developing. The modulator can also be constructed as a completely digital circuit and used as a noise shaping circuit in a digital digital-to-analog converter.

Phase based vector modulator

Abstract: Vector modulation is effected by summing output signals from two phase modulators. The lack of amplitude modulation on the signals when summed permits non-linear processing of the signals, such as PLL frequency translation. In one embodiment, the phase modulators comprise fractional-N phase locked loops modulated with digital data words. In another, the phase modulators comprise direct digital synthesizers.

Sigma-delta oversampled analog-to-digital converter network with chopper stabilization

Abstract: In an oversampling interpolative analog-to-digital converter having a sigma-delta modulator followed in cascade by a decimation filter, the decimation filter supplies digital output signals for the oversampling analog-to-digital converter at an output rate that is a submultiple 1/R of an oversampling rate at which digital samples of an input signal for said decimation filter are supplied. The chopping rate of the chopper-stabilized amplifier is a multiple of the output sample rate of the decimation filter to place the fundamental and the harmonics of the chopping at the frequencies corresponding to the zeroes in the decimation filter response, better to keep remnants of the chopper stabilization from appearing in the output samples from the decimation filter. The chopper stabilization moves the flicker (or 1/f) noise of the amplifier in the frequency spectrum from baseband to sidebands of the chopping frequency, and the chopper-stabilized amplifier is operated at a chopping rate higher than said output rate, to reduce the amplitude of the lower sideband as aliased into the baseband. The chopper-stabilized amplifier is operated at a chopping rate lower than half said oversampling rate, to reduce non-linearities associated with the settling of the chopper stabilized amplifier after each switching thereof.

Read-out of photodiodes using sigma-delta oversampled analog-to-digital converters.

Abstract: Sigma-delta analog-to-digital conversion is used in sensing apparatus that generates a digital signal descriptive of light energy received by a photosensor, such as one of a plurality of photosensors that together receive various elements of a radiant-energy image. A preamplifier generates an analog output signal responsive to the photocurrent of the photosensor, which analog output signal is undesirably accompanied by wideband noise. The analog output signal is supplied to a sigma-delta analog-to-digital converter, the decimation filter of which not only suppresses in the digital signal a component arising from the quantization noise from the sigma-delta modulator portion of the analog-to-digital converter, but also suppresses a component arising from remnant wideband noise from the preamplifier.

A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities

Abstract: A multistage third-order sigma-delta modulator, which is unconditionally stable and has a low sensitivity to component mismatch and op-amp performance limitations, has been designed and fabricated in a 1.2- mu m CMOS double-poly technology. The modulator, consisting of cascaded second- and first-order stages, is scaled to prevent performance degradation from integrator overload. In addition, the first-stage integrator output is used directly, instead of its quantization error, to facilitate ratioless input circuitry in the second stage. Experimental results indicate a signal-to-noise ratio of 93 and 90 dB at a signal-to-distortion ratio of 93 dB for sample rates of 24 and 80 kHz, respectively. >

Multi-stage sigma-delta analog-to-digital converter

Abstract: A precision sigma-delta A/D converter having a desired number of cascaded stages is disclosed herein. The multi-stage sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal X(z) to an output sequence of digital words. The converter (10) of the present invention includes a first sigma-delta converter stage (14) for generating a first sequence of digital words and a quantization error signal in response to the analog input signal X(z). An interstage amplifier (34) then amplifies the quantization error signal by a first gain factor G. The present invention further includes a second sigma-delta converter stage (18) for generating a second sequence of digital words in response to the amplified quantization error signal. The first and second sequences are next filtered by a digital noise cancellation network (31, 32) and the filtered second sequence is divided by the first gain factor G via a divider circuit (38). A summing circuit (40) provides the output sequence of digital words by summing the filtered first sequence and the divided second sequence. The digital noise cancellation network (32) is also used to compensate for errors due to analog component imperfections, e.g., capacitor mismatches and finite operational amplifier gain.

System for generating correction signals for use in forming low distortion analog signals

Abstract: A method and apparatus for generating correction signals for use in forming low distortion analog signals. A digital representation of a desired analog waveform is encoded into a digital data signal which is outputted to memory. A digital correction signal is encoded, having an opposite phase and increased amplitude from the signal distortion which it is determined will occur when the digital data signal is repetitively read out of memory and decoded. This digital correction signal is outputted to memory. The digital data and correction signals are repetitively and synchronously read out of memory into a decoder. The decoder converts both digital signals into analog signals, so that the analog correction signal may superpose on the distortion in the analog data signal, resulting in a low distortion analog signal.

Delta sigma modulator having programmable gain/attenuation

Abstract: A delta signma modulator is programmable to realize a number of different gain settings. A user of the delta sigma modulator (which may be a human or an electronic system) may select a setting among a plurality of available settings. Programmability of gain is realized by selectively controlling the rate of sampling of an analog input relative to the rate of sampling of a reference voltage and/or by controlling interspersing of samples of fixed voltage with the analog input or reference voltage. To effect a positive gain, the rate of sampling of the analog input is selected to the bar larged than that of the rate of sampling of the known reference voltage. Alternatively, or additionally, fixed voltage charge samples are interspersed with the reference. In contrast, to effect a negative gain, the rate of sampling of the analog input is set to be less than the rate of sampling of the reference voltage and/or samples of fixed voltage are interspersed with the analog input. Lastly, to effect no net gain, the rate of sampling of the analog input is set to be substantially equal to the rate of sampling of the reference voltage.

High-order, plural-bit-quantization sigma-delta modulators using single-bit digital-to-analog conversion feedback

Abstract: A high-order sigma-delta modulator has a single feedback loop including a linear network and a quantizer, which quantizer comprises a plural-bit analog-to-digital converter, a digital comparator and a single-bit digital-to-analog converter. The linear network comprises a cascade of integrators, a second-order resonator, a cascade of second-order resonators or a cascade of second-order resonators with an additional integrator. The loop behaves much the same as a conventional single-feedback-loop, one-bit sigma-delta modulator, inasfar as the feedback signal is concerned. However, a plural-bit preliminary output signal is available, so the truncation error can be determined. The truncation error is cancelled in the ultimate output signal from the high-order sigma-delta modulator, using additional digital circuitry having the a transfer function analogous to the overall transfer function for input signal of the cascade connection of the linear network, plural-bit analog-to-digital converter in the quantizer, and any scaling circuitry therein or thereafter.

Multiplexed sigma-delta A/D converter

Abstract: A sigma-delta analog-to-digital converter employs multiplexed single-loop modulators (101, 102, 103, 104) in parallel and respectively phased time-divided clocks. The parallel modulators have the effect of producing digital output at a high sampling frequency that is a multiple of the phased switching frequencies applied to the modulator circuits. In one preferred embodiment, four second-order sigma-delta modulators are driven in clocked phased sequence and combined by a multiplexor circuit. Another embodiment employs second-order modulators using RC integrators. A further embodiment replaces the multiplexor with an adder when in-phase modulator clocks are used, and the adder also acts as a simple low pass filter.

A first-order current-steering sigma-delta modulator

Abstract: A new architecture is presented for a first-order sigma-delta ( Sigma Delta ) modulator. The system achieves a high sampling frequency, can be used as a building block for higher-order modulators, and uses circuit techniques that are largely independent of a specific technology. The key features of this implementation are that it operates in a continuous-time (as opposed to switched) mode and does not need feedback amplifiers. To test the validity of the concept, the system was realized in 2- mu m, n-well, double-metal, single-poly technology. It has a measured resolution of 9 b and a linearity of 13 b at a clock frequency of 20 MHz with an oversampling ratio of 128. It operates from a power supply of +or-2.5 V with a power consumption of 3 mW. The circuit occupies an area of 0.92 mm/sup 2/. >

Two phase sampling for a delta sigma modulator

Abstract: A delta sigma modulator provides dual phase sampling of analog input and/or a reference voltage. This dual phase sampling may be realized using a switched capacitor circuit having dual legs with a capacitor on each such leg. The dual phase sampling of the reference voltage poses a complication that mandates the necessity of providing a compensation signal. The delta sigma modulator is provided with appropriate circuitry to provide a compensation signal that compensates for the reduced signal level due to the dual sampling. In particular, the delta sigma modulator compensates for the reduced level of the output from an integrating amplifier circuit due to the timing necessary to implement the dual sampling approach.

Multibit sigma-delta modulator with reduced sensitivity to DAC nonlinearity

Abstract: A new architecture is presented for a multibit oversampled Sigma-Delta A/D convertor. A novel feedback arrangement is employed to reduce the sensitivity of the overall resolution to the nonlinearity of the multibit DAC. Simulations confirm the improved performance achieved by the proposed structure.

16 bit error-correcting digital-to-analog converter

Abstract: An improved digital-to-analog conversion circuit (10) comprises digital circuitry (12) for receiving digital input signals from a digital input signal source, conversion circuitry (42) receiving the digital input signals and producing analog output signals and analog output circuitry (44) for sending analog output signals to an analog output signal load The conversion circuit (10) includes calibration circuitry (46) that samples analog output signals from analog output circuitry (44) and includes a reference signal source (52) for producing a plurality of reference signals A comparator (50) compares a predetermined aspect of the analog output signals to the reference signals to produce therefrom a plurality of difference signals Correction circuitry includes error detection circuit (95) that includes a successive approximation register (62) and a digital controller (66) for receiving the difference signals and a digital interpolator (26) for generating a plurality of correction signals The digital interpolator (26) receives the correction signals in response thereto and sends signals to a vernier digital-to-analog converter (38) to precisely control the analog output signals from conversion circuitry (42)

IIR filtering on sigma-delta modulated signals

Abstract: A design methodology for realising IIR filters on sigma-delta modulated signals is proposed It is shown that only 3N adders together with minor logic are required to implement an Nth order filter This type of filtering should prove useful in VLSI technologies where interfaces to analogue signals are required

Digital-to-analog converter using pulse-width modulation

Abstract: A digital-to-analog converter utilizing a PWM system for converting input digital data to PWM signals and finally to an analog signal divides the sampling period of the input digital data into an even number of sampling periods and produces PWM signals with equal pulse widths corresponding to the input digital data each divided sampling period, whereby a simple structure is provided to reduce harmonic distortion and obtain a high quality analog signal.

Plural-channel decimation filter, as for sigma-delta analog-to-digital converters

Abstract: A decimation filter in which two filtering processes are carried out on a time-division-multiplexed basis using kernels that are sampled-data representations of triangular waves, one of which triangular waves decrements while the other increments, or vice versa. A digital multiplier receives the time-interleaved kernels as a multiplicand and receives as a multiplier a stream of bits supplied at a rate that is one-quarter that of the filter clock pulses. The digital multiplier applies its product output signal to the addend input port of a parallel-bit adder. The sum output port of this adder connects to a cascade connection of first, second, third and fourth clocked latches. The signal from the output port of the fourth clocked latch is supplied to the augend input port of the adder except during the first four clock pulse durations after the kernel values reach maxima. The signal from the output port of the third clocked latch is supplied to the augend input port of the adder during zeroeth and second clock pulse durations after the kernel values reach maxima, and arithmetic zero is supplied to the augend input port of the adder during the first and third clock pulse durations after the kernel values reach maxima. First and second output signals for the decimation filter are extracted from the output ports of the second and fourth clocked latches. This decimation filter can be used on a single-channel or dual-channel basis.

Analog-to-digital signal converter comprising a multiple sigma-delta modulator

Abstract: Analog-to-digital converter comprising a plurality of sigma-delta modulators, the input of the pulse shaper of a modulator always being coupled to the input of a next modulator via a coupling filter, and the output of the modulators being connected to the summing circuit via decimators, whereas in the decimators the filter function of the coupling filters is compensated. The loop filters in the modulators are described by third-order transfer functions with real poles and zeros.

Digital circuit simulation of analog/digital circuits

Abstract: A method and apparatus for providing a single digital simulation of a circuit with analog and digital components. A netlist characterizing a circuit with analog and digital components is utilized. The netlist defines each component in the circuit and its interconnections. The netlist is conveyed to a digital simulator which includes an expanded cell library. The cell library defines analog components in a digital manner. The digitally defined analog components process analog signals which are simulated as arrays of binary values, termed vector voltages. The vector voltages may be combined, mathematically or logically, with other vector voltages to produce binary signals suitable as inputs to digital circuit elements. Regardless of the complexity of the circuit, and despite the fact that both analog and digital components are present, a single integrated digital simulation of the entire circuit is rapidly executed by utilizing digital models of the analog components.

Noise Shaping and Pulse-Width Modulation for an All-Digital Audio Power Amplifier

Abstract: Results from simulations of the performance of new methods for digital audio power amplification are presented. Digital pulse-width modulation is used in conjuction with interpolative noise-shaping techniques to convert digital audio signal data directly into analog power