Showing papers on "Digital electronics published in 1975"

Digital circuit failure detector

Abstract: A device for detecting the existence and location of failures on circuit boards is disclosed. The device is specially adapted for use with boards having a number of serially connected digital loops. Digital circuitry is provided which simultaneously compares a number of checkpoints on the faulty board with corresponding points on a known good board, and the first point to fail is isolated. Inhibit circuitry prevents failure indications at checkpoints if those failures occur subsequent to the first failure.

An experimental multiplier circuit based on superconducting Josephson devices

Abstract: This paper describes the design, testing, and operation of a 4-bit multiplier circuit based on Josephson tunneling logic (JTL) gates. The algorithm adopted was that of a simple serial 4-bit multiplier consisting of a 4-bit adder with ripple carry, together with a four phase, 8-bit accumulator shift register. The circuit, fabricated using a 25-/spl mu/m minimum linewidth technology, operated with a minimum cycle time of 6.67 ns (a limit imposed by the external test equipment) giving a 4-bit multiplication time of 27 ns with an average power dissipation of 35 /spl mu/W per logic gate. With better external pulse generators, or internal Josephson junction generators, the present circuit has been simulated to operate with a 3.0-ns cycle giving a 4-bit multiplication time of 12 ns.

Logic level decoding circuit

Abstract: In a digital system wherein digital data having two operating logic voltage levels corresponding to two different logic states is transmitted from one unit and received at another separate unit, circuitry is provided for determining the mean voltage value of the received logic voltage levels and for comparing the mean voltage value to the received data to provide decoding of the correct logic state of the individual signal bits.

Synthesis of multiple input-change hazard-free combinational switching circuits without feedback†

Abstract: This paper deals with hazards on outputs of combinational circuits without feedback for multiple input changes. A procedure is given to decompose a Boolean function into a feedback free circuit. The procedure either gives a logic hazard-free circuit or shows that the Boolean function cannot be broken down into a feedback free circuit which is free of logic hazards for multiple input changes. The procedure proves that all multiple input change combinational circuits cannot be implemented without dynamic logic hazards with no internal feedback. The result is therefore considerably different than the single input change and multiple input change static logic hazard cases.

Deductive Techniques for Simulating Logic Circuits

Abstract: The use of logic simulation to facilitate the development of computers, telephone switching processors, and other digital systems has almost become an accepted industrial practice. In order to improve the quality of the design, to evaluate design alternatives, and to shorten development intervals, logic simulators have found wide-spread applications in design checkout and verification, derivation and validation of fault-detection and fault-isolation tests, and management of design and manufacturing data. Because of this, the efficiency of logic simulation techniques has also become a vital concern among the simulator developers and the users.

Principles of Transistor Circuits: Introduction to the Design of Amplifiers, Receivers and Digital Circuits

Abstract: Over the last 40 years, Principles of Transistor Circuits has provided students and practitioners with a text they can rely on to keep them at the forefront of transistor circuit design.Although integrated circuits have widespread application, the role of discrete transistors both as important building blocks which students must understand, and as practical solutions to design problems, remains undiminished.The ninth edition has been thoroughly updated to cover the latest technology and applications, including computer circuit simulation, and many diagrams have been revised to bring them in line with current usage. Updated topics include thyristors, Darlington transistors, amplifiers, ring modulators, power supplies, optoelectronics and logic circuits.

Applications of low-level differential logic

Abstract: Application of low-level differential logic will be discussed, citing a bipolar 8 × 8 bit multiplier with a 15-ns multiply time. The device LSI circuit uses either 2's complement or sign-magnitude binary number notation. A digital parallel correlator operating at a 150-MHz data rate has also been developed.

Mode control computer interface

Abstract: In simulation equipment which performs the function of signal processing sensor systems simulation for in-depth analysis of critical parameters and systems response, a mode control interface allows a single operator of simulation equipment to remotely control the modes of several analog simulators or analog computers, either manually or automatically. Diode transistor logic is used in developing selected logic functions for controlling the proper mode of operation of simultaneously activated simulated systems.

Digital automatic frequency control system

Abstract: This invention relates to an automatic frequency control system wherein analog and digital techniques are utilized to detect and correct an off-frequency condition of a controlled oscillator. Digital circuits determine the operating frequency of this oscillator and produce a discrete error voltage when an off-frequency condition exists. The error voltage is then fed back to the oscillator for use in correcting the off-frequency condition.

A System of Magnetic Bubble Logic

Abstract: By using two magnetic-bubble positions per bit it is possible to develop simple logical circuits which display essentially unlimited fan-in and fan-out. Systems of these circuits can be organized such that they conserve bubbles. Pipelining methods can be employed to enhance the throughput.

Signal maximum or minimum seeking circuit

Abstract: SIGNAL MAXIMUM OR MINIMUM SEEKING CIRCUIT Abstract of the Disclosure In a feedback control circuit, a combined analog and digital circuit maximizes or minimizes a controlled signal by incrementally varying the controlling signal. A condition of the system is that the controlled signal must reach a maximum or minimum in the range of the controlling signal. Specifically, the circuit is applied to a wheel slip control of an electric locomotive to adjust the motor current to a maximum value to obtain the peak tractive effort that the rail conditions will permit.

Synchronizing control system for motor

Abstract: PURPOSE: To improve stability for setting accuracy and temperature variation and to regulate simply a circuit by processing signals with digital circuit. COPYRIGHT: (C)1976,JPO&Japio

Digital Electronics and Laboratory Computer Experiments

Abstract: Section I. Principles of Digital Logic.- to Experiments 1-5.- Experiment 1. DC Properties of Logic Elements.- Experiment 2. Complex Logic Functions from Simple Gates-Part 1.- Experiment 3. Complex Logic Functions from Simple Gates-Part 2.- Experiment 4. Other Useful Solid-State Devices.- Experiment 5. Properties and Use of Digital-to-Analog (DAC) and Analog-to-Digital (ADC) Converters.- Section II. Principles of Interfacing.- to Experiments 6-17.- Experiment 6. Computer-Controlled Logic Chip Test.- Experiment 7. Computer-Controlled Analog-to-Digital Conversion.- Experiment 8. Graphic-Display Experiments Using an X-Y Plotter and/or Storage Oscilloscope.- Experiment 9. Transient Decay Signal (Capacitor Discharge).- Experiment 10. Ensemble Averaging of Repeatable Noisy Signals.- Experiment 11. Multiplexing Using Triggerable Distinct Waveforms.- Experiment 12. Determination of Data-Acquisition Rate-The Nyquist Frequency.- Experiment 13. Computer-Aided Demonstration of the Photoelectric Effect.- Experiment 14. Computer-Assisted Potentiometric Titrations.- Experiment 15. On-Line Digital Computer Applications in Gas Chromatography.- Experiment 16. On-Line Digital Computer Applications for Kinetic Analysis.- Experiment 17. Computer-Controlled Colorimetry.- Section III. Appendices.- Appendix A. REAL-TIME BASIC (RTB) for Varian 620 Computers (Oregon/Nebraska Version).- Appendix B. Purdue real-time basic.- Appendix C. General-Purpose Interface and Logic Experiment Devices.- Appendix D. Equipment and Reagents List.- Appendix E. Schematics of Special Devices Used in This Book.- Appendix F. Detailed Description of Data-Acquisition Interface for Hewlett-Packard 2100-Family Computer Systems.- Appendix G. Interpreting Specifications Found on Digital Integrated-Circuit Data Sheets.- Appendix H. Operational Amplifiers.- Appendix I. Bibliography.

Analysis of load structures for current-mode logic

Abstract: Integrated circuit technology allows load characteristics to be shaped to the requirements of a circuit. Because it is possible to claim advantages for a variety of loads, a computer-aided analysis is used to relate the transient characteristics of a current-mode logic circuit to its static load line. A variety of load lines have been studied and an integrated diode-clamped-type load structure appears to offer the best static and dynamic characteristics.

Multi-function remote control ic

Abstract: An integrated digital circuit for a wireless remote control system employs a first counter to distinguish the frequency of actuating signals and a confidence counter for establishing a minimum duration for an actuating signal. Logic circuitry responsive to an externally applied voltage level controls the operation of a three stage binary counter and a flip-flop to selectively initiate a first mode utilizing two frequencies for control of an eight step bi-directional volume function and a second mode in which the same two frequencies control a four state cyclic volume function and a bi-stable picture control.

All digital delta to PCM converter

Abstract: A digital circuit for converting a delta modulated signal to a binary coded signal without producing an interim analog signal. The principal portions of the circuit are an up-down counter, a read-only memory the instantaneous output of which is controlled by the up-down counter, logic for driving the up-down counter in response to an incoming delta modulated signal, and a scanner for producing time-spaced pulses in response to the instantaneous outputs of the memory. A comparator is also included for driving the up-down counter relatively slowly to compensate for drift by ensuring that, over relatively long periods such as a few seconds, the output of the up-down counter oscillates around its mid-value.

Reliability Analysis of Logic Circuits

Abstract: An efficient algorithm is presented for computing the reliability matrix of a logic network whose components are characterized by a known probability of malfunctioning. Using the concept of path sensitizing, a graphical representation of error propagation is derived. Through the computation of Boolean path functions, the information provided by these graphs is put into a malfunction table from which the matrix entries are directly computed. The method not only offers computational efficiency but also provides further physical insight into the reliability problem.

Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers

Abstract: Logic-in-memory (LIM) organization allows central processor functions of computing systems to be combined with memory in regular arrays. The cells of these arrays can themselves be constructed regularly and economically using similar two-level emitter-function logic (EFL) structures. The structure is a development of current-mode logic and it permits the large-scale integration (LSI) realization of three levels of logic with similar silicon area and power dissipation to a single conventional emitter-coupled logic (ECL) gate. It also permits the realization of a D latch in a single structure. The capability of the structure is demonstrated in examples of LIM data transfer and sorting arrays.

Direct-coupled transistor-transistor logic: a new high-performance LSI gate family

Abstract: The direct-coupled transistor-transistor logic (DCT/SUP 2/L) family consists of a multiple-emitter AND gate and a NOR gate similar to direct-coupled transistor logic (DCTL). High speed for low power is obtained by limiting the voltage swing and using a low voltage power supply of about 2 V. Using a conservative, standard Schottky process, the DCT/SUP 2/L NOR gate has a delay of about 1 ns for 4-mW gate power. A computer-aided analysis shows that this is faster than the basic gates of emitter function logic (EFL), emitter-coupled logic (ECL), or Schottky transistor-transistor logic (T/SUP 2/L) with the same process and gate power. A comparison of actual arithmetic logic units shows that Schottky DCT/SUP 2/L is smaller and faster than ECL and Schottky T/SUP 2/L. The higher speed and density of DCT/SUP 2/L makes it a better large-scale integration (LSI) concept than the other logic families.

Power dissipation in planar digital circuits

Abstract: Continued miniaturization of digital electronic circuitry leads to increasing density of heat production and difficulty in removing the heat. Simple circuit considerations lead to an estimate of the limitations on performance that result from limits on heat transfer rates.

Computer-aided device modeling and design procedure for current hogging logic (CHL)

Abstract: Modeling of functional devices requires computer simulation of lateral and vertical device structure due to geometrical complexity. It not only must meet the requirements of network analysis programs, but also has to enable quantitative design. For the basic element of current hogging logic (CHL), the computer simulation of the two-dimensional situation has resulted in and given justification for a simple model approximating the injection performance and enabling quantitative design of even complex CHL circuits.

Design of an arithmetic element for serial processing in an iterative structure

Abstract: This paper describes the arithmetic and logic design of the digit processing logic of an arithmetic element. The arithmetic element is used in an iterative structure and arithmetic processing takes place serially on a digit by digit basis with the most significant digit first. Starting from the arithmetic specification of the digit processing logic, the arithmetic design (namely, the choice of number system, number representation and the digit algorithm) is developed. Algebraic and logic designs of the logic necessary to execute the digit algorithm and its implication for LSI implementation are discussed.

NENDEP-a simple n-channel MOS technology for logic circuits

Abstract: A relatively simple technology which uses six masking steps is presented. This technology is useful for fabricating logic circuits with depletion load devices. Threshold adjustment of the driver devices was obtained by a boron implantation. Self-alignment results from a phosphorus implantation. The technological procedure is described in detail and the motivation for the various processing steps is explained. A ring oscillator was fabricated to test the usefulness of the technology and to check the results of a computer-aided circuit analysis program.

Testability enhancement in digital system design

Abstract: A new way of employing hardware redundancy to reduce the number of tests for fault detection in both combinational and synchronous sequential circuits is investigated. An approach is presented for utilizing systematic redundancy to simplify design work. Models for PLM (programmable logic module) and CMM (controllable memory module) are depicted. Systematic design and detection procedures are described. Using these procedures, an easily testable circuit (for stuck faults) can be designed. In contrast to the earlier results on fault detection in logic circuit, two tests are needed to detect any stuck faults of combinational logic circuit. Four tests are necessary and sufficient to detect any stuck faults of elementary logic gates and the malfunction of flip-flops of synchronous sequential circuit using Delay flip-flops or trigger flip-flops.

Reliability of logic circuits with random inputs

Abstract: In a logic circuit, ‘ 1 ’ and ‘ 0 ’ are only Boolean symbols and actually represent two voltages A and B. In general, A and B are random variables and hence the input(s) as well as output(s) in a digital circuit are all random. In this note a statistical analysis of basic logic modules is presented. Examples are solved to illustrate the reliability evaluation of digital circuits.

A Microprocessors-Controlled DIC Test System*

Abstract: The objective of this paper is to bring forth the benefits that can be realized by using LSI microprocessors in test equipment and instrument applications. We will attempt to do this by describing the Qualifier* 901, which is a low-cost bench top digital integrated circuit tester controlled by an LSI microprocessor. First, we identify the scope of low-cost testers and describe the general principles of operation of such testers using fixed logic control. Then we describe the Qualifier 901, and finally, we point out the advantages gained by the usage of the intelligence of the microprocessor in Qualifier 901 versus fixed logic controlled testers.

Synchronization of digital circuits by bus triggering

Abstract: Data flow between multiple digital circuits having various internal clock rates is controlled by an asynchronous trigger bus. A trigger pulse is generated on the trigger bus when a trigger condition is simultaneously detected in two circuits desiring to communicate.

Binary counter circuit

Abstract: The configuration of a binary counter utilizing two superconducting junctions is described. Waveforms are shown for a divide-by-2N cascade of N stages, each comprising a binary counter and differentiator.