Showing papers on "Digital electronics published in 1976"

Digital Integrated Electronics

Abstract: This book represents the third generation of textbooks coauthored by H. Taub covering the general topics of pulse, switching, digital, and integrated circuits. The progression to the present book started in 1956 with Pulse and Digital Circuits, a text treating digital and switching circuits almost exclusively with vacuum-tube devices. A decade later the highly acclaimed and well-recognized book, Pulse. Digital, and Switching Woveforms, was issued in the second generation. In this volume, the importance of the transistor was emphasized and vacuum-tube circuits were presented only incidentally. Now, after another decade, the numerous advancements in integrated circuits have prompted the present work. The purpose of this text is to describe and analyze almost all of the basic integrated circuit building blocks from which digital circuits and systems are assembled. However, as noted in the Preface, Digital Integrated Electronics is intended as a continuation of Pulse, Digital, and Switching Woveforms rather than as a replacement. The reviewer agrees totally with this conclusion since the 1965 work provides a more thorough-and deeper treatment of fundamental semiconductor device operation than the present work. Use of the book presumes some background in semiconductor devices and circuits. The reviewer feels the book is so well written that a previous familiarity by the reader with semiconductor device characteristics, biasing, modeling, and amplifier analysis will be quite adequate for easy comprehension of the topics presented. The level and duration of the material are appropriate for a two-semester course coming in the late junior and senior years. Selected sections of the text are quite appropriate for a one semester or one quarter graduate level course dealing generally with hardware for instrumentation, timing, and data acquisition and storage techniques. For those having the suggested background with semiconductors, Chapter 1 is generally a review except that here these devices are treated from a switching mode viewpoint rather than the more conventional “linearized” amplifier model. The reader must make this change in viewpoint in order to appreciate the contents of the remaining chapters. Chapter 2 provides a further transition between the analog and digital viewpoints by first describing operational amplifier concepts, and then using this device as a vehicle for explaining the principles and operation of

Digital computer structure providing arithmetic and boolean logic operations, the latter controlling the former

Abstract: A digital computer of relatively simple and efficient structural organization which is capable not only of conventional arithmetic operations according to a program but also of (i) performing chained Boolean logic processing on any selected bit of any of various selected words held in memory, (ii) using the logic processing result by storing it at any selected bit location in any of various selected words held in memory, and/or (iii) causing different, predetermined instructions within a program to have their execution dependent upon the results of previously performed single bit logic processing. The logic processing is carried out in response to specially coded instruction words which may be randomly interspersed between conventional arithmetic instruction steps within an overall program. Existing registers and apparatus components necessary for conventional arithmetic operations are utilized in large measure to carry out the routing of signals to and from the logic processor, and very little added hardware is required to create the logic processing, storing, and dependent conditioning.

The Error Latency of a Fault in a Sequential Digital Circuit

Abstract: In digital circuits there is typically a delay between the occurrence of a fault and the first error in the output. This delay is the error latency of the fault. A model to characterize the error latency of a fault in a sequential circuit is presented.

A Per-Channel A/D Converter Having 15-Segment µ-255 Companding

Abstract: This paper describes a companded analog-to-digital (A/D) converter for voiceband signals that is simple and potentially inexpensive. The converter uses only 18 coarsely spaced analog levels. Fine resolution is obtained by oscillating between these levels at an increased speed and averaging the result over a Nyquist interval. The companding used in the converter is effectively the same as that of μ-255 pulse-code modulation (PCM). In the encoding process a one-bit code is generated at 256 000 samples/s. This 1-bit per sample signal can be transmitted and decoded directly, or a simple digital circuit will produce a 13-bit, 8-kHz linear PCM signal that can be compressed to 8-bit companded PCM format. In this paper the basic operation of the 1-bit coder is described and its performance when connected to a 1-bit decoder is illustrated. Methods for obtaining both linear and compressed PCM are then presented, and the properties of these PCM signals with respect to noise, gain tracking, and harmonic content are described. Relative insensitivity to circuit component variations, absence of analog gates, along with the need to generate only a few analog levels, make the coder especially well suited to integrated circuit realization.

An associative logic matrix

Abstract: While retaining the regular interconnection structure of read-only memory and programmable logic array devices, associative logic makes possible the efficient realization of multiple output, multilevel, combinational, and sequential networks. The extreme versatility of associative logic is provided by internal feedback and matrix segmentation, both characteristic features of the new device. Internal feedback permits networks to be realized in two or more logic levels without the need for external output-input connections. It also makes practical the formation of memory circuits within the matrix. Segmentation permits formation of collinear but functionally independent line segments, thereby improving the areal efficiency of monolithic devices. Consideration of associative logic proceeds from a review of logic implementation by means of memory devices and concludes with a description of an associative logic device developed using bipolar technology.

F/LOGIC - An interactive fault and logic simulator for digital circuits

Abstract: Digital simulators are becoming a standard and necessary CAD tool in the circuit design process. The acceptance of this design aid is a result of a number of factors, the predominant one being the over-whelming size and complexity of present day logic circuits and the requirement that a complete test plan be developed for these circuits. Another factor is that recent generation logic simulators have proven to be very flexible tools, capable of simulating very large circuits with a high degree of precision.

High-speed GaAs MSI

Abstract: A report on a process for the medium-scale integration of MESFET digital circuits on GaAs will be offered. Gate propagation delays < 100 ps with fanout of two and binary division from dc to 2 GHz have been achieved.

Asynchronous logic array

Abstract: An asynchronous logic array capable of directly implementing Petri net specification of digital systems is disclosed. The array can be used in general synthesis of asynchronous digital circuits and systems. The parallel nature of the array gives the realized systems the speed and other characteristics of hard wired circuits even though they are realized from a uniform logic array. The logic array is particularly suited for implementing control circuits and promises to extend the field of micro programming to asynchronous and parallel computers.

Energy per logic operation in integrated circuits: definition and determination

Abstract: A figure of merit for the comparison of different types of logic circuits on the basis of inverters is presented. This figure of merit-the minimum energy per logic operation-is equal to the product of the time period necessary for carrying out a logic operation times the power which is fed into the inverter during this time period. Methods for the determination of these terms by ring oscillator measurements and model calculations are considered. In contrast to the so-called `delay-power' product, these newly defined terms are independent of the kind of measurement, as for example the number of stages of the ring oscillator. Thus the minimum energy per logic operation is an intrinsic figure of merit which allows a qualitative comparison of different types of logic circuits on a physical basis.

Majority decision logic circuit

Abstract: A majority decision logic circuit has an odd number of elementary input signal circuits connected in parallel with a power source, each of the elementary input signal circuits being composed of a pair of P- and N-channel MOS transistors, the drains of the MOS transistors being interconnected to form an output terminal at the connection point and the gates being interconnected to form an input terminal at the connection point, all the output terminals of the elementary input signal circuits being connected together to form the output terminal of the majority decision logic circuit. A majority decision logic circuit has, in addition to the odd number of elementary input signal circuits, a plurality of logic circuits having their output terminals respectively connected to the input terminal of the elementary input signal circuits. A majority decision logic circuit comprises the elementary input signal circuits, the logic circuits and switching circuits, whereby the majority of outputs of a selected odd number of input signal circuits is decided. The abovesaid circuits can be formed with MOS transistors only, and are easily fabricated as an integrated circuit.

A Digital Receiver for Tone Detection Applications

Abstract: A digital circuit suitable for detection of tones in signaling applications is described. The amount of hardware required for the realization of the circuit is shown to be quite small. The circuit may be used for both analog and digital input signals. For analog signals, the necessary A/D conversion becomes very simple. Results of simulations on a digital computer are given that indicate the good performance of the circuit.

A CMOS monolithic 3&#189;-digit A/D converter

Abstract: A 3 1/2-digit A/D converter, combining linear and digital circuits on a CMOS monolithic integrated chip, providing auto-polarity, auto-zero, auto-calibration, high input impedance and low power dissipation, will be described.

A Programmable TV Receiver

Abstract: Digital circuit technique has begun to be applied to television receivers recently. Digital channel selection systems using a varactor tuner and remote control switches are two such examples.

A Numerical Expansion Technique and Its Application to Minimal Multiplexer Logic Circuits

Abstract: A method of realizing arbitrary combinational switching functions with multiplexers is derived. These circuits are divided in two classes where the first allows only uncomplemented variables as control inputs and the second has unrestricted inputs. The selected inputs to each multiplexer in the first class of circuits (tree circuits) are shown to be residue functions of the output function. Using this fact, it is demonstrated that many functional properties simplify realization procedures.

On Magnetic Bubble Logic Circuits

Abstract: This paper is concerned with the realization of logic functions by using two-input magnetic bubble logic elements. A magnetic bubble logic element is the multiple-output logic element whose number of ``1'' 's of the output is equal to that of corresponding input, and fanout of each output terminal of the element is restricted to one. In order to realize some functions, it is necessary to use the generators which correspond to constant-supplying elements. First, the number of generators which are necessary and sufficient to realize an arbitrary functions is obtained for a given set of elements. In particular, it is shown that an arbitrary function can be realized by using I B elements and at most two generators. Since the I B element is a universal element in the above sense and is considered to be rather easily realized by magnetic bubble interactions, the I B logic circuits are mainly discussed. The I B minimum circuit defined here is a circuit which consists of minimum number of generators and minimum number of I B elements. In the last half of this paper, it is shown that the minimum circuits of most functions have the characteristic circuit structure called ``1-4 form.''

Automatic generation of logic diagrams

Abstract: This paper identifies the basic notions involved in the automatic generation of logic diagrams. A system (ALDGS) for generating logic diagrams automatically is described and sample diagrams are given.

Modern Electronic Circuit Design

Abstract: Modern electronic circuit design , Modern electronic circuit design , مرکز فناوری اطلاعات و اطلاع رسانی کشاورزی

Integrating analog-to-digital converter with digital self-calibration

Abstract: With dual-slope integrating analogue-to-digital (A/D) converters, which are most frequently used for relatively low-speed conversion, the drift of the operational amplifier is a very critical factor in limiting their performance. The newly discovered digital self-calibration method which completely eliminates the drift problem, is more readily adaptable to ratiometric conversion, where the input and the reference voltages are of the same polarity. Some of the advantages are: no necessity of manual adjustments, the use of inexpensive operational amplifiers instead of costly units with no performance degradation for the temperature range limited only by digital circuits, and the possibility of A/D converters operating on a single power supply. As is the case with the basic dual-slope converters, no precision components of high absolute or relative accuracy are required.

Clocked digital counting system

Abstract: A system for processing cyclic signal pairs generated by an optical transducer to provide an accurate measurement of the displacement of one member with respect to a reference is suitable for determining weight by measuring spring scale tare deflection. The system includes a pair of comparator Schmitt trigger circuits for shaping pulse waveform signals. The pulse signals are processed by fully clocked digital circuits including edge discriminators to generate multiple count pulses which are processed by combination logic for direction determination. Further processing includes sign determination (positive-negative) and zero identification circuits to provide up and down pulses which are filtered and fed to up/down counter stages. Counter stage information is decoded for feedback control and processing logic indication. The zero identification circuit facilitates an unambiguous zero reference indication by skipping one count at zero to provide a display sign change indication on either side of zero prior to incrementing display counts to better define true zero as an edge or line between successive displays rather than as a zone. In an alternate embodiment, zero transition indicators are provided by feeding the count pulses directly to an updown counter and utilizing the most significant counter bit to invert the counter outputs upon a transition through actual zero.

On multiple fault analysis in combinational circuits by means of Boolean difference

Abstract: The Boolean difference has proved to be an elegant mathematical concept in the study of single faults of a stuck-at nature in combinational logic circuits. Recently Ku and Masson have extended this tool of analysis to cover all possible multiple-fault situations of logic circuits as well. In this letter, we have considered the problem of multiple-fault analysis through the use of the Boolean difference and derived suitable expressions that give the set of test-input codes for the detection of all possible multiple faults of combinational circuits. The developed expressions are compact and simpler, in general, and require much less computation to mire at the test vectors, particularly in cases where the multiple faults of interest are specified. These expressions, like those of Ku and Masson, are useful when only k simultaneous faults or all faults up to and including k faults are to be considered.

Digital transponder universal pulse assembly

Abstract: A combination of large scale integrated digital circuits for providing universally selectable decoding, encoding and over-interrogation control functions in a radar transponder. The circuits are implemented in semiconductor chip and hybrid circuit form and selection of desired functions may be accomplished by external switches, by jumper wiring or by custom designed printed circuit boards. The use of large scale integrated circuit techniques allows facilitation of multiple control functions without necessity of bulky assemblies or high power consumption.

High-speed programmable logic arrays in ESFI SOS technology

Abstract: Exploratory MOS programmable logic array (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated. These PLA's used dynamic logic gates and are built in epitaxial-silicon films on insulators (ESFI) silicon-on-sapphire (SOS) technology. The problems arising with the use of these dynamic gates in a two-stage logic array are discussed and different circuits are presented. The advantage of these circuits, in addition to their high speeds, is reduced power consumption, and the possibility to determine the number of feedback loops when the array is personalized. The features of the circuits are compared with each other with a complete PLA described in an earlier paper (see ibid., vol. SC-10, p.331 (1975)). The results gained from computer simulations agree reasonably well with the experimental results.

High Speed MOSFET Circuits Using Advanced Lithography

Abstract: During the last decade we have seen a dramatic increase in the complexity of silicon integrated circuit chips, particularly in memory. The n-channel FET technology is dominant in main memory and in lower performance logic and arrays (i.e., read-only memory and buffers) because of its higher circuit density and simpler processing, whereas bipolar transistor technology dominates for high-performance logic and arrays.

High-performance integrated injection logic: a microprogram sequencer built with I/SUP 3/L

Abstract: A microprogram sequencer is described. Its role in a systems environment is indicated. Functional details of the device including its instruction set are given. A newly developed technology isoplanar integrated injection logic (I/SUP 3/L) is discussed. Emphasis is placed on methods to achieve the required high performance. Details of the device structure and layout techniques are included. The resulting speed performance is indicated and general parameters are displayed.

Control logic for successive-approximation A/D converters

Abstract: Iterative building-block approach is used to minimize component count. Modular design has same logic structure for all bits.

Efficiency of Compact Testing for Sequential Circuits.

Abstract: : Compact testing uses random inputs to test digital circuits. Detection is achieved by comparison between some statistic property of the circuit under test, like the frequency of ones on the output line, and the same property for the fault-free circuit. This paper shows that compact testing can be used efficiently for sequential machines, although it has some inherent limitations. Synchronization is achieved by a long sequence of random inputs whose length is circuit dependent. However, for most sequential circuits, synchronization can be achieved in a few seconds. The great majority of failures inside the memory elements are easily detected even with short tests. Compact testing also detects most of the failures in the combinational parts. There, its efficiency is largely dependent upon the test length and also the characteristics of the random number generators. However, even the most subtle failures may be detected if the test has sufficient length. Some of the requirements and trade-offs to achieve efficient detection are presented.

Shift register with Gunn devices for multiplexing techniques in the gigabit- per-second range

Abstract: The subject of the paper is the monolithic integration of digital circuits on GaAs, a technique which is of significance for the subnanosecond range. Planar Gunn devices operated in the triggered-domain mode are used, and the technological requirements of such circuits are described. The limits of GaAs integrated circuits with regard to package density and bit rate are given. A dynamic shift register with Gunn devices for multiplexing and demultiplexing techniques in connection with p.c.m. transmission in the gigabit-per-second range is demonstrated. The technological level attainable at present is illustrated by a dynamic shift register consisting of five monolithically integrated Gunn devices. Experimental results with continuously operating circuits for a bit rate close to 2 Gbit/s are reported.