Showing papers on "Drain-induced barrier lowering published in 1976"

Field effect transistor for detection of biological reactions

Abstract: A field effect transistor including conventional source and drain electrodes employs, in the gate region, a layer of antibody specific to a particular antigen. An electrolyte solution such as 0.155 Normal sodium chloride atop the antibody layer provides a predetermined drain current versus drain voltage characteristic for the device. Replacement of the electrolyte solution with another electrolyte solution containing the antigen alters the charge of the protein surface layer due to the antigen-antibody reaction, thus affecting charge concentration in a semiconductor inversion layer in the transistor. The time rate of change of drain current thus provides a measure of the antigenic protein concentration in the replacement solution.

Finite-element simulation of GaAs MESFET's with lateral doping profiles and submicron gates

Abstract: Results of a two-dimensional finite-element simulation of a GaAs MESFET are presented. The simulation is used to determine the drain current and transconductance as well as the two-dimensional voltage, electron density, and electric-field distributions. It is shown that placement of a compensated doping region in the high electric-field region between gate and drain increases the drain current and transconductance by reducing the velocity-saturation effect. The transconductance and drain conductance of the MESFET in the saturation region of devices having different channel heights are compared with previous analysis.

Threshold voltage of narrow channel field effect transistors

Abstract: A new effect associated with Metal-Oxide-Silicon Field-Effect-Transistors (MOS-FET's) is presented in this paper. MOS-FET's show an increase of threshold voltage with decreasing ratio of channel width to gate depletion width. This narrow channel effect is explained by means of geometrical edge effects. With decreasing channel width the transition from the field oxide depletion region to the gate oxide depletion region becomes comparable to the gate width and cannot be neglected in the derivation of the threshold voltage equation. A theoretical model is given to explain the influence of decreasing channel width on the threshold voltage as well as on other electrical parameters. This theoretical model is in good agreement with experimental results given in this paper.

Drain conductance of junction gate FET's in the hot electron range

Abstract: A new model is proposed for the drain conductance of J-FET's in the hot electron range. The model is based on a physical picture revealed through two-dimensional numerical analysis. The two-dimensional analysis shows that the electron concentration changes gradually at the boundary of a depleted region which is defined by a conventional theory. Because of this gradual change, electrons can remain after the pinch-off and contribute to the drain current. Although the high electric field causes the electron velocity to saturate, the drift velocity vector rotates into the x axis (source-to-drain) with the increase in the drain voltage. The increase in the x component V x of the drift velocity gives rise to a small increase in drain current, that is, a finite drain conductance. The proposed model takes into account the above two essential features, gradual change in electron distribution, and the rotation of the velocity vector. This model is constructed in a single formulation which describes the current-voltage characteristics from the linear to the saturated drain-current region. Theoretical calculations agree quite well with the experiment on GaAs Schottky barrier gate FET's.

Silicon-on-sapphire mesa transistor having doped edges

Abstract: Instabilities in the leakage current and threshold voltage of a field effect transistor on an insulator substrate, at both room temperature and after operation at relatively high temperatures (150° C), are substantially reduced by selectively doping edge regions adjacent the transverse side surfaces of the channel region of the field effect transistor, wherein the breakdown voltage of the channel-to-drain junction is substantially increased Atoms are placed in these edge regions to provide therein a carrier concentration of at least 5 × 10 16 atoms-cm -3 of the opposite conductivity type to that of the source and drain regions The doped edge region extends partly across said channel region and extends fully across the side surface at the end of the source region

Double implanted planar mos device with v-groove and process of manufacture thereof

Abstract: An MOS transistor has a short vertical channel extending along the thickness of the transistor wafer and along the wall of a V-shaped groove, and has laterally disposed source, drain and gate electrodes on the same surface of the wafer. The channel is formed by a double ion implantation, or double diffusion operation. The source and drain electrodes are disposed on the same surface of the wafer and on opposite sides of the V-groove. The transistor has the speed capability of a bipolar transistor and high device density of a silicon gate MOS device, and has a shorter channel length (less than 1 micron) and higher punch-through voltage than has been previously available in a planar-MOS device.

Barrier height voltage reference

Abstract: A barrier height voltage reference includes two field-effect transistors which are substantially identical except for their gate-to-channel potential barrier characteristics and which are biased to carry equal drain currents at equal drain voltages. The resulting difference in potential between the gate contacts of the two field effect transistors produces a voltage reference which is substantially independent of operating point, supply potential, and temperature.

MOS field-effect transistor structure with mesa-like contact and gate areas and selectively deeper junctions

Abstract: An MOS field effect transistor includes a substrate in which source and drain regions are formed. A thick silicon dioxide layer is selectively formed on the upper surface of the substrate, so that in the resulting structure, the junction depth associated with the source and drain regions is selectively greater at contact locations and at the portions of the source and drain regions that are in contact with the active channel.

Self-aligned double implanted short channel V-groove MOS device

Abstract: A short-channel V-groove MOS transistor is provided having laterally disposed source, drain, gate dielectric on the same face of a lightly p-doped substrate. Using ion implantation, a heavily doped vertical channel layer is symmetrically provided below and between the drain and the source in the substrate and being self-aligned to the gate which is formed in the V-groove by a silicon dioxide layer and a conductor layer. Appropriate leads contact the gate conductor, the drain and the source. Such transistor can be incorporated in an integrated circuit to form an inverter circuit with a lateral depletion-mode V-MOS as a load transistor.

MOS input protection structure

Abstract: A breakdown preventing protection structure for an insulated gate field effect semiconductor device is disclosed for limiting input voltages to levels not substantially exceeding the supply voltage. A planar insulated gate field effect protection transistor is provided in series with the input. The protection transistor includes a source forming the circuit input, a drain connected to the gate of the device to be protected, and a gate electrode connected to the supply voltage which also supplies the device to be protected. A shunting protective diode may be included at the source of the protection transistor to limit negative input voltages to the diode threshold voltage and positive input voltages to the reverse avalanche breakdown of the protective diode. The protection circuit is particularly well suited to protect V-groove metal oxide semiconductor devices which have breakdown voltages well below breakdown voltages of conventional planar MOS transistor devices.

Dual gate MNOS transistor

Abstract: A dual gate MNOS memory transistor is disclosed The transistor includes drain and source regions of a first conductivity type formed in a substrate of a second conductivity type The region of the substrate between the drain and source regions forms the channel of the transistor First and second insulating layers forming a charged trapping structure overlie the channel region A first gate having a width less than the width of the channel overlies the central portion of the channel region A second gate, insulated from the first gate, overlies the first gate and the remainder of the channel region The threshold voltage of the transistor is shifted by selectively biasing the gates and the substrate High and low threshold voltage states are used to represent the two values of a digital signal

Complementary type insulated gate effect transistor

Abstract: PURPOSE:To obtain a C-MOS of a high speed and a high scale of integration by encircling the perimeters and bottom surfaces of the source, drain of the N, P channel transistors formign the C-MOS with the regions of an opposite conductivity type from the source, drain and of an impurity concentration higher than that of substrate.

Multiplication circuit with field effect transistor (FET)

Abstract: A drain resistor is connected to a drain electrode of a Field Effect Transistor (FET). One of the input signals to be multiplied is applied to the drain electrode through the drain resistor. The other input signal to be multiplied is applied to a gate electrode of the FET. An output proportional to the product of two signals appears across a resistor connected between a source electrode of FET and ground. In such an arrangement the resistance value of the drain resistor is so determined that the gradient of the characteristics of the drain current to the one input signal becomes almost equal to that of the characteristics of the drain current to the other input signal.

Analysis of field distributions in a GaAs m.e.s.f.e.t. at large drain voltages

Abstract: Electric-field distributions and carrier-density distributions in a GaAs m.e.s.f.e.t. at large drain voltages are investigated with a new analytical model, which takes account of the electron-drift-velocity saturation with negative differential mobility and the extension of a depletion layer towards the drain electrode.

A High Power MOS-FET with a Vertical Drain Electrode and Meshed Gate Structure

Abstract: A p-channel power MOS-FET is developed which exhibits 20A current, 3\mho transconductance and 85 V breakdown voltage in a 5×5 mm2 chip. The features of the device structure are a vertical drain electrode which enables to use most of the surface area for the source electrode and a meshed gate structure which makes it possible for the channel width per unit area to become twice as large as that of a conventional MOS-FET, thereby drain current of the device can be increased. The device with an offset gate structure was fabricated from an n on p+ epitaxial wafer by using the polysilicon gate and the ion implantation processes. The device does not show local current concentration, thermal runaway or second breakdown. Stable operation is obtained at ambient temperatures up to 180°C, which is attributed to a negative temperature coefficient of the drain current.

Light current constant voltage source using FETS - gives a constant voltage supply in easily integrated form using two series connected FETS

Abstract: The circuit consists of two matched series connected field effect transistors (M1, M2) each typically of P channel type. The drain of one transistor is connected to the unstabilised positive supply line (VDD) whilst its source is connected to the drain of the second transistor (M2). The source of this is earthed. The gates and the common drain source point in this circuit are commoned to produce the required constant voltage output. This is examined with the help of suitable characteristic curves and model equations and is illustrated with an application to an FET transistor clock generator circuit, for which it forms the voltage supply.

Low offset field effect transistor correlator circuit

Abstract: A low offset field effect transistor correlator circuit where one signal is applied to a balanced input through capacitors to the drain and source electrodes of a field effect transistor and having a second signal applied to the gate of the transistor. Low pass filters are connected to the source and drain, and the correlated input signals appear across resistors connecting the outputs of the filters.