Showing papers on "Electronic design automation published in 2000"

A model for types and levels of human interaction with automation

Abstract: We outline a model for types and levels of automation that provides a framework and an objective basis for deciding which system functions should be automated and to what extent. Appropriate selection is important because automation does not merely supplant but changes human activity and can impose new coordination demands on the human operator. We propose that automation can be applied to four broad classes of functions: 1) information acquisition; 2) information analysis; 3) decision and action selection; and 4) action implementation. Within each of these types, automation can be applied across a continuum of levels from low to high, i.e., from fully manual to fully automatic. A particular system can involve automation of all four types at different levels. The human performance consequences of particular types and levels of automation constitute primary evaluative criteria for automation design using our model. Secondary evaluative criteria include automation reliability and the costs of decision/action consequences, among others. Examples of recommended types and levels of automation are provided to illustrate the application of the model to automation design.

Cell-level placement for improving substrate thermal distribution

Abstract: The dramatic increase of power consumption in very large scale integration circuits has led to high operating temperature and large thermal gradient, thereby resulting in serious timing and reliability concerns. Temperature-tracking is thus becoming of paramount importance in modern electronic design automation (EDA) tools. In this paper we present two thermal placement tools for standard cell and macro cell design styles respectively. They are aimed at reducing hot spots in a design without compromising traditional design metrics such as area and wire length. We developed a compact substrate thermal model that can be used by the placer to calculate the temperature profile of a placement efficiently, or to convert the user-specified temperature constraint into the corresponding power distribution constraint as an alternative placement objective. As a result, our method is much more efficient than directly employing temperature profile simulation during the placement process. The simulation results show noticeable improvement of thermal distribution over the traditional placement algorithm, with little impact on area and wire length of the final layout.

Asynchronous design using commercial HDL synthesis tools

Abstract: New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Promotion of asynchronous design strongly depends upon the "level of service" delivered to the designer. Current asynchronous design tools require a significant re-education of designers and their capabilities are far behind synchronous commercial tools. One solution to these problems, which we advance in this paper, is to stick to a conventional design flow as closely as possible and to use commercial design tools as much as possible. The paper considers a particular subclass of asynchronous circuits (Null Convention Logic or NCL) and suggests a design flow which is completely based on commercial CAD tools. It argues about the trade-off between the simplicity of design flow and the quality of obtained implementations.

Design of mixed-signal systems-on-a-chip

Abstract: The electronics industry is increasingly focused on the consumer marketplace, which requires low-cost high-volume products to be developed very rapidly. This, combined with advances in deep submicrometer technology have resulted in the ability and the need to put entire systems on a single chip. As more of the system is included on a single chip, it is increasingly likely that the chip will contain both analog and digital sections. Developing these mixed-signal (MS) systems-on-chip presents enormous challenges both to the designers of the chips and to the developers of the computer-aided design (CAD) systems that are used during the design process. This paper presents many of the issues that act to complicate the development of large single-chip MS systems and how CAD systems are expected to develop to overcome these issues.

C-based SoC design flow and EDA tools: an ASIC and system vendor perspective

Abstract: This paper examines the achievements and future of system-on-a-chip (SoC) design methodology and design flow from the viewpoints of an in-house electronic design automation team of an application-specific integrated circuit and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC's complexity and the timing closure caused by deep-submicrometer technology. To solve these two problems, we propose a C-based SoC design environment that features integrated high-level synthesis (HLS) and verification tools. A HLS system is introduced using various successful industrial design examples, and its advantages and drawbacks are discussed. We then look at the future directions of this system. The high-level verification environment consists of a mixed-level hardware/software co-simulator, formal and semi-formal verifiers, and test-bench generators. The verification tools are tightly integrated with the HLS system and take advantage of information from the synthesis system. Then, we discusses the possibility of incorporating physical design features into the C-based SoC design environment. Finally, we describe our global vision for an SoC architecture and SoC design methodology.

Boolean satisfiability in electronic design automation

Abstract: Boolean Satisfiability (SAT) is often used as the underlying model for a significant and increasing number of applications in Electronic Design Automation (EDA) as well as in many other fields of Computer Science and Engineering. In recent years, new and efficient algorithms for SAT have been developed, allowing much larger problem instances to be solved. SAT “packages” are currently expected to have an impact on EDA applications similar to that of BDD packages since their introduction more than a decade ago. This tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem. Specifically, we highlight the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation, among others. In addition, we provide an overview of the algorithmic techniques commonly used for solving SAT, including those that have seen widespread use in specific EDA applications. We categorize these algorithmic techniques, indicating which have been shown to be best suited for which tasks.

Methodology server based integrated circuit design

Abstract: An environment for designing integrated circuits. Computers include browsers for displaying pages of forms, with the computers in communication with a methodology server and a compute server. The methodology server contains design methodologies accessed by the computers, with the design methodologies defining steps of designing and testing of integrated circuits. The computers or methodology server are also in communication with a compute server. The compute server executes electronic design automation tools as requested.

Common-mode failures in redundant VLSI systems: a survey

Abstract: This paper presents a survey of CMF (common-mode failures) in redundant systems with emphasis on VLSI (very large scale integration) systems. The paper discusses CMF in redundant systems, their possible causes, and techniques to analyze reliability of redundant systems in the presence of CMF. Current practice and results on the use of design diversity techniques for CMF are reviewed. By revisiting the CMF problem in the context of VLSI systems, this paper augments earlier surveys on CMF in nuclear and power-supply systems. The need for quantifiable metrics and effective models for CMF in VLSI systems is re-emphasized. These metrics and models are extremely useful in designing reliable systems. For example, using these metrics and models, system designers and synthesis tools can incorporate diversity in redundant systems to maximize protection against CMF.

Generating synthetic benchmark circuits for evaluating CAD tools

Abstract: For the development and evaluation of computer-aided design tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation tools, one could consider to actually generate synthetic circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. An indirect validation verifies that existing partitioning programs have comparable behavior for both real and synthetic circuits. The problems of accounting for timing-aware characteristics in synthetic benchmarks are addressed in detail and suggestions for extensions are included.

Space mapping optimization of microwave circuits exploiting surrogate models

Abstract: A powerful new Aggressive Space Mapping (ASM) optimization algorithm is presented It draws upon recent developments in both surrogate-based optimization and microwave device neuromodeling Our surrogate formulation (new to microwave engineering) exploits, in a novel way, a linear frequency-space mapping This is a powerful approach to severe response misalignments

An industrial view of electronic design automation

Abstract: The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation. The EDA business has profoundly influenced the integrated circuit (IC) business and vice-versa. This paper reviews the technologies, algorithms, and methodologies that have been used in EDA tools and the business impact of these technologies. In particular, we focus on four areas that have been key in defining the design methodologies over time: physical design, simulation/verification, synthesis, and test. We then look briefly into the future. Design will evolve toward more software programmability or some other kind of field configurability like field programmable gate arrays (FPGAs). We discuss the kinds of tool sets needed to support design in this environment.

A simple nonlinear model of the switched reluctance motor

Abstract: The paper presents a simple nonlinear model of the switched reluctance motor (SRM) which requires a minimum of precalculated or measured input data. Therefore, it is convenient for use in earlier stage of SRM design in order to minimize time for finding optimal configuration. Moreover, it is shown that this model produces accurate torque shape for given current, and accurate flux linkage-current relationships. This also provides reliable results in dynamic regime. The simulation and experimental results are compared for available three-phase 6/4 motor.

EDA in IBM: past, present, and future

Abstract: Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

Vhdl Design Representation and Synthesis

Abstract: Preface. 1. Structured Design Concepts. The Abstraction Hierarchy. Textual vs Pictorial Representations. Types of Behavioral Descriptions. Design Process. Structural Design Decomposition. The Digital Design Space. 2. Design Tools. CAD Tool Taxonomy. Schematic Editors. Simulators. The Simulation System. Simulation Aids. Applications of Simulation. Synthesis Tools. 3. Basic Features of VHDL. Major Language Constructs. 3. Lexical Description. Character Set. VHDL Source File. Data Types. Data Objects. Language Statements. Advanced Features of VHDL. The Formal Nature of VHDL. VHDL 93. Summary. 4. Basic VHDL Modeling Techniques. Modeling Delay in VHDL. The VHDL Scheduling Algorithm. Modeling Combinational and Sequential Logic. Logic Primitives. 5. Algorithmic Level Design. General Algorithmic Model Development in the Behavioral Domain. Representation of System Interconnections. Algorithmic Modeling of Systems. 6. Register Level Design. Transition from Algorithmic to Data Flow Descriptions. Timing Analysis. Control Unit Design. Ultimate RISC Machine. 7. Gate Level and ASIC Library Modeling. Accurate Gate Level Modeling. Error Checking. Multivalued Logic for Gate Level Modeling. Configuration Declarations for Gate Level Models. Modeling Races and Hazards. Approaches to Delay Control. 8. HDL-Based Design Techniques. Design of Combinational Logic Circuits. Design of Sequential Logic Circuits. Design of Microprogrammed Control Units. 9. ASICs and the ASIC Design Process. What is an ASIC? ASIC Circuit Technology. Types of ASICs. The ASIC Design Process. FPGA Synthesis. 10. Modeling for Synthesis. Behavioral Model Development. The Semantics of Simulation and Synthesis. Modeling Sequential Behavior. Modeling Combinational Circuits for Synthesis. Inferred Latches and Don't Cares. Tristate Circuits. Shared Resources. Flattening and Structuring. Effect of Modeling Style On Circuit Complexity. 11. Integration of VHDL into a Top-Down Design Methodology. Top-Down Design Methodology. Sobel Edge Detection Algorithm. System Requirements Level. System Definition Level. Architecture Design. Detailed Design at the RTL Level. Detailed Design at the Gate Level. 12. Synthesis Algorithms for Design Automation. Benefits of Algorithmic Synthesis. Algorithmic Synthesis Tasks. Scheduling Techniques. Allocation Techniques. State of the Art in High-Level Synthesis. Automated Synthesis of VHDL Constructs. Index. References. About the Authors. Index.

Quality of EDA CAD tools: definitions, metrics and directions

Abstract: In this paper we survey major problems faced by EDA tools in tackling deep submicron (DSM) design challenges like: crosstalk, reliability, power and interconnect dominated delay. We discuss the need for rethinking quality models used in EDA tools to allow early and reliable planning, estimation, analysis, and optimization. Key design quality metrics from a CAD tool perspective are surveyed, and methodologies and directions are proposed for the next generation design automation tools, intended to meet the challenges ahead. Ideas such as forward synthesis, incremental synthesis, system-level interconnect prediction and planning, and their implications on design quality design tool architecture, and design methodology are explored.

EDA challenges facing future microprocessor design

Abstract: As microprocessor design progresses from tens of millions of transistors on a chip using 0.18-/spl mu/m process technology to approximately a billion transistors on a chip using 0.10-/spl mu/m and finer process technologies, the microprocessor designer faces unprecedented Electronic Design Automation (EDA) challenges over the future generations of microprocessors. This paper describes the changes in the design environment that will be necessary to develop increasingly complex microprocessors. In particular, the paper describes the current status and the future challenges along three important areas in a design flow: design correctness, performance verification and power management.

Behavioral-synthesis electronic design automation tool business-to-business application service provider

Abstract: A business-to-business application service provider includes an Internet website and webserver with EDA-on-demand solutions for system-on-a-chip designers. Such website allows electronic designs in hardware description language to be uploaded into a front-end EDA design environment. A behavioral model simulation tool hosted privately on the webserver tests and validates the design. Such tool executes only in the secure environment of the business-to-business application service provider. The validated solution is then downloaded back over the Internet for a pay-per-use fee to the customer, and in a form ready to be placed and routed by a back-end EDA tool. Such validated design solutions are also downloadable to others in exchange for other designs, or available in technology libraries. The intellectual property created can be re-used, sold, shared, exchanged, and otherwise distributed efficiently and easily from a central for-profit clearinghouse.

System level design using C

Abstract: This paper discusses the use of C++ for the design of digital systems. The paper distinguishes a number of different approaches towards the use of programming languages for digital system design and will discuss in more detail how C++ can be used for system modeling and refinement, for simulation, and for architecture design.

Measurement, analysis and modeling of real-time source data traffic in factory communication systems

Abstract: In the performance evaluation and design of communication systems for distributed automation systems the almost realistic modeling of the data traffic of automation devices plays a decisive part. Therefore the real-time communication behaviour of a high-grade automated installation in the discrete manufacturing is evaluated. Selected communication requirements are analysed and transferred to a analytic model. This model finally is validated.

METRICS: a system architecture for design process optimization

Abstract: We describe METRICS, a system to recover design productivity via new infrastructure for design process optimization. METRICS seeks to treat system design and implementation as a science, rather than an art. A key precept is that measuring a design process is a prerequisite to optimizing it and continuously achieving maximum productivity. METRICS (i) unobtrusively gathers characteristics of design artifacts, design process, and communications during the system development effort, and (ii) analyzes and compares that data to analogous data from prior efforts. METRICS infrastructure consists of (i) a standard metrics schema, along with metrics transmittal capabilities embedded directly into EDA tools or into wrappers around tools; (ii) a metrics data warehouse and metrics reports; (iii) data mining and visualization capabilities for project prediction, tracking, and diagnosis. We give experiences and insights gained from development and deployment of METRICS within a leading SOC design flow.

Method for delay-optimizing technology mapping of digital logic

Abstract: A delay-optimizing technology-mapping process for an electronic design automation system selects the best combination of library devices to use in a forward and a backward sweep of circuit trees representing a design. A technology selection process in an electronic design automation-system comprises the steps of partitioning an original circuit design into a set of corresponding logic trees. Then, ordering the set of corresponding logic trees into an ordered linear list such that each tree-T that drives another ordered tree precedes the other ordered tree, and such that each ordered tree that drives the tree-T precedes the tree-T. Next, sweeping forward in the ordered linear list while computing a set of Pareto-optimal load/arrival curves for each of a plurality of net nodes that match a technology-library element. And, sweeping backward in the ordered linear list while using the set of Pareto-optimal load/arrival curves for each of the net nodes and a capacitive load to select a best one of the technology-library elements with a shortest signal arrival time. Wherein, only those net nodes that correspond to gate inputs are considered, and any capacitive loads are predetermined.

Pattern-matching for transistor level netlists

Abstract: A single pattern-matching algorithm which allows both exact and inexact pattern-matching so that transistor-level design automation tools can reliably perform timing analysis, electrical rules checking, noise analysis, test pattern generation, formal design verification, and the like prior to manufacturing custom logic. The user (circuit designer) specifies which of each of the pattern external nets may be matched inexactly (attached to Vdd, attached to GND, and shorted to other external nets), with the remainder of the pattern external net connections being matched using exact isomorphism constraints. The method described herein achieves a substantial reduction in the number of patterns which circuit designers must generate, and altogether eliminates the need for an exponential number of patterns by providing an inexact pattern matcher to circuit designers. It further provides rooted sub-graph isomorphism so that a user can query whether a particular pattern is embedded at a particular location in the main circuit design, utilizing inexact sub-graph isomorphism

Method for fabricating integrated circuits

Abstract: Functional and geometrical sub-components of logic circuits are defined and used in the design of integrated circuits to facilitate the transformation of an integrated circuit design for fabrication at foundries with different design rules.

A robust genetic algorithm for structural optimization

Abstract: The focus of this paper is on the development and implementation of a methodology for automated design of discrete structural systems. The research is aimed at utilizing Genetic Algorithms (GA) as an automated design tool. Several key enhancements are made to the simple GA in order to increase the efficiency, reliability and accuracy of the methodology for code-based design of structures. The AISC-ASD design code is used to illustrate the design methodology. Small as well as large-scale problems are solved. Simultaneous sizing, shape and topology optimal designs of structural framed systems subjected to static and dynamic loads are considered. Comparisons with results from prior publications and solution to new problems show that the enhancements made to the GA do indeed make the design system more efficient and robust.

A practical approach to the synthesis of arithmetic circuits using carry-save-adders

Abstract: Carry-save-adder (CSA) is one of the most widely used types of operation in implementing a fast computation of arithmetics. An inherent limitation of the conventional CSA applications is that the applications are confined to the sections of arithmetic circuit that can be directly translated into addition expressions. To overcome this limitation, from the analysis of the structures of arithmetic circuits found in industry, we derive a set of simple, but effective CSA transformation techniques other than the existing ones. These are 1) optimization across multiplexers, 2) optimization across design boundaries, and 3) optimization across multiplications. Based on the techniques, we develop a new timing-driven CSA transformation algorithm that is able to utilize CSA's extensively throughout all circuits. Experimental data for practical testcases are provided to show the effectiveness of our algorithm.

Automatic process-oriented control circuit generation for asynchronous high-level synthesis

Abstract: As an asynchronous design style becomes popular, the request for asynchronous high-level synthesis (AHLS) tools is increasing continuously. In this paper, a method, so called process-oriented method, which generates distributed asynchronous control circuits automatically in a hierarchical and systematic manner is suggested as part of an AHLS tool. Experimental results show that the suggested method is efficient in the aspects of area and performance of derived control circuits.