Showing papers on "Electronic packaging published in 1989"

Polymers for Electronic Applications

Abstract: The object of this book is to review and to discuss some important applications of polymers in electronics. The first three chapters discuss the current primary applications of polymers in semiconductor device manufacturing: polymers as resist materials for integrated circuit fabrication, polyimides as electronics packaging materials, and polymers as integrated circuits encapsulates.

Polymeric materials for electronics packaging and interconnection

Abstract: Polymers play an increasingly important role in the construction of integrated circuitry and many electronic devices. This new volume provides an overview of this important topic with an emphasis on the chemical and materials properties of polymers for electronic packaging. Its 39 chapters cover a broad spectrum of topics in four general areas: physical chemistry of materials, properties and applications of encapsulants, properties and applications of gels, and printed circuit board substrates and materials for circuit board substrates. Also includes a review of the marketing trends that drive packaging technology.

Low-expansion MMCs boost avionics

Abstract: Metal-matrix composites (MMCs) offer attractive properties for electronic packaging in aerospace applications

Microelectronic packaging technology : materials and processes : proceedings of the 2nd ASM International Electronic Materials and Processing Congress, Philadelphia, Pennsylvania, USA, 24-28 April 1989

Abstract: Proceedings of the Second ASM International Electronics and Processing Congress held in Philadelphia, April 1989. More than 50 contributions present the recent microelectronic R&D and engineering efforts toward higher density and higher speed electronic packaging methodologies and fabrication techno

Ceramic Materials for Electronic Packaging

Abstract: The paper reviews ceramic materials that are used or can be used in electronic packaging. Main attention is given in relatively new packaging materials such as highly thermal conductive AlN and SiC (BeO-doped) or low-firing cordierite and spodumene glass-ceramics. Application of sol-gel processes in preparation of ceramic powders is discussed.

High-performance VLSI through package-level interconnects

Abstract: A packaging technique utilizing controlled-collapse chip connection to integrate two existing high-performance VLSI devices into a single pin-grid-array (PGA) package is described. The design and layout of the multilayer ceramic package, electrical and thermal performance, and future enhancements are discussed. The performance of the package is compared to that of a companion two-cavity, wire-bonded evaluation package. The potential use of the packaging technique as a substitute for wafer-level integration is examined. >

Mechanical considerations for reliable interfaces in next generation electronics packaging

Abstract: The author reviews some basic mechanical design approaches available to assure reliable interfaces within and between packaging levels in the chip, package, and circuit-board assemblies. While the approaches can be applied to traditional circuit-board and hybrid assemblies emphasis is placed on the hybrid wafer-scale integration multichip module packaging technologies. It is concluded that a combination of recently available packaging materials of improved properties, recently developed improved analysis techniques, and the advantages of the new hybrid wafer-scale integration technology offers the opportunity to design significantly improved reliability into the next generation of military electronic equipment. Additionally, the equipment size and weight can be reduced significantly. A dramatic demonstration of the miniaturization possible with these technologies was made on a miniaturized version of a GPS (global positioning system) receiver. >

Device for transporting packaging material to a packaging machine

Abstract: 2.1. The supply of high-performance packaging machines with web-shaped wound packaging material (reels) and/or prefabricated blanks has hitherto necessitated a considerable amount of manual labour. The sometimes appreciable deadweight of the packaging material primarily has an adverse effect here. 2.2. In order to allow a virtually fully automatic feeding of the packaging machines with packaging material, a conveyor track (31) leading to the individual consumption points on the packaging machines is arranged above the packaging machines ("overhead"). Individual reels (26, 27, 28) or blanks (82) stacked in cassettes (84) are respectively transported along this conveyor track (31) by means of material conveyors (41). These are equipped with respective material holders (44) which consist solely of rigid immovable supporting members for the reels or cassettes (84). The feed and unloading of these material holders (44) take place automatically as a result of a corresponding relative movement of feeding and unloading members.

Materials for high–density electronic packaging and interconnections in the higher packaging levels

Abstract: This paper concentrates on the materials requirements anticipated for future packaging strategies of electronic components beyond the 1st level package. This includes Wafer Scale Integration (Level 0), hybrid assembly of bare chips in multichip modules (Level 1.5), printed wiring board (PWB) assembly, including surface mount (Level 2), and higher levels (connectors, mother boards, and cables). Furthermore, high-performance digital VLSI logic packaging only is addressed, to the exclusion of memory, analog, and power circuitry (except power supplies).

Integrated optoelectronics-to-VLSI packaging technology

Abstract: A generic integrated optoelectronic-to-VLSI packaging technology using silicon substrate and etched silicon optical submount has been developed and demonstrated. The miniature silicon submount that interfaces optical fiber with the optoelectronic component and the silicon substrate containing VLSI circuits is fabricated with double-sided nonplanar photolithography and anisotropic etching techniques. The advantages of this technology are: ability to interface optical information and circuits with VLSI in a single package; precision controlled capacitive, resistive, and inductive loading; minimized distance between optoelectronic components and electronic ICs, and between decoupling capacitors and active circuits; self-aligned fiber insertion; and highly automated manufacturing. These advantages translate to higher functional density and performance at a lower cost than conventional optoelectronic packaging technologies. >

Acetylene-Terminated Polyimide Composites for Advanced Electronic Packaging Applications

Abstract: Surface mount technology (SMT) is an electronic packaging technology wherein the leads of electronic components are soldered directly to metallized pads on the surface of a printed circuit board (PCB). The SMT with leadless ceramic chip carriers (LCCCs) is used to design, fabricate, and assemble affordable, high-speed, high-density electronic modules with reduced size and weight and improved electrical performance. In surface mount devices, the LCCCs are soldered directly onto the fabric composite PCB substrate. New high-performance composite substrate materials must be developed to take full advantage of SMT. Fabricating a PCB that will perform reliably throughout its intended life is also an increasingly important requirement, especially if the goal is to satisfy the high reliability required in military applications. Consequently, SMT is driving the development of PCB substrate materials with improved thermal and electrical properties. In our continuing effort to meet these military demands, we evaluated high-temperature resistant/high-performance acetylene-terminated polyimide composites for use in SMT PCBs. This paper focusses on the processing and on the thermal, thermomechanical, and dynamic mechanical properties data developed for these acetylene-terminated polyimide composites for their potential evaluation as PCBs. The characterization includes such properties as in-plane coefficient of thermal expansion (CTE), out-of-plane CTE, and glass transition temperature (Tg), which determine the solder joint reliability, plated-through-hole (PTH) reliability, and dimensional stability.

Investigation into Thermal Conductivity of Composite Materials for Electronics Packaging

Abstract: As part of a two-year investigation into the use of composite materials for military electronic equipment enclosures, the thermal conductivity of composite materials was determined by testing and predicted by an analytical technique. The objectives included identifying methods of improving thermal conductivity of composites and utilization of a prediction method. The comparative test and the Lewis-Nielson semitheoretical prediction methods were used and are described. The materials evaluated were a thermoplastic polymer with several discontinuous filler types. The analytical predictions were in good agreement with the test results except at high filler levels, but do not take into account anisotropic material properties or temperature effects. Test and prediction results are presented.

Ceramic Fiber Composites for Electronic Packaging: Thermal Transport Properties

Abstract: The thermal diffusivities and specific heats of several polymer matrix composites containing ceramic Fiber FP [1] and AIN fibers were measured between 20 K and 300 K. The anisotropic thermal conductivities inferred are related to specific fiber geometries and the thermal conductivities of the composite components. The high in-plane conductivities at 125K suggest possible applications for high-Tc, superconductor electronic packaging.

Effect of Humidity and Electronic Packaging Exhalates on the Performance of some Active and Passive Components used in an Electronic Equipment

Abstract: The performance of some commercial P-N Junction diodes, some ceramic capacitors and some resistors has been tested under moisture (RH 60% to 95%) and various exhalate vapours (HCl, HNO3., HCOOH, CH3 COOH, NH3 and SO2) which are generally released by the electronic packaging materials. The ideality factor of the diode changes after exposure, the change being more at higher exposure times. The organic acid vapours degrade the devices the most. Silicon diodes, in general, are found to be less sensitive to the humidity and exhalate vapours as compared to Germanium and Indium Antimonide diodes. The presence of oxide layer on the surface of silicon diodes may be responsible for the smaller degradation effect.

Packaging of VLSI devices

Abstract: VLSI technologies are characterized by a drastic reduction of component size and the economical production of large-area chips. Electrical and geometrical characteristics of modern VLSI chips require a synchronized progress in the development of chip and board technologies. Furthermore, alternative hierarchies within electronic systems, such as the application of multichip modules or microsystems, must be considered. The geometrical and electrical chip parameters are discussed, and the requirements for future packaging technologies are summarized. >