Showing papers on "Error detection and correction published in 1983"

Theory and practice of error control codes

Abstract: To understand the theoretical framework upon which error-control codes are built and then Algebraic Codes for Data Transmission By Richard E. Blahut. Hamid Jafarkhani, “Space-Time Coding: Theory and Practice”, Cambridge. Textbook, Richard E. Blahut, Algebraic Codes for Data Transmission. Bibliography Peter Sweeney, Error Control Coding: From Theory to Practice Juergen. 2Automatic Control Laboratory, ETH Zurich, Switzerland several examples to illustrate the performance of the approximation scheme in practice. Information theory says that there exists operational quantities called channel (9) Richard E. Blahut, “Computation of channel capacity and rate-distortion functions,” IEEE.

Automatic-repeat-request error control schemes

Abstract: ERROR DETECTION incorporated with automatic-repeatrequest (ARQ) is widely used for error control in data communications systems. This method of error control is simple and provides high system reliability. If a properly chosen code is used for error detection, virtually error-free data transmission can be attained. This paper surveys various types of ARQ and hybrid ARQ schemes, and error detection using linear block codes.

S-Shaped Reliability Growth Modeling for Software Error Detection

Abstract: This paper investigates a stochastic model for a software error detection process in which the growth curve of the number of detected software errors for the observed data is S-shaped. The software error detection model is a nonhomogeneous Poisson process where the mean-value function has an S-shaped growth curve. The model is applied to actual software error data. Statistical inference on the unknown parameters is discussed. The model fits the observed data better than other models.

A Modified Selective-Repeat Type-II Hybrid ARQ System and Its Performance Analysis

Abstract: The hybrid ARQ scheme with parity retransmission for error control, recently proposed by Lin and Yu [1], [2], is quite robust. This scheme provides both high system throughput and high system reliability. In this paper, a modified Lin-Yu hybrid ARQ scheme is presented. The modified scheme provides a slightly better throughput performance than the original Lin-Yu scheme; however, it is more flexible in utilizing the error-correction power of a code. The modified scheme can be incorporated with a rate 1/2 convolutional code using Viterbi decoding. Furthermore, the pure selectiverepeat ARQ is a degenerated case of the modified scheme in selective mode. Lin and Yu analyzed their scheme only for a receiver buffer of size N where N is the number of data blocks that can be transmitted in a round-trip delay interval. No analysis for other buffer sizes was given. In this paper, the throughput performance of the modified Lin-Yu scheme is analyzed for any size of receiver buffer. Consequently, the throughput efficiency of the pure selective-repeat ARQ for any receiver buffer size can be obtained. We also show that the modified scheme achieves the same order of reliability as a pure ARQ scheme.

Reed-Solomon error correction apparatus

Abstract: Disclosed is a Reed-Solomon error correction apparatus which is programmable to perform several distinct error correction functions. The apparatus performs the following functions: encoding, error detection, syndrome generation, burst error trapping, and Chien searching.

Bit steering apparatus and method for correcting errors in stored data, storing the address of the corrected data and using the address to maintain a correct data condition

Abstract: In a computer system, an apparatus detects the existence of an error in data retrieved from memory, corrects the erroneous data, and takes steps to maintain the correct condition of the data. In taking these steps, when the erroneous data is corrected, the corrected data is stored in a spare portion of the memory; however, the address of the corrected data in memory is recorded in a bit steering array, a physically separate memory of much smaller size. The bit steering array stores a plurality of such addresses. When an incoming read request signal is generated, it simultaneously energizes the memory and the bit steering array. In response to the read request signal, the bit steering array develops an output signal indicative of the address of the corrected data and representative of the identity of the erroneous data. In response to the read request signal, data, including the erroneous data, is read from memory. In addition, the corrected data is read from the spare portion of the memory. However, in response to the output signal from the bit steering array, the erroneous data is replaced or exchanged with the corrected data. In the case of a double bit error, one bit is corrected in the manner just described. The other bit is corrected in an error correction code matrix, which is designed to correct single bit errors.

Partitioned linear block codes for computer memory with 'stuck-at' defects

Abstract: Linear block codes are studied for improving the reliability of message storage in computer memory with stuck-at defects and noise. The case when the side information about the state of the defects is available to the decoder or to the encoder is considered. In the former case, stuck-at cells act as erasures so that techniques for decoding linear block codes for erasures and errors can be directly applied. We concentrate on the complimentary problem of incorporating stuck-at information in the encoding of linear block codes. An algebraic model for stuck-at defects and additive errors is presented. The notion of a "partitioned" linear block code is introduced to mask defects known at the encoder and to correct random errors at the decoder. The defect and error correction capability of partitioned linear block codes is characterized in terms of minimum distances. A class of partitioned cyclic codes is introduced. A BCH-type bound for these cyclic codes is derived and employed to construct partitioned linear block codes with specified bounds on the minimum distances. Finally, a probabilistic model for the generation of stuck-at cells is presented. It is shown that partitioned linear block codes achieve the Shannon capacity for a computer memory with symmetric defects and errors.

Correction and monitoring of transient errors in a memory system

Abstract: A microcomputer system in which transient errors occurring in a memory are corrected and logged by a program controlled microprocessor and a simple error detection and correction circuit. When an error occurs in information readout of a memory location, the error detection and correction circuit is responsive to the error to (1) store the address of memory block containing the location, (2) store the type of error, and (3) generate an error signal which interrupts the microprocessor. In response to the interrupt, the microprocessor enters an interrupt routine to: (1) identify the block of memory locations in which the error occurred, (2) determine the type of error, (3) reaccess each memory location of the memory block to effect a rereading thereof, (4) receive each word of readout information, corrected if necessary by the error detection and correction circuit, (5) rewrite each of the received words back into the memory at the proper reaccessed memory location, (6) read out each of the rewritten locations to determine if any error is still present which would indicate a permanent rather than a transient error, and (7) finally, log the error in an error rate table if it is a transient error.

Hybrid ARQ error control using sequential decoding

Abstract: An important feature of ARQ sequential decoding is that a very low undetected error probability can be achieved without increasing significantly the complexity of decoding. Several ARQ sequential decoding algorithms based on the stack algorithm are considered. Analysis is done for a memoryless channel with noiseless feedback, and the emphasis is on evaluating the undetected error probability and the maximum throughput attainable with each algorithm. A time-out algorithm is analyzed and the parameters optimizing the performance of this algorithm are found. A new algorithm called the slope control algorithm, capable of achieving a better throughput than the time-out algorithm, is proposed. The algorithm is analyzed using random coding arguments, and the parameters maximizing the throughput for various conditions are found. All theoretical results are verified by computer simulation for a binary symmetric channel.

The Design of Error Checkers for Self-Checking Residue Number Arithmetic

Abstract: During the last few years residue number (RNS) arithmetic has gained increasing importance for providing high speed fault tolerant performance in dedicated digital signal processors. One factor that has limited the use of redundant RNS theory in practice is the hardware complexity of the error checker. This paper presents a mathematical analysis of the error correction algorithm which suggests a new design with considerably reduced hardware complexity. A hardward architecture for a high speed pipelined error checker is proposed.

Concurrent Error Detection in Multiply and Divide Arrays

Abstract: A method proposed for concurrent error detection in ALU's is used in the design of multiplier and divider arrays. This method, called recomputing with shifted operands (RESO), can detect all errors caused by failures confined to a cell of the cellular array. The assumption that the failures are confined to a small area of an integrated circuit and the precise nature of the failures is not known is very applicable to VLSI circuits. RESO uses time redundancy for error detection and requires only a small increase in the hardware of a multiply and divide array.

Combined source and channel coding for variable-bit-rate speech transmission

Abstract: Motivated by potential applications to mobile radio, we studied variable-bit-rate speech communication through Gaussian-noise and Rayleigh-fading channels. For convenience we used a constant signaling rate of 32 kb/s and adjusted the source-coding and channel-coding rates in response to changing transmission quality. When the channel quality was good enough, we used all 32 kb/s for speech transmission. When the channel quality was lower, we reduced the source rate to 24 or 16 kb/s and introduced channel coding to control distortion due to transmission errors. We concentrated on specific source and channel codes that could be implemented with hardware of modest complexity. The source code was embedded differential pulse code modulation, which is amenable to variable-bit-rate operation and economical to implement. For error control we introduced punctured convolutional codes and a Viterbi decoder with only 16 states. Although the source/channel codec was simple, it offered good performance. Speech quality was at the level of normal telephony when the channel was good; the error-correcting codes extended by up to 13 dB the range of channel signal-to-noise ratios that support adequate quality. Our performance estimates were based on a new analysis of transmission errors in embedded differential pulse code modulation and on computer simulations of speech transmission through fixed and fading channels.

Go-Back-N ARQ Schemes for Point-to-Multipoint Satellite Communications

Abstract: The conventional go-back- N ARQ is modified so as to be applicable to point-to-multipoint communication by using a control block that indicates the occurrence of retransmission to all the receivers. This paper also presents a "tandem error control scheme," in which the up-link and the down-links use separate go-back- N ARQ's. The throughput efficiency of the tandem go-back- N ARQ is analyzed. Specifically, the mathematical formula for the throughput efficiency is obtained for cases in which there is a single receiver. The throughput efficiencies of these schemes are also evaluated by simulation.

Attitudes and Preferences of ESL Students to Error Correction

Abstract: This article presents the findings of a survey of ESL students' attitudes toward and preferences for the correction of spoken errors by native speaker friends. The 418 subjects reported generally positive attitudes toward error correction and claimed to prefer even more correction than their friends did. They saw correcting errors as facilitating—even being necessary—for the improvement of their oral English.

Error detecting and correcting memories

Abstract: A system and procedure for organizing a digital memory by incorporating error correcting circuitry and error detecting circuitry into the memory based on the graph of an error-correcting code in tree form. The error detecting circuitry detects a variety of multiple errors in stored binary bits, and in addition detects certain failures in the memory circuitry. One embodiment coordinates a series of independent memory subarrays in an interdependent manner so that all of the bits in an arbitrarily large memory are organized so as to form several long code words in a single-error-correcting double-error-detecting code. Another embodiment organizes all of the bits in the memory so that they form a single codeword in a double-error-correcting, triple-error-detecting code derived from a projective plane. Coding efficiency is high: in the cases of a 256K memory, including the required parity check bits, only (33/32) 256K bits, approximately, must be stored. Single error correction can take place at the time of a read with very little additional delay compared to that of a normal irredundant memory.

Error-Correcting Codes with Byte Error-Detection Capability

Abstract: Single error-correcting and double error-detecting codes capable of detecting all single byte errors are important for practical applications. They can be used to enhance the reliability and the data integrity of computer memory systems. Here we present the construction of these codes. The construction techniques are developed from the theory of orthogonal flats in finite Euclidean geometry.

Method of correcting for errors in radar imaging

Abstract: A method of correcting for focus errors or higher order errors, or various combinations thereof, in the final image effected by the processing of a radar. With regard to correcting focus errors, the method coherently combines the signal focus data from selected target time histories derived by a first stage processor of the radar to form a complex signal representative of the average focus error of the radar image. From the phase of the complex signal is derived a set of focus error compensation signals which are used to compensate for focus errors in the target time histories derived by the first stage processor. With regard to the higher order error correction, the method coherently combines the signal data from selected target time histories derived by the first stage processor by shifting the phase and frequency centroids of each complex signal thereof to a common value. Light filtering may be provided to remove wide band noise with a linear phase filter. Accordingly, the coherently combined and filtered error correction signals are point wise inverted and thereafter used to correct the complex signals of the time histories derived by the first stage processor. An additional embodiment is provided to permit both the focus error and higher order error correction methods to be performed at an intermediate stage in the radar processing.

Automatic frame synchronization recovery utilizing a sequential decoder

Abstract: A digital communication system including an encoder and decoder for the transmission of digital information over a transmission medium, the system having automatic frame synchronization and error correction requiring a minimum of tansmission bits and decoding time. The encoder processes a data stream and generates a transmission bit stream of N bits using convolutional encoding, autosynchronization sequence combining, and bit interleaving. The multi-phase sequential decoder decodes the received coded data, corrects transmission errors and automatically achieves frame synchronization from P selected phases of the received data. This is accomplished by selecting the phase of the received data with the best metric, bit de-interleaving, removing the autosynchronization sequence and comparing the received data of the selected phase with the extended code word subsets from the node having the best metric. The decoder then selects a new best metric node and phase in an iterative process until the decoding operation terminates with either valid decoded data upon reaching a terminal node or a code word erasure due to computation or memory overflow. Thus the decoder simultaneously searches for the correct phase and decoded data by iteratively maximizing the code word metric in one decoding operation.

Reed-Solomon error detecting and correcting system employing pipelined processors

Abstract: Apparatus and methods are disclosed for providing on-line error detection and correction of errors in an optical disk storage system using Reed-Solomon decoding techniques. An implementation is employed which divides the Reed-Solomon decoding process into a sequence of well defined steps requiring a minimum of inter-step parameter transfers. These steps are implemented by a plurality of processors operating in a pipelined manner.

Linear block codes for error detection (Corresp.)

Abstract: The probability of undetected error of linear block codes for use on a binary symmetric channel is investigated. Upper hounds are derived. Several classes of linear block codes are proved to have good error-detecting capability.

Code error detection and correction method and apparatus

Abstract: Method and apparatus for detecting and correcting code errors in processing a digital signal such as a digital audio signal are disclosed. An error word correcting parity word generated from a plurality of data words is added to the plurality of data words to form a first frame, and the data words and the parity word of a plurality of different first frames are distributed in a second frame and a plurality of additional parity words for detecting and correcting error words in the second frame are added to the second frame to form a Reed-Solomon code. The code errors are detected and corrected using this code. A code error rate counter is provided, and when an output of the code error counter exceeds a predetermined count, the code error correction is inhibited for a predetermined time period or until the code error rate reaches a second predetermined code error rate.

Differential PSK System with Nonredundant Error Correction

Abstract: Theoretical analysis and experimental results for a DPSK system with nonredundant error correction are described. The error correction capability of the proposed demodulation method is achieved without utilizing additional bandwidth. The demodulator utilizes outputs of differentially coherent detectors that employ the received signal delayed by two or more time slots as references. These outputs are shown to be the parity check sums of two or more conSecutive outputs of the conventional detector under noise-free conditions. The error rate performance of the proposed demodulation method is theoretically and experimentally studied for quaternary DPSK. Experimental results agree with the theory, which indicates that performance is superior to conventional DPSK by 1.2 dB, but poorer than coherent detection by 1.3 dB. This method can be applied effectively to TDMA communications and to on-board regenerative repeaters.

Circuit techniques for a VLSI memory

Abstract: This paper describes circuit techniques necessary for dynamic RAMs with high-packing density to implement submicron device technology. An on-chip error checking and correcting technique using bidirectional parity checking is proposed to reduce the soft error rate. In a sense-refresh amplifier, capacitor-coupled presenting is introduced to compensate for threshold imbalance. An on-chip supply voltage conversion is described as a solution for a hot carrier-injection problem. A 256K CMOS dynamic RAM has been designed and fabricated as a test vehicle for these techniques.

Coded data on a record carrier and method for encoding same

Abstract: The coded data (12) on the record carrier (10) and the method for encoding such data (12) in tracks (14) provide a relatively simple and yet very effective means for making the data record carrier (10), and particularly the data (12) recorded thereon, highly tolerant of errors such as "burst errors" where one or more spots of data on the data record carrier (10) are obliterated. The data (12) are recorded on the data record carrier (10) in arcuate nested tracks (14), each track (14) comprising a stream of data bits. The stream of data bits includes an encoded front track address (32) and encoded back track address (44) with coded groups or so-called Hamming type coded groups (52) of data bits therebetween each of which can comprise 96 or 105 data bits. Error correction is provided by including in the coded groups data words which include a data byte and a field of parity bits, typically an eight bit data byte followed by a four bit parity field. Also a cyclic redundancy checksum byte is provided in the group as a further check of the data therein. Further, this data is multiplexed. Additionally, one or two redundant groups are provided in each track (14) for recreating missing groups and a cyclic redundancy checksum field is provided for error detection in each track (14).

System for identifying defective media in magnetic tape storage systems

Abstract: A method and associated system for monitoring errors that occur in magnetic media storage read and write operations, for identifying uncorrectable errors and classifying them. In the system, a counter keeps track of specific locations of data blocks as well as the physical locations of the data recorded upon the media. When an error occurs in read or write operations that cannot be corrected by the error correction circuits, the error location is stored. After an error correction procedure, including usual retry operations, is completed, the count values of the error correction procedures are also stored. Means are provided for comparing the recorded error counts for initial and retry operations. A match of error positions, not correctable through standard error recovery procedures and in the presence of valid recording channel electronics operation, indicates a media defect at the identified location.

Error correction method for the transfer of blocks of data bits, a device for performing such a method, a decoder for use with such a method, and a device comprising such a decoder

Abstract: For an error correction method for the transfer of word-wise arranged data, two word correction codes are successively used, each code acting on a group of words while therebetween an interleaving step is performed. The actual transfer takes place by means of channel words for which purpose there are provided a modulator and a demodulator. Invalid channel words are provided with an invalidity bit in the demodulator. During the (possibly correcting) reproduction of the data words, the invalidity bits can be used in one of the two error corrections in various ways. When too many words of a group of code words are invalid, all words of the relevant group are invalidated. If a word comprising an invalidity bit is not corrected during correction by means of a syndrome variable, all words of the relevant group are invalidated. If the number of invalidity bits lies within given limits, they act as error locators so that the code is capable of correcting a larger number of words.

Decoding of BCH double error correction - triple error detection (DEC-TED) codes

Abstract: Decoding of BCH multiple error correction code codewords with α as a primitive element of the finite field GF (2m) is accomplished by generating syndrome subvectors S1 from all column m-tuple αk positions and syndrome subvectors S2 from all column m-tuple α3K positions, generating a permutation of syndrome subvector S1 for each bit position on the codeword and then selecting those bit positions K where S1 3 +S2 +QK=0 as the bit or bits in error.

Time Diversity with Adaptive Error Detection to Combat Rayleigh Fading in Digital Mobile Radio

Abstract: A new diversity technique is proposed to combat Rayleigh fading in digital mobile radio systems transmitting speech signals. The speech signals are μ-law PCM encoded ( \mu = 255 , 8 kHz sampling, 8 bits/code word, 64 kbit/s data rate), and alternate data words are used to form two streams called "odd" and "even." The even stream is delayed by τ seconds and the streams are interleaved prior to radio transmission using two-level PSK modulation. At the receiver the odd data stream is delayed by τ and interleaved with the even stream. Consequently, if an error burst occurs, the effect of the reshuffling of the data stream is, in general, to place words with bit errors in juxtaposition to those correctly received. After μ-law PCM decoding of the words, a statistical error detection strategy is evoked to identify the erroneous samples. These samples are replaced by adjacent sample interpolation to give the recovered speech sequence. No recourse to channel protection coding is made. In our experiments a Rayleigh fading envelope was generated from a hardware simulator and stored in a computer, along with four sentences of speech. The system was then simulated and the recovered speech perceived. The objective performance measures were segmental SNR for the audio signal, and BER. Different error detection strategies were examined and restrictions on τ investigated. For a mobile speed of 30 mph, SNR values of 32, 21, and 16 dB were obtained for BER values of 0.1, 1, and 2 percent, corresponding to SNR gains over an uncorrected system of 3, 9, and 11 dB, respectively.