Showing papers on "Flip-flop published in 1980"

Phase rotation circuit for an eddy current tester

Abstract: An Eddy Currest Tester for detecting defects in conductive materials employs phase rotation circuitry for eliminating the effects of lift-off signals from the reactive component of the output of an eddy current probe. An operator digitally selects a frequency which is input to the eddy current probe which is adjacent a test material. The signal output from the eddy current probe is amplified and demodulated into reactive and resistive components which are processed by phase rotation circuitry. The phase rotation circuitry is calibrated by applying a lift-off signal thereto while a phase adjust switch is on. When the phase adjust switch is on the reactive signal component is applied to a zero crossing detector which in conjunction with a flip flop controls the counting direction of an counter which addresses a sine-cosine table in a eraseable programable read only memory. The sign-cosine values are strobed into a latch which provides the sine-cosine information to multiplying circuits which multiply the reactive and resistive signal components output of the demodulator by the sine and cosine stored in the latch. The outputs of the multiplying circuit are input to a phase rotator which outputs signals which are rotated in the complex plane by the angle corresponding to the sine and cosine stored in the latch. While the phase adjust switch is on, the reactive component of the output of the phase rotator hunts about zero. When the phase adjust switch is off, the phase rotator rotates the phase of any signal input into the multiplying circuitry by the angle indicated by the last sine and cosine values strobed into the latch.

Prediction of flip-flop behaviour in metastable state

Abstract: Two easy experimental measurements carried out on the fundamental gate of a logic family are presented which allow us to foresee the behaviour of the same technology latch circuit in its metastable state produced by a marginal triggering.

An E-beam fabricated GaAs D-type flip-flop IC

Abstract: A first generation of monolithic digital IC's using normally-on type GaAs MESFET's with 1.2-mu m gate length was initially developed. This technology leads to logic gates with propagation delays in the range 130-170 ps. It was applied to the fabrication of an edge-triggered D-type flip-flop IC whose perfomance is presented: minimum data pulsewidth (350 ps), maximum toggle frequency (up to 1.6 GHz), data input sensitivity. An improved technology intended for higher speeds is now under development. It utilizes direct-writing E-beam lithography to delineate 0.75-mu m gate length devices with extremely high alignment accuracy. This fabrication process leads to 61 ps (4 pJ) or 68 ps (2 pJ) propagation delays measured on a dual-ring oscillator test circuit. Recent advances in N/N/sup -/ epitaxial deposition techniques make these performances very uniform and satisfactorily reproducible. D-type flip-flop IC's have been fabricated with this new technology using a reduced (-1 to -1.5 V) pinchoff voltage value. Stable D-type operation up to 3-GHz clocking frequencies has been experimentally observed with a corresponding speed-power product of 2.6 pJ/gate.

A 3.5 GHz self-aligned single-clocked binary frequency divider on GaAs

Abstract: A fully planar self-aligned technology has been ultilised to fabricate a monolithic single-clocked binary frequency divider consisting of a gated master/slave flip-flop and a complementary clock-pulse generator to drive it. An optimised version of the gated m.s. flip-flop is presented along with the m. e.s.f.e.t.model used for the simulations. Correct counting from d.c. up to 5.5 GHz for the gated m.s. flip-flop and up to 3.5 GHz for the single-clocked divider are reported. The performance and evaluation of the circuits are dealt with in detail.

An E-Beam Fabricated GaAs D-Type Flip-Flop IC

Abstract: A first generation of monolithic digital IC's using normally-on type GaAs MESFET's with 1.2-mu m gate length was initially developed. This technology leads to logic gates with propagation delays in the range 130-170 ps. It was applied to the fabrication of an edge-triggered D-type flip-flop IC whose perfomance is presented: minimum data pulsewidth (350 ps), maximum toggle frequency (up to 1.6 GHz), data input sensitivity. An improved technology intended for higher speeds is now under development. It utilizes direct-writing E-beam lithography to delineate 0.75-mu m gate length devices with extremely high alignment accuracy. This fabrication process leads to 61 ps (4 pJ) or 68 ps (2 pJ) propagation delays measured on a dual-ring oscillator test circuit. Recent advances in N/N/sup -/ epitaxial deposition techniques make these performances very uniform and satisfactorily reproducible. D-type flip-flop IC's have been fabricated with this new technology using a reduced (-1 to -1.5 V) pinchoff voltage value. Stable D-type operation up to 3-GHz clocking frequencies has been experimentally observed with a corresponding speed-power product of 2.6 pJ/gate.

Emitter function logic flip-flop circuit

Abstract: An EFL J-K flip-flop circuit is provided in which feedback of only the true output Q of the slave latch to the input of the master section is required. The circuit in one embodiment includes a slave D-type latch comprising an EFL latch circuit combined with a one level current steering network, a master section comprising an EFL latch circuit combined with a two level current steering network, and an ECL inverter for complementing the K input signal to provide a K signal for the master section. All input combinational logic in the master section, including the complementing of the Q feedback signal, takes place in one emitter coupled transistor pair in the second level of the current steering network and at two input emitters of the master section EFL latch circuit. In an alternative embodiment, the ECL inverter is replaced by a third level current switch in the master section. Additional second level current switches may be added to the master and slave sections to provide the flip-flop circuit with asynchronous set and clear functions.

Data transmission clock pulse recovery appts. - has receive terminal with delayed signal and off=line signal comparison and setting counter giving recovered pulse at output

Abstract: Circuitry is for recovery of clock pulses from an incoming data transmission so that the clock pulses can be used for synchronising a decoder, esp. applicable to Bi-phase coded transmissions. A passive delay line delays the incoming signal whilst a by-pass path directs an undelayed signal directly to the input of an exclusive OR gate, the delayed input is presented to the other gate input. The gate output operates the set input of a counter and the recovered clock pulse is taken from the output. The delay line comprises two NAND gates (1, 4) and RC circuitry (2, 3, 5, 6). The delayed and undelayed signals are input to an Exclusive OR gate (7) with its output fed to a NAND gate (8) with a feedback from the counter (9). The NAND gate (8) output is used to set the counter (9). The D type Flip Flop (12) delays the incoming data (E) so that it is available at the output (A2) with reconstituted clock pulse and in sync with the clock pulse at the other output (A1).

Electronic time casting clock

Abstract: PURPOSE:To offer small sized electronic time casting clock, by giving the function performing time casting and stopping at night with electronic constitution, to the clock. CONSTITUTION:When an output is produced from the detector 1 at a correct time, the flip flop 12 is set, and the control signal 4 of one second period is fed to the count circuit 8 and the signal generation circuit 5 via the gate circuit 16, and the time casting tone 6 is produced until the count content of the counter circuit 7 is in agreement. The flip flop 13 is trigggered with the output of the counter circuit 17 to hold am and pm. When the time comes to be stopped for the time casting, the switch 18 is closed and the content of the counter circuit 7 and the output of the flip flop 13 are stored in the memory circuit 10. Thus, the flip flop 14 is set, the gate circuit 17 is closed and time casting is avoided. In this case, the counter 15 counts time casting stop time and the gate circuit 17 is open after set time.

Control circuit for electrical household appliance - has start and cancel function keys connected to electronic circuit with three flip=flop(s)

Abstract: The control unit is designed for programmable household electric equipment and has a safety feature incorporated to ensure correct re-setting if the keyboard is incorrectly programmed, e.g. by children. There are two input keys, one (1) for a cancel function and another (2) for a start function, each connected through a hysteresis-type Schmitt trigger (3, 4) in parallel with an RC-type timing circuit (5, 6, 7, 8). The start key function key circuit is connected to the R terminals of two D-type flip flops (12, 13). The cancel function key circuit is coupled through a logic element with an AND gate (16) and an OR gate and a monostable flip-flop (15) to the output lead (14) to the programmable electrical unit.

Noise suppression circuit - has triple-input NAND=gate combining input pulses with outputs of bistable flip=flop and delay circuit

Abstract: The noise suppression circuit has the input pulses applied directly to one input of a bistable flip flop and via a delay circuit to the other input of the flip flop. A NAND-gate combines the outputs of the flip flop and the delay circuit with the input pulses in order to produce noise-free output pulses. The flip flop consists of two cross coupled NAND-gates. The delay circuit consists of a NAND-gate with threshold and an RC high pass circuit. A NAND-gate may be connected to the input of the delay circuit to suppress inverted noise pulses in a sequence of inverted signal pulses. The advantage lies in the few components needed. The NAND-gate in the delay circuit may be replaced by a voltage-controlled flip flop.

CMI encoder circuit - has one JK-flip=flop two D-flip=flops four OR=gates and five NOR=gates

Abstract: The CMI-code (coded mark inversion) , which is a two stage NRZ code, is implemented in this encoder circuit. It comes well within permitted tolerances and does not require alignment. This is achieved by employing a combination of JK- and D-type flip- flops, OR-gates and NOR-gates. The output of a JK-flip flop (JK) and a D-flip-flop (D1) are fed to a NOR gate (N1) which in turn feeds a second D- flip-flop (D2) whose output goes, via a second NOR-gate (N2) to an OR-gate (O1) and to the output terminal (A). An additional three OR-gates and three NOR-gates complete the combinational logic.

Phase difference measuring circuit

Abstract: PURPOSE:To make possible discrimination of lag and lead of the phase by making up a simple circuit composed of two pulse conversion circuits and a flip-flop circuit which output peculiar pulses at the rise of one input and at the fall of the other input. CONSTITUTION:Pulse conversion circuits 1, 2 are respectively composed of zero cross comparators 11, 21 and differential circuits 12, 22 and their outputs are connected with the set input S and the reset input R, the differential circuit 12 is output at the rise the input, the differential circuit 22 is output at the fall of the input and a flip-flop 3 is controlled. Thus outputs in parallel to phase difference and discriminated by the lead and lag of the phases are obtained from the output Q of the flip flop 3.

Pulse count circuit

Abstract: PURPOSE:To enable to remarkably reduce the hardware and to decrease the error of count value, by count and process in timesharing manner, through the use of a set of counter memory circuit and comparison circuit for a number of pulse inputs. CONSTITUTION:IC1-IC5 are J-K flip flop circuit, and the output inverted every reception of pulse input to the clock terminal CP of IC1 is fed to IC2. On the other hand, the gate control signal input is fed to the input terminal of IC3 to hold the output of IC2,IC3 by shifting them to IC4,IC5 with hold pulse. The output of IC2 and IC4 and that of IC3 and IC5 are respectively in logical operation with the NOR circuits IC6 and IC7. Further, from this operation, the count of input pulse is made by judging the presence of pulse input, presence of gate control signal, and input state of gate control signal.

Jk flip flop circuit

Abstract: PURPOSE:To realize a high-operation reliability JK flip flop circuit where yield is improved and cost is reduced, by giving a prescribed delay to clocks for data entry. CONSTITUTION:Dummy gate 21 is provided as a means to give a delay to clock input CLKd for data entry. Due to existence of dummy gate 21, the delay dependent upon dummy gate passage is given to the clock system for data entry equivalently to the delay dependent upon gate passage generated inevitably in the clock system for trigger. Dummy gate 21 can be realized if a needless unused gate is used as it is in a LSI. Then, since the passage delay quantity of gate unit is constant approximately in respect to any gate, unstable elements are eliminated.

Asynchronous counter circuit

Abstract: PURPOSE:To avoid malfunction in compensation with hazard or spike phenomenon, by detecting the specific state separate which is transited before the output of flip flop in a plurality of stages of cascade connection reaches specific state. CONSTITUTION:The output DCBA of flip flop 1A-1D is preset to 1001, it is counted down according to the input of the clock CK and when it reaches 0000, the latch circuit 6 is set with the output of the NOR gate 5. When the next clock is given, it is 1111, and the output of the AND gate 2 gives trigger to the monostable multivibrator 3 through the AND gate 7, preset is made again to 1001, and the latch circuit 6 is reset. In this case, in the process of count down, even if 1111 is made at transient state, since no latch circuit 6 is set, the monomultivibrator 3 is not started.

Signal output circuit of ultrasonic pulse switch

Abstract: PURPOSE:To output the relfection signal of ultrasonic wave pulse signal, with the simple circuit constitution such as differentiation circuit, integration circuit, NAND circuit and inverter circuit. CONSTITUTION:The output circuit consists of the differentiation circuit 16a and integration circuit 16b taking the output of the flip flop circuit 12 as input signal, which is set when the reception signal is present within the gate close period and reset at the next reception time, NAND circuit 16C inputted to one input end via the diode D1 for the output of the differentiation circuit 16a and inputted to another input for the output of the integration circuit 16b, inverter circuit 16d to which the output of the NAND circuit 16C is inputted to another input terminal via the diode D2, and parallel circuit consisting of the capacitor C1 and the resistor R1. The inverter circuit 16d outputs the relay drive signal.

Receive circuit for digital time multiplexed exchange - has synchronising word comparator and two bistable flip=flops controlling serial input shift register

Abstract: The receiver circuit includes shift register with the same number of stages as there are bits in a signal block. The register is released to receive bits serially by a bistable flip flop circuit acting as a coincidence circuit. Sync. words in the register are compared with a reference sync. bit pattern. If the two are them same, the comparator resets the first flip flop and sets the second flip flop in the bistable flip flop circuit. The second flip flop is reset at the end of the receive interval.

Crystal oscillation circuit

Abstract: PURPOSE:To enable temperature compensation with a simple member, without using temperature compensation capacitor. CONSTITUTION:The signal from the watch circuit 50 outputs intermittent signal phi1 to the AND gate 83 via the differentiation circuit. The switch 91 of the temperature sensor circuit 90 is operated with phi1, and the voltage VM varied with the temperature is outputted on the line 94 while phi1 in H level. In the intermittent control circuit 80, the signal phi2 is outputted to the line 88 and the signal phi3 to the line 95, and the signals control the AND gates 103, 104, 105, 106 of the control circuit 100. The thresholds VTH1, VTH2 of the inverters 101 and 102 are set to different value. Further, the flip flop's 109, 110 are operated with the output of the AND gates 103-106 to drive the AND gates 113, 114, 115 and to control the temperature compensation signal forming circuit 30.

Pulse converter for supplying clock to digital semiconductor circuit

Abstract: A device for producing two clock pulse trains from a periodic signal comprised of waveforms of any shape produces digital pulses having the same period and further having respective duty cycles which are separated by pauses when the pulse series are aligned. The device consists two flip flop cells and two push-pull transistor outputs respectively connected thereto, each push-pull output having an output tap between the transistors. One flip flop cell is connected directly to a waveform source, and the other flip flop cell is connected to the waveform source via a transistor follower circuit.

A five-inputs flip-flop

Abstract: A study is presented about a family of bistables whose first elements are the D and JK flip-flops, and whose main property is the fact that we are able to synthesise any autonomous sequential machine having up to 2i internal states (?i ? i) with just i flip-flops of the type defined by the ith element of the family, and without combinational gates.

Phase delay or advance detection unit

Abstract: PURPOSE:To measure phase delay or advance between a measured n-degree higher harmonic and a reference n-degree higher harmonic by taking out the fundamental wave as well as the n-degree higher harmonic out of a distorted wave and subjecting them to logical operation. CONSTITUTION:The fundamental wave flowing on transmission lines is given to PLL circuit 4 through band-pass filter 2, and a higher harmonic which agrees with the phase of the fundamental wave is applied to waveform shaping circuit 6. The n-degree higher harminic flowing on transmission lines is given to waveform shaping circuit 7 through band-pass filter 3. AND circuits 8 and 9 give AND between outputs of waveform shaping circuits 6 and 7 or their inversional signals. RS flip flop 12 is set or reset according to positive or negative phase difference between the reference n-degree higher harmonic and the measured n-degree higher harmonic, and this data is stored in latch 13 and is displayed on display equipment 14.

Locally or remotely operable electronic lock - has keyboard for entered code and flip=flop and counter controlling opening decision

Abstract: The electronic lock can be operated locally or remotely and has an input keyboard acting as a key into which given codes are entered. The keyboard unit's output is connected via code switches to logic. The outputs of the logic are connected to a flip-flop and only set the flip-flop when the data entered is incorrect. If the entered data is correct the logic moves a counter on. The counter determines the correctness of the sequence and is reset after receiving the last pulse from the logic. For the lock to open, two conditions must be met. First, the counter must have been reset, e.g. to zero. Secondly the flip-flop must not have been set. The lock is simple, cheap and effective.

Tttype flip flop

Abstract: PURPOSE:To prevent malfunctions caused by differential pulsatile noise and so on included in the trigger pulse signal, by integrating and inputting trigger pulses. CONSTITUTION:Integration time constant forming resistance R1 and the cathode of input trigger pulse stopping diode D1 are connected to one input of NAND gate N1, and output logic holding resistance R4 connected in parallel to the anode of diode D1 and one end of integration time constant forming capacitor C2 are connected to the other input, and the other end of C2 is connected to output Q' of NAND gate N2. Symmetrically to these connections, resistance R2 and the cathode of diode D2 are connected to one input of gate N2, and resistance R4 connected in parallel to the anode of diode D2 and one end of capacitor C2 are connected to the other input, and the other end of C2 is connected to output Q of gate N1. Then, the input logical value of trigger pulses is integrated; and when this value exceeds the threshold voltage, this circuit is operated. Since this circuit is not operated by a pulse shorter than time constant R1C2 or R2C2, the FF can be prevented from malfunctions even if differential noise is included in input pulses.

Clock generator for data processor - has switchable frequency and bistable flip=flops connected to form ring counter

Abstract: The clock generator has an oscillator with a number of outputs corresp. to the number of different clock frequencies. Interconnected bandpass filter oscillators oscillate at different frequencies and have two oscillator stages contg. a digital circuit acting as amplifier and coupled together inductively via a transformer. A changeover network receives signals selecting the clock frequency. Each oscillator has a bistable control flip flop for the operating state connected at its output via coupling dides directly to the feedback path of one of the oscillator stages.

Synchronisation system for binary signal receiver - has bistable flip=flops clocked by received signal and clock generator for producing comparison pulse

Abstract: The system synchronises the reception of binary data using a divider chain driven by two different clock frequencies. A control circuit is synchronised to the clock generator and contains three bistable flipflops and a logic circuit. A comparator contains a first bistable flip flop clocked by the received signals, a second bistable flip flop clocked by the clock generator, and a logic circuit. The control circuit's logic comprises two AND-gates, and OR-gate and one NOR-gate.

Power supply circuit

Abstract: PURPOSE:To enable to perform ON-OFF control for the function of power supply switch with the remote control transmitter, for the power supply circuit having the power supply switch function of electronic unit. CONSTITUTION:When the main power switch 6 is turned on in advance, the voltage E1 rectified and smoothed at the smoothing circuit 7 is fed to the amplifier 2, signal separation circuit 3, wave shape circuit 4, and flip flop 5 to keep them in waiting condition. When the remote control signal from the remote control transmitter is received at the receiver 1, it is amplified at the circuit 2, the power supply ON-OFF signal is separated and shaped into one short signal at the circuit 4, the flip flop 5 is inverted. Thus, the transistor Q4 of the ON-OFF control circuit 9 and diodes D7 and D8 are cut off, the transistors Q1, Q3 of the voltage stabilization circuit 8 are turned on, DC output voltage is led out at the output terminal T1, the power supply is tutned on, and it is turned off when the remote control signal is received further.

Unlock signal output circuit of pll circuit

Abstract: PURPOSE:To make it possible to obtain the output of a continuous level as an unlock signal during an unlock period without integrating circuits requiring large- capacity capacitors, etc. CONSTITUTION:Unlock signal of PLL circuit 14 is applied to the set terminal of set/reset flip flop 6. Output Q1 of flip flop 6 is applied to AND circuit 7 together with instruction signal TUL and is applied to the D terminal of latch circuit 8. The output of latch circuit 8 is applied to the D terminal of latch circuit 9, and the output of latch circuit 9 is decided by controller 11; and when the output disapperas in latch circuit 9, output Q2 of output port 12 which has been set to ''1'' is returned to original ''0'' by next instruction signal TUL by controller 11 simultaneously with changing of the oscillation frequency.