Showing papers on "Low-power electronics published in 1996"

Transistor sizing for low power CMOS circuits

Abstract: A direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area. Analytical formulation for the power dissipation of a circuit in terms of the transistor size is derived which includes both the capacitive and the short circuit power dissipation. SPICE circuit simulation results are presented to confirm the correctness of the analytical model. Based on the intuitions drawn from the analytical model, heuristics for initial transistor sizing on critical and noncritical paths for minimum power consumption are developed. Further, fast heuristics to perform transistor sizing in CMOS circuits for minimizing power consumption while meeting the given delay constraints are presented.

Device and Technology Impact on Low Power Electronics

Abstract: In this chapter, we will explore the interplay between device technology and low power electronics. For device designers, this study may contain lessons for how to optimize the technology for low power. For circuit designers, a more accurate understanding of device performance limitations and new possibilities both for the present and the future should emerge from reading this chapter.

Inaccuracies in power estimation during logic synthesis

Abstract: This paper studies the confidence with which power can be estimated at various levels of design abstraction. We report the results of experiments designed to identify and evaluate the sources of inaccuracies in gate-level power estimation. In particular, we are interested in power estimation during logic synthesis. Factors that may invalidate or diminish the accuracy of power estimates include optimization, technology mapping, transistor sizing, placement and wiring, and choice of input stimuli.

Effects of correlations on accuracy of power analysis—an experimental study

Abstract: In this paper, we describe the correlation assumptions made by different power analysis methods and evaluate the impact on the accuracy of total power dissipation calculation as well as of the power dissipated by individual signals. Industrial circuits and applications are used. The results show that some assumptions cause inaccuracies of more than 100% for certain circuit types.

Sampled-data modelling and simulation of cyclically switched converters

Abstract: A procedure for the description of power electronics circuit dynamics is proposed with the intention of control system design and discrete-time system simulation. The a,pproach is specially suited to be used along with computer-aided analysis and synthesis software packages such as MATLAB. The various modelling steps are illustrated by an application to a dcldc converter under different control strategies.

Advanced materials for low power electronics

Abstract: This paper will review recent advances in the development of key material structures essential for the cost effective manufacture of promising low power technology candidates such as scaled CMOS [bulk/silicon-on-insulator (SOI)], BiCMOS and HBTs. The introduction of a new breed of 200/300 mm substrates, such as ultra-thin SOI and low cost intrinsically gettered bulk Si (e.g., hydrogen annealed, buried layers) for the front-end process and low K dielectric materials (polymers, aerogels, etc.) and Cu metallization for the interconnects, will play major roles in meeting the performance (maximum speed at minimum power at Vdd = 1 V), manufacturability and cost requirements driving the low power paradigm. The material requirements and timing for their introduction into manufacturing need to be in concert with their anticipated insertion into the 0.25 0.18 μ m technology nodes for both memory and logic (μP) applications. A critical review of the major manufacturing challenges facing these material systems will be discussed.

Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models

Abstract: Accurate MOSFET I/sub dsat/ model including LDD parasitic resistance and channel subthreshold leakage models current MOSFET operation regions, particularly moderate inversion and subthreshold regions that are important for low power electronics, have been presented with measurement data. Based on these accurate models, CMOS gate performance and power consumption optimization guidelines have been discussed in terms of device T/sub ox/, V/sub dd/ and V/sub t/. It predicts that there exists certain T/sub ox/ value that can minimize the gate delay. Device designs for low power electronics considering trade-offs by varying V/sub dd/, T/sub ox/ and V/sub t/ are highlighted.