Showing papers on "Memory refresh published in 1994"

Room-temperature single-electron memory

Abstract: This paper presents room-temperature operation, for the first time, of single-electron memory, in which one electron represents one bit of information. This is made possible by our new one-transistor memory configuration which has a very high charge sensitivity (conventionally, three circuit elements are needed). Another new technique, which facilitates single-electron memory, is the ultra-thin (3.4 nm) poly-Si film used for the active region, in which sub-10-nm-width current channels and storage dots are naturally formed. In the fabricated poly-Si TFT's a single electron is stored (or "written") on a low-energy silicon island, and the number of stored electrons is counted (or "read") by the quantized threshold-voltage shift. Single-electron memory provides the potential for new nonvolatile RAM's, suitable for mobile computers/communicators. >

Disk controller with volatile and non-volatile cache memories

Abstract: A disk storage subsystem includes both volatile and non-volatile portions of memory. In response to a write command from a host computer, the controller allocates a predetermined number of memory blocks in the non-volatile cache memory and allocates a corresponding number of blocks in the volatile memory. Host supplied write data is then stored in the allocated non-volatile memory blocks. The data may also be mirrored in additional non-volatile memory. Immediately thereafter the subsystem sends an acknowledge signal to the host. The subsystem then performs a DMA operation to copy the write-data from the non-volatile memory blocks to the volatile memory blocks. The write-data is then stored on a disk drive at which point the non-volatile memory may be de-allocated. Subsequent reads of the given data may be read from the volatile memory, reducing disk access time. In the event of a power failure, data stored in the non-volatile memory but not yet written to disk is preserved. In the event of a disk controller failure, the non-volatile memory modules may be transferred to a functioning disk controller for recovery.

Multiplexed memory timing with block reset and secondary memory

Abstract: A spatial light modulator array with adaptable multiplexed memory architecture. The modulator has an array of individually controllable pixels, where a predetermined number of pixels are assigned to a memory cell (16). The memory cell receives data from an input bus (14). On a signal (22), the memory cell transfers its data to a secondary memory (18), and to the activation circuitry (20) of one of its assigned pixels. On a second signal, the pixel responds to the data on the activation circuitry. When the display time of the data is less than the load time for the memory cell, the secondary memory is set with a second signal (24) so as to make the pixel dark and another control signal makes the pixels respond to the memory. In this way, the load time is lengthened and the data rate remains relatively low, even though the number of bits of intensity may not be the same as the number of bits of intensity used to determine the number of pixels assigned to each memory cell.

Flash memory control method and information processing system therewith

Abstract: A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

Preservation of a computer system processing state in a mass storage device

Abstract: A computer system wherein the processing state of the system may be saved and restored on a mass storage device upon the occurrence of a triggering event. The computer system of the present invention comprises a processor and various memory areas and system resources. Main memory includes several areas including a system management area comprising a segment of isolated random access memory within main memory. The system management area may only be accessed while the processor is in a system management interrupt state. The remaining portions of main memory are freely accessible (i.e. non-isolated) by any interrupt or noninterrupt processing logic. The basic approach of the present invention for saving the processing state of a computer system in nonvolatile storage is to: (1) sense a save system state triggering event; (2) write the contents of system registers and memory to a nonvolatile mass storage device; and (3) enter a suspend state and wait for a resume triggering event or power off the computer system completely. The basic approach of the present invention for restoring the processing state of the computer system from nonvolatile memory is to: (1) sense the resumption of processing of the application of power to the computer system; (2) read the contents of a previously save processing state from a nonvolatile mass storage device and restore the contents of memory and computer system registers; and (3) return control to the previously running application program.

Non-volatile memory module

Abstract: Certain embodiments described herein include a memory system which can communicate with a host system such as a disk controller of a computer system. The memory system can include volatile and non-volatile memory and a controller which are configured such that the controller backs up the volatile memory using the non-volatile memory in the event of a trigger condition. In order to power the system in the event of a power failure or reduction, the memory system can include a secondary power source which is not a battery and may include, for example, a capacitor or capacitor array. The memory system can be configured such that the operation of the volatile memory is not adversely affected by the non-volatile memory or the controller when the volatile memory is interacting with the host system.

Electronic processor for pulse oximeters

Abstract: An apparatus for measuring the concentration of blood constituents in which the architecture of the electronic processor reduces the amount of controller processing time required for tasks such as data acquisition and generation of system control signals. A demodulator is coupled to a probe for converting a first electrical signal to digital data. An interface is coupled to the demodulator for receiving the digital data and generating interrupts when a first amount of the digital data has been received. A buffer memory is coupled to the interface for storing the digital data. A controller having a controller memory (in specific embodiments, a CPU having a CPU memory) is also coupled to the buffer memory. The controller transfers the digital data from the buffer memory to the controller memory in response to the interrupts. The controller then processes the digital data to calculate the arterial oxygen concentration.

Clock management for power reduction in a video display sub-system

Abstract: A video sub-system features reduced power consumption by periodically disabling the video controller clocks used for transferring pixel data to a screen. The video clocks are pulsed only when pixel data is being transferred to the screen, during the time that a horizontal line of pixels is being scanned on the screen. The video clocks are not pulsed during the horizontal and vertical blanking periods, when the electron beam in a cathode-ray-tube is being re-traced. The video clocks are also not pulsed during a recovery period for a flat-panel screen. A video memory contains pixel information for the entire screen and is controlled by a memory controller. The memory controller uses a memory clock to transfer all or part of a horizontal line of pixels to a video buffer. The pixel data is then read out of the video buffer to the screen in a serial fashion, synchronized to the video clock. Host data may be written to a host buffer using a bus clock from the host, and then written to the video memory using the memory clock. The memory clock is only pulsed when data is transferred to or from the video memory, or during memory refresh. The memory clock is not pulsed when the video memory is idle. Power consumption is reduced by enabling or pulsing the memory clock and the internal bus clock only when a transfer request is received, pending, or in progress.

Dynamic memory disambiguation using the memory conflict buffer

Abstract: To exploit instruction level parallelism, compilers for VLIW and superscalar processors often employ static code scheduling. However, the available code reordering may be severely restricted due to ambiguous dependences between memory instructions. This paper introduces a simple hardware mechanism, referred to as the memory conflict buffer, which facilitates static code scheduling in the presence of memory store/load dependences. Correct program execution is ensured by the memory conflict buffer and repair code provided by the compiler. With this addition, significant speedup over an aggressive code scheduling model can be achieved for both non-numerical and numerical programs.

Resynchronization circuit for a memory system and method of operating same

Abstract: A resynchronization circuit for processing a stream of data values read from a memory system, and a method of operating the same. The resynchronization circuit includes a first in, first out (FIFO) memory device, a phase locked loop circuit and a latency control circuit. The FIFO memory device receives a stream of data values and a first clock signal from the memory system. The data values are sequentially read into the FIFO memory device in response to the first clock signal. The phase locked loop circuit receives a second clock signal, and in response generates an output clock signal which leads in phase the second clock signal. The output clock signal is provided to the FIFO memory device to cause the data values to be sequentially read from the FIFO memory device. As a result, a stream of data values is generated which is synchronized with the second clock signal. The latency control circuit, which is coupled to the FIFO memory device, enables the data values to be read from the FIFO memory device after a selectable delay period which follows the initiation of the read operation from the memory system.

Memory access control method and system for realizing the same

Abstract: Comparators are provided for monitoring a data write request output from CPU to a keyboard controller 113, and a request for inhibiting a memory access of 1 MB or more. Circuits are provided for generating a memory access disabling signal for disabling a memory access of 1 MB or more in response to the detection of the requests by the comparators. The memory access disabling signal is transmitted to the memory and KBC 113.

Highly compact memory device with nonvolatile vertical transistor memory cell

Abstract: A highly compact nonvolatile solid state memory core is provided that stores and reproduces both digital and analog signals for multimedia applications. The memory core includes vertical electrically erasable and programmable read only memories (EEPROM) cells having, for example, a stacked gate or a split channel configuration. An array of EEPROM cells on the same chip is prewritten and is used as a reference for digital-analog conversions and for memory cell programming. An intelligent write method allows each memory cell to either store an analog signal or multiple digital signals. Based on the previously stored signal, the intelligent write method determines whether to charge or to discharge the floating gate associated with the selected memory cell. Thus, full erasure is not required prior to programming each memory cell. The present invention significantly increases the density of memory cell arrays while prolonging the useful life of the array.

Memory controller for reading data from synchronous RAM

Abstract: A memory controller reads data from a memory bank of synchronous RAM during a small and variable data valid window, by compensating for delays in receiving the data caused by memory loading, chip and card manufacturing process variations, and the like. The memory controller includes a system clock driver to supply the memory bank with a clock reference signal. A sampling clock provides an assortment of sampling clock signals duplicative of the system clock signal, with various delays. A command driver initiates Read operations in the memory bank by relaying Read command signals to the memory bank. In response to the level of memory loading, such as the number of memory modules present in the memory bank, a clock selector directs a selected one of the sampling clock signals to a delay module, which replicates any delay the system clock driver may have. If desired, an additional, user-selectable supplementary delay unit may be used to increase the delay provided by the delay module, thereby increasing or offsetting the delay of the selected sampling clock signal. The delay module provides a delayed clock signal to synchronize receipt of Read data signals from the memory bank at a clocked latch, enabling the latch to receive the Read data signals during the appropriate data valid window. Specifically, the latch is activated by receipt of Read command signals, which may be coordinated, for example, with the rising edge of the delayed clock signal. The latched Read data signals are then available for use by other logic circuitry.

Apparatus and method for integrating texture memory and interpolation logic in a computer system

Abstract: In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.

Fully pipelined and highly concurrent memory controller

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

Memory access coalescing: a technique for eliminating redundant memory accesses

Abstract: As microprocessor speeds increase, memory bandwidth is increasingly the performance bottleneck for microprocessors. This has occurred because innovation and technological improvements in processor design have outpaced advances in memory design. Most attempts at addressing this problem have involved hardware solutions. Unfortunately, these solutions do little to help the situation with respect to current microprocessors. In previous work, we developed, implemented, and evaluated an algorithm that exploited the ability of newer machines with wide-buses to load/store multiple floating-point operands in a single memory reference. This paper describes a general code improvement algorithm that transforms code to better exploit the available memory bandwidth on existing microprocessors as well as wide-bus machines. Where possible and advantageous, the algorithm coalesces narrow memory references into wide ones. An interesting characteristic of the algorithm is that some decisions about the applicability of the transformation are made at run time. This dynamic analysis significantly increases the probability of the transformation being applied. The code improvement transformation was implemented and added to the repertoire of code improvements of an existing retargetable optimizing back end. Using three current architectures as evaluation platforms, the effectiveness of the transformation was measured on a set of compute- and memory-intensive programs. Interestingly, the effectiveness of the transformation varied significantly with respect to the instruction-set architecture of the tested platform. For one of the tested architectures, improvements in execution speed ranging from 5 to 40 percent were observed. For another, the improvements in execution speed ranged from 5 to 20 percent, while for yet another, the transformation resulted in slower code for all programs.

Power efficient RAM disk and a method of emulating a rotating memory disk

Abstract: Data is stored in and read from a semiconductor memory system including multiple memory integrated circuits in data units commonly exchanged with a rotating memory device. One or more data units to be stored are clustered with a multiplicity of other data units stored in the semi conductor memory to form a cluster of data units. The cluster of data units is compressed, and the compressed cluster of data units is then error correction coded. The compressed cluster of data units is then stored in the semiconductor memory with a multiplicity of contiguous data bits being stored in a single memory integrated circuit. Data compression reduces the number of memory integrated circuits required, thereby reducing both cost and power consumption. Data is stored in and read out of the memory integrated circuits serially such that only a single memory integrated circuit is active at a time, further reducing power consumption.

Memory Systems 1994

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Random access memory having flash memory

Abstract: A semiconductor nonvolatile memory device including first and second bit lines, a buffer memory connected to the first and second bit lines, an electrically erasable programmable nonvolatile memory connected to the first and second bit lines, a writing latch circuit to which the first and second bit lines are connected in parallel and having a differential sensor type sense amplifier, and a switching circuit for switching the nonvolatile memory and the latch circuit to a nonconnected state at the time of operation of the buffer memory and switching the buffer memory and the latch circuit to a nonconnected state at the time of a writing or erasure operation on the nonvolatile memory.

Content-addressable memory with programmable field masking

Abstract: An apparatus and method for programmable field masking in content-addressable memory (CAM). The present invention provides a CAM with at least one group of memory cells interconnected by a word line and a match line. The group of memory cells includes data memory cells divided into a number of data memory cell fields for storing data bits of a data word. A mask memory cell is provided within the group of memory cells for storing at least one mask bit indicating a status of data stored in at least one of the data memory cell fields. The mask memory cell is operative to interrupt the match line in response to the stored mask bit. A match line detector detects a signal level on the match line to indicate if input data bits supplied on the data memory cell bit lines match data bits stored in at least one of the data fields. The data memory cell fields may be organized into a hierarchy, with mask memory cells connected between the data fields, to provide hierarchical masking. General programmable masking of any data field within the group is provided using multiplexed mask memory cells connected by bypass lines. The multiplexed mask memory cells may store one or more mask bits in order to allow a bypass line to be connected to portions of the match line, thereby masking a given data memory cell field.

Method and apparatus for implementing refresh in a synchronous dram system

Abstract: A synchronous DRAM system with internal refresh is controlled by a refresh signal issued by an oscillator or memory controller coupled to the DRAM. By locating the oscillator on the processor or memory controller better control of the frequency of refresh is achieved, particularly, as the signal can be derived from a crystal which is not sensitive to variations in operating conditions. The oscillator drives a refresh signal on a bus or signal line to the DRAM, such that the refresh address counter is incremented and the row identified by the refresh address counter is refreshed.

System for downloading software

Abstract: An improved system is disclosed for downloading, verifying, and/or testing software from a remote programmer to an Electronic Engine Control ("E.E.C.") unit on a gas turbine engine. The invention includes a remote programmer that communicates with the E.E.C. unit through a serial communications link. The E.E.C. unit receives the communications through a serial memory that transmits them to a shared memory and on through a central processing unit ("C.P.U.") to a program memory. A redundant control circuit is controlled by the remote programmer and directs the E.E.C. unit through three operational modes. In a first, or download/verify, mode of operation, the E.E.C. unit may receive and store a boot program. In a second, or program memory, mode, the C.P.U. executes the boot program to allow the C.P.U. to read from and/or write to the program memory in response to communications from the serial channel. In a third, or normal, mode of operation, the C.P.U. can only read from the program memory and an on-board or host computer may replace the remote programmer, so that the C.P.U. executes software stored in the program memory in response to communications received from the host computer to control multiple actuators on the engines, but the host computer cannot access the E.E.C. unit's program memory.

Bootstrap loading from external memory including disabling a reset from a keyboard controller while an operating system load signal is active

Abstract: A computer system bootstrap loads a processor and associated memory from an external memory device instead of being bootstrap loaded from on-board read only memory. The computer system is comprised of a system bus, a processing component, a first system memory device, a memory card interface controller, and an external memory device connected to the memory card interface controller. The system also includes a second system memory device, a keyboard memory device, a keyboard controller and a reset switch for causing a reset and initialization of the processing component. Upon reset, the logic in the memory card interface controller remaps the address space associated with the first system memory device to the external memory device and remaps the address space associated with the second system memory device to the keyboard memory device. This remapping redirects execution control of the processing component to the external memory device and allows the keyboard memory device to be loaded and verified by the processing component. The keyboard controller is held in a reset state. Once the keyboard memory device and local random access memory has been loaded from the external memory device, the address space remapping of the first and second memory devices is restored to a normal configuration. The contents of the first and second memory devices can then be loaded and verified. The reset condition is then removed from the keyboard controller and normal operation of the computer system is restored.

Non-volatile semiconductor memory device having memory cells, each for at least three different data writable thereinto selectively and a method of using the same

Abstract: A method of writing or reading at least three different data in each memory cell, in a non-volatile semiconductor memory device having a plurality of memory cells, each memory cell having floating gate for setting a given threshold voltage in the memory cell. In addition, a non-volatile semiconductor memory device capable of checking if the data stored in the selected memory cell is correct by using one of at least two binary bits of the data as a parity bit, and a method of writing or reading data in or from that memory device.

Evaluating the memory overhead required for COMA architectures

Abstract: Cache only memory architectures (COMA) have an inherent memory overhead due to the organization of main memory as a large cache called an attraction memory. This overhead consists of memory left unallocated for performance reasons as well as additional physical memory required due to the cache organization of memory. In this work, we examine the effect of data reshuffling and data replication on the memory overhead. Data reshuffling occurs when space needs to be allocated to store a remote memory line in the local memory. Data that is reshuffled is sent between memories via replacement messages. A simple mathematical model predicts the frequency of data reshuffling as a function of the attraction memory parameters. Simulation data shows that the frequency of data reshuffling is sensitive to the allocation policy and associativity of the memory but is relatively unaffected by the block size chosen. The simulation data also shows that data replication in the attraction memory is important for good performance, but most gains can be achieved through replication in the processor caches.

Nonvolatile memory with volatile memory buffer and a backup power supply system

Abstract: A memory device that resides on a single substrate includes a nonvolatile memory array Control circuitry is coupled to the memory array for controlling memory operations with respect to the memory array A volatile memory buffer is coupled to the control circuitry for buffering data that is to be written into the memory array The control circuitry fetches the data from the memory buffer to store in the memory array A power supply control circuit is provided for detecting loss of a power supply applied to the memory buffer and for coupling a backup power supply to the memory buffer when the power supply is disconnected from the memory buffer such that data integrity of the memory device is maintained

CPU-controlled garbage-collecting memory module

Abstract: The CPU-controlled garbage-collecting memory module (CPU-C GCMM) is essentially an intelligent memory that connects to a central processing unit (CPU) and performs the routine and repetitive tasks associated with a spectrum of garbage-collecting techniques under the direction and control of the CPU. The CPU-C GCMM performs its garbage-collecting tasks as background tasks to be performed when the CPU-C GCMM is not burdened with the ordinary fetch and store operations necessitated by the application programs being run on the CPU. The CPU-C GCMM can be structured in a variety of ways. One species which embodies the essence of the invention includes a memory and a memory controller which provides the means for reading data from and writing data to the memory. The memory controller receives fetch requests directly from the CPU and returns the requested data immediately even though the data may be incorrect in certain instances. A microcontroller which exercises overall control over the component parts of the CPU-C GCMM together with a fetch monitor work together to repair any incorrect data deliveries to the CPU by the memory controller. A communication-channels unit provides the means of communication between the CPU and the microcontroller for handling all interactions between the CPU and the CPU-C GCMM except fetch requests. An object space manager unit provides a means for rapidly identifying the header of an object given a pointer to the interior of an object.

Fault tolerant memory system which utilizes data from a shadow memory device upon the detection of erroneous data in a main memory device

Abstract: A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device to the output terminal.

Semiconductor memory system with the function of the replacement to the other chips

Abstract: In a semiconductor memory system including a plurality of memory chips, a spare memory is shared among the memory chips. For such a purpose, a common redundant circuit and an external terminal capable of accessing to a spare memory are added to a semiconductor memory system, and a first region for storing a defect address in each memory of the semiconductor memory system and a second region for storing a defect address of the system of the object having the same structure as the first region are provided in the redundant circuit. With this, even when the defect of a normal memory of the semiconductor memory system can not be replaced with the spare memory of the system itself, replacement is made possible with other system having the same structure. Accordingly, the yield of the semiconductor memory system can be increased, and the reliability is also increased.