Showing papers on "Memory refresh published in 1998"

Active pages: a computation model for intelligent memory

Abstract: Microprocessors and memory systems suffer from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive computations to the memory system. An Active Page consists of a page of data and a set of associated functions which can operate upon that data. We describe an implementation of Active Pages on RADram (Reconfigurable Architecture DRAM), a memory system based upon the integration of DRAM and reconfigurable logic. Results from the SimpleScalar simulator [BA97] demonstrate up to 1000X speedups on several applications using the RADram system versus conventional memory systems. We also explore the sensitivity of our results to implementations in other memory technologies.

Power control system for synchronous memory device

Abstract: A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.

Low latency shared memory switch architecture

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Memory interface controller

Abstract: The present invention relates to a memory interface controller for a data transmission system. A memory interface controller is capable of randomly accessing a memory using an associative memory and variably processing data using an extended memory. There is provided a memory interface controller which includes a control logic unit for selectively outputting signals; a comparand register for storing a sequence number; an associative memory for outputting a match address; a priority address encoder for outputting a priority match address; an external memory controller for outputting an empty address of the associative memory; an external tended memory controller for outputting a priority empty address; and an extended memory address and control signal generator for generating an address and a control signal (enable/read/write).

Memory system including a memory module having a memory module controller

Abstract: A system (300) that has a system memory controller (304) and memory module (306, 308). The memory modules (306, 308) include memory module controller (310, 316) coupled to the system memory controller (304) and a plurality of memory devices (312-315, 317-320) coupled to the memory module controllers (310, 316).

Nonvolatile semiconductor memory device with soft-programming to adjust erased state of memory cells

Abstract: A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data "0" can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

Memory module system having multiple memory modules

Abstract: There are provided a memory controller, a plurality of memory modules, and an external data bus common to the plurality of memory modules. The plurality of memory modules each include a plurality of memory chips, a plurality of internal data buses connected between a corresponding memory chip and an input/output terminal, a logic chip, and a plurality of switch transistors each connected between a corresponding internal data bus and a corresponding input/output terminal to turn on/off in response to a control signal from the logic chip. The plurality of switch transistors in a memory module selected by the memory controller are turned on, and the plurality of switch transistors in the memory modules other than the selected memory module are turned off. Thus, the capacity of the memory modules may be increased while maintaining high-speed data transfer.

Semiconductor storage device and method of controlling it

Abstract: The aim is to improve reliability and life of a semiconductor storage device using memory elements for which deterioration is a problem. In a semiconductor disk device equipped with a flash memory section 110 having memory elements M(0)˜M(9) having a plurality of sectors used as ordinary sectors or spare sectors, and a disk controller section 120 that performs data writing/reading in respect of memory elements M(0)˜M(9) in accordance with address information input from outside, there are provided a data error information management table 127 that stores for each memory element the situation regarding occurrence of write/read error of memory elements M(0)˜M(9), a micro CPU 131 that detects deterioration of memory elements in accordance with the situation regarding occurrence of write/read error stored in data error information management table 127, and an address conversion table 128 that effects conversion of address information such that memory elements M(0)˜M(9) for which deterioration has been detected by micro CPU 131 are not used.

Methods and apparatus for dual-boot memory selection, update, and recovery in a programmable device

Abstract: Methods and associated apparatus for using a dual-boot capable programmable device and for updating programmed information in such a dual-boot capable programmable device. The apparatus of the present invention includes a primary boot memory device (108), a secondary boot memory device (110), and means for selecting between the two memory devices for purposes of "booting" the dual-boot mode device (100, 114..122). In particular, a reset switch (122) of the apparatus of the present invention resets devices in the dual-boot capable programmable device and is coupled to a selection device (114..120). The selection device (114..120) multiplexes signals from the two boot memory devices onto the corresponding bus signals of the dual-boot capable programmable device. When a "long" reset switch activation is sensed (118), the selection device selects a first of the two boot memory devices for coupling to the programmable device. A "short" activation (120) of the reset switch selects the other boot memory device. The present invention also includes methods (200..214, 400..410) for updating the contents of the two boot memory devices so as to avoid an inoperable state encountered due to failure of the update process in a single boot memory device. In particular, both boot memory devices are updated in sequence. The second memory update (206..214) is prevented if the first memory update (200..202) is determined to have failed (204).

Method and apparatus for implementing multiple memory buses on a memory module

Abstract: A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.

Using FET switches for large memory arrays

Abstract: The present invention discloses a method and apparatus for interfacing a memory array to a memory controller using a field-effect transistor (FET) switch. The memory controller has a bus which comprises a plurality of signal lines. The memory array is coupled to the memory controller. The memory array is divided into N groups of memory devices; each group has K memory devices. K memory devices in each of the N groups share memory signal lines. The FET switch couples the bus to one of the N groups of the shared memory signal lines at different times in response to a switch control indication.

Ferroelectric memory using ferroelectric reference cells

Abstract: A random access memory circuit is described which uses single ferroelectric memory cells to store data. The ferroelectric memory cells can be selectively read using reference cells to generate a reference voltage which is compared to a voltage representative of data stored on the memory cell using a multiplexed sense amplifier. In using two ferroelectric reference cells in which one contains a logical 0 polarization, and the other contains a logical 1 polarization, a single-ended reference voltage can be generated on a reference bit line. A ferroelectric memory cell can then be read by comparing the voltage on its corresponding bit line to the reference bit line using the sense amplifier. The content of the memory cell being read and the content of the reference cells can be rewritten on the same clock cycles to save on access time.

Method and apparatus for testing an integrated memory device

Abstract: A method of memory array testing that detects defects which are sensitive to environmental conditions. A repair signature is generated reflecting the repair state of the memory. A memory device is rejected if there is a change in the repair signature of the memory array over the operating range of the device. In one embodiment, an integrated circuit includes a memory array, spare memory elements for repairing defective locations of the memory array, a built-in self-test (BIST) circuit for detecting faults in the memory array, a built-in self-repair (BISR) circuit for causing the failed memory location of the memory array to be replaced with a spare memory element, and a signature generator where the signature is based on a compression of addresses corresponding to failed memory locations, wherein the signature is used to determine that a repair result of the memory array is invariant over different environmental conditions.

Memory device and system including a low power interface

Abstract: A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.

Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module

Abstract: A memory module controller for providing interface between a system memory controller and a plurality of memory devices on a memory module. The memory module includes first interface circuitry and control logic. The first interface circuitry is configured to receive from the system memory controller a first memory transaction in a first format. The control logic is coupled to the first interface circuitry and configured to convert the first memory transaction into a second memory transaction in a second format for the plurality of memory devices. The second format of the second memory transaction is different than the first format of the first memory transaction.

Apparatus and method for updating ROM without removing it from circuit board

Abstract: An updater device for flash read-only memory is provided. The updater device may be constructed using a power input interface that transfers battery from either a battery or an electrical adapter to the updater device. The updater device has a body containing circuitry that controls the operations of the device. Located in the body is an input, or first, port and an output, or second, port for engaging flash read-only memories. A source flash read-only memory is inserted into the input port and the updater is then placed over the target flash read-only memory so that the updater device engages the target flash memory. A button that is located on the body activates the updating process. First the microprocessor reads data from the source flash read-only memory via a first read-only memory interface located in the input port. Then the microprocessor uses a second read-only memory interface in the second port to erase the target read-only memory. Next, the microprocessor encodes the data read from the source flash memory onto the target flash memory. Before ending the updating process, the updater device confirms that the data encoded on the target flash read-only memory matches that previously read from the source flash read-only memory. During the updating process, the target flash memory is not removed from the attached printed circuit board. Light emitting diodes are attached to the body of the updater device to indicate the status of the updating process. After the newly encoded data on the target flash memory is confirmed a light emitting diode is activated to inform the user whether the target flash memory was properly encoded.

Method and apparatus for updating flash memory resident firmware through a standard disk drive interface

Abstract: A method for updating the content of EEPROM memory used for controlling processes run on a microprocessor used to control the operations of a long term memory array which includes moving an update process stored in the EEPROM memory to a random access memory associated with the microprocessor; and then using the update process stored in random access memory for erasing the contents of the EEPROM memory, and furnishing data to the microprocessor on a sector by sector basis from a host computer through an interface used by the microprocessor to provide data to the long term memory array. The data furnished by the host is written sector by sector to the EEPROM memory until the EEPROM memory has been updated.

Method of processing memory requests in a pipelined memory controller

Abstract: A method for processing multiple memory requests in a pipeline. Each memory request is processed in part by a plurality of stages. In a first stage, the memory request is decoded. In a second stage, the address information for the memory request is processed. In a third stage, the data for the memory request is transferred. A request buffer is used to hold each of the memory requests during the processing of each of the memory requests.

Reducing power consumption in computer memory

Abstract: A computer system comprising an input/output device, a processor, a memory device, and a bridge logic device for interfacing the memory device to the processor and input/output device incorporates a refresh logic device for generating a memory refresh signal during suspend mode. Because the rate at which memory must be refreshed generally depends on the temperature of the memory device, the refresh logic varies the frequency of the refresh signal according to the temperature of the memory device, resulting in substantial power savings. In a preferred embodiment, the refresh logic uses a normal-rate refresh signal at the beginning of suspend mode and incrementally steps down the refresh rate as the memory temperature decreases. In other embodiments, the refresh logic incorporates a signal generator which produces a refresh signal at a frequency that varies according the output voltage from a temperature sensor or the temperature-sensitive resistance of a thermistor. In yet another embodiment, a variable-rate refresh logic is incorporated into the memory device, resulting in a self-refreshing memory module.

High performance cost optimized memory with delayed memory writes

Abstract: A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.

Programmable logic array device with random access memory configurable as product terms

Abstract: A look-up-table-based programmable logic device is provided with memory circuitry which can be operated either as random access memory ("RAM") or to perform product term ("p-term") logic. Each individual row of the memory is separately addressable for writing data to the memory or, in RAM mode, for reading data from the memory. Alternatively, multiple rows of the memory are addressable in parallel to read p-terms from the memory. The memory circuitry of the invention is particularly useful as an addition to look-up-table-type programmable logic devices because the p-term capability of the memory circuitry provides an efficient way to perform wide fan-in logic functions which would otherwise require trees of multiple look-up tables.

Synchronous memory test system

Abstract: An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware, modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing data in the memory device. The tester is comprised of a 32-bit RISC CPU (80) in electrical communication with address/data/control bus (82) and with processor clock (84) which provides timing for the CPU. ROM (90) provides a non-volatile storage for all memory test system operating software programs, and RAM (93) provides temporary and intermediate storage for software programs.

Non-volatile semiconductor memory allowing user to enter various refresh commands

Abstract: In a non-volatile flash memory having memory cells divided into blocks, a command state machine decodes a refresh command entered, and sends a decoded result to a write state machine. The write state machine performs a refresh operation in accordance with the decoded result. The nonvolatile flash memory allows a user to enter the refresh command. The refresh command includes “SINGLE BLOCK REFRESH”, “FULL CHIP REFRESH”, “REFRESH SUSPEND”, and “REFRESH RESUME”.

Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array having plural electrically erasable memory cells including a gate, a source, a drain, and an electric charge accumulation layer each disposed in a matrix form. A data writing section writes data into memory cells in this memory cell array. A data reading section reads out data in memory cells of the memory cell array. A data erasing section erases data in memory cells of the memory cell array. A control section controls, when applying a first signal to the gate in a specified memory inhibited of writing and applying a second signal to a node capacitively coupled to at least one of source and drain, in writing data into the memory cells, so that the second signal may fall later than the first signal.

Data storage system storing data of varying block size

Abstract: A data system comprising a store ( 10 ), a memory ( 12 ), a user interface ( 32 ) and a memory controller ( 24 ) where the memory is used to buffer all data transferred between the user interface and the store, the system being characterized in that the memory controller copies data directly between the store and the memory, whereas the memory controller re-organizes data when the data is transferred between the memory and the user interface.

Method and apparatus for enhancing the performance of semiconductor memory devices

Abstract: A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.

High performance packaging for microprocessors and DRAM chips which minimizes timing skews

Abstract: A method and apparatus for packaging microprocessors and memory devices on a single silicon substrate is described. Microprocessors and memory devices are placed on both sides of the silicon substrate. Through holes are formed in the substrate to connect the microprocessor and memory devices together. By packaging the microprocessor and memory element this way, the propagation length between the memory and the microprocessors is shortened, and timing skews are minimized, and data transmission speed is increased. In addition, additional active and passive circuits and/or components can also be fabricated in one or both sides of the silicon substrate.

High bandwidth cache system

Abstract: A direct access storage device (DASD) controller system for serves computer elements such as processors and disk arrays through a serial interconnect scheme. The system includes a plurality of adapters belonging to either a first set or a second set. Cache memory is divided into master memory cards and slave memory cards, each slave memory card in communication with a corresponding master memory card. A plurality of bidirectional multichannel serial data links connects one adapter with one memory card such that every adapter in the first set of adapters is connected to every master memory card and such that every adapter in the second set of adapters is connected to every slave memory card.

A method and apparatus for hardware block locking in a nonvolatile memory

Abstract: The memory device (200) includes a nonvolatile memory array (215) including a first block of memory cells (230). The first volatile protection bit coupled to the first block is programmable to prevent a memory access operation directed to the first block from being performed.

Dram core refresh with reduced spike current

Abstract: A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.