Showing papers on "Memory refresh published in 2002"

Dual-port buffer-to-memory interface

Abstract: Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 120:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Non-volatile memory control

Abstract: According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time, wherein the method comprises implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time, the arrangement being such that the controller waits for the at least one of the arrays to complete before initiating the transfer to and from a further array.

Enhanced memory module architecture

Abstract: A memory module architecture that supports Flash and static memory devices in addition to dynamic memory devices. The module architecture of the present invention preferably redefines standard application of chip select signals on existing module architectures to provide requisite signaling to support Flash and static RAM devices. Use of serial presence detect signaling features of standard memory modules is also modified to provide desired identity and parameters of such an enhanced module. A further aspect of the present invention provides for a support structure to immobilize the loose edge of the memory module opposite the electrical edge connector of the module to further enhance the module's resistance to vibration and mechanical shock by immobilizing the module with respect to rotation about the key in the socket connector.

Method of writing data to non-volatile memory

Abstract: According to a first aspect of the invention, there is provided a controller connected to a non-volatile memory and including a volatile memory, wherein the controller maintains lists in volatile memory of blocks in the non-volatile memory allocated for storage of logical sector data and of blocks recently erased in the non-volatile memory.

Fail-over of multiple memory blocks in multiple memory modules in computer system

Abstract: A computer system has a memory controller for controlling accesses to multiple memory modules, each having multiple memory blocks, and a fail-over circuit for failing-over individual memory blocks from multiple memory modules. The digital information stored in an individual memory block that has experienced memory errors in excess of a permissible threshold is copied to an auxiliary memory location. The memory accesses directed to the failed-over memory block are intercepted and redirected to the auxiliary memory location. Tags are stored to identify failed-over memory modules and corresponding auxiliary memory modules, so a tag look-up for an accessed memory address can generate a hit signal when the memory access is to a failed-over memory module and cause the auxiliary memory module to respond to the memory access.

Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

Abstract: In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Memory card and memory controller

Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.

Laser programmable electrically readable phase-change memory method and device

Abstract: Roughly described, a phase-change memory such as a chalcogenide-based memory is programmed optically and read electrically. No complex electrical circuits are required for programming the cells. On the other hand, this memory can be read by electrical circuitry directly. The read out speed is much faster than for optical disks, and integrated circuit chips made this way are more compatible with other electrical circuits than are optical disks. Thus memories according to the invention can have simple, low power-consuming, electrical circuits, and do not require slow and power-hungry disk drives for reading. The invention therefore provides a unique low power, fast read/write memory with simple electrical circuits.

Memory system and memory card

Abstract: A memory system comprises nonvolatile memory chips (CHP1, CHP2) having memory banks (BNK1, BNK2) capable of performing memory operations independently and a memory controller (5) capable of accessing/controlling separately the nonvolatile memory chips. The memory controller can selectively instruct the memory banks of the nonvolatile memory chips to perform a simultaneous or interleave write operation. Therefore, the simultaneous write operations each requiring a write time much longer than the write set-up time can be completely parallel carried out, and the interleave write operations following the write set-up can be carried out parallel and overlapped with a write operation of another memory bank. As a result, the number of nonvolatile memory chips constituting a memory system capable of performing a high-speed write operation can be relatively small.

On a new way to read data from memory

Abstract: This paper explains a new family of techniques to extract data from semiconductor memory, without using the read-out circuitry provided for the purpose. What these techniques have in common is the use of semi-invasive probing methods to induce measurable changes in the analogue characteristics of the memory cells of interest. The basic idea is that when a memory cell, or read-out amplifier, is scanned appropriately with a laser, the resulting increase in leakage current depends on its state; the same happens when we induce an eddy current in a cell. These perturbations can be carried out at a level that does not modify the stored value, but still enables it to be read out. Our techniques build on it number of recent advances in semi-invasive attack techniques, low temperature data remanence, electromagnetic analysis and eddy current induction. They can be used against a wide range of memory structures, from registers through RAM to FLASH. We have demonstrated their practicality by reading out DES keys stored in RAM without using the normal read-out circuits. This suggests that vendors of products such as smartcards and secure microcontrollers should review their memory encryption, access control and other storage security issues with care.

Disk drive employing a non-volatile serial semiconductor memory for storing a control program for a microprocessor

Abstract: A disk drive is disclosed comprising a microprocessor, a non-volatile serial semiconductor memory for storing code segments of a control program, a first semiconductor memory for storing code segments of a loader program, and a second semiconductor memory for receiving the code segments of the control program. When the disk drive is powered on, the microprocessor executes the loader program from the first semiconductor memory to load the control program from the non-volatile serial semiconductor memory into the second semiconductor memory. The microprocessor then executes the control program from the second semiconductor memory.

Method and apparatus for memory access scheduling to reduce memory access latency

Abstract: A device is presented including a memory controller. The memory controller is connected to a read request queue. A command queue is coupled to the memory controller. A memory page table is connected to the memory controller. The memory page table has many page table entries. A memory page history table is connected to the memory controller. The memory history table has many page history table entries. A pre-calculated lookup table is connected to the memory controller. The memory controller includes a memory scheduling process to reduce memory access latency.

Appliance, including a flash memory, that is robust under power failure

Abstract: An appliance that includes a host device and a memory unit with a primary memory, and a method of operating the appliance. According to one aspect of the appliance, the primary memory is nonvolatile and the memory unit also includes a volatile memory a power sensor and a controller. When the power sensor detects interruption of power to the memory unit, the controller copies data selectively from the volatile memory to the primary memory. Power for this copying is provided by a secondary power source such as a battery or a capacitor. According to another aspect of the appliance, the appliance includes primary and secondary power sources, and the memory unit also includes a charge pump whose functions include both boosting power from the primary source for the primary memory and charging the secondary source.

Flash memory with multiple status reading capability

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The memory automatically provides status data when a read command is received for a memory array location that is currently subject to a write operation. The automatic status output allows multiple processors to access the memory device without substantial bus master overhead. The memory can also output status data in response to a status read command.

Method for dynamically adjusting a memory page closing policy

Abstract: A method for dynamically adjusting a memory page-closing policy for computer systems employing various types of DRAM memory partitioned into one or more memory banks, and circuitry for implementing the method. In general, the method comprises monitoring memory accesses to memory banks and dynamically adjusting the memory page closing policy for those memory bank based on locality characteristics of its memory accesses so that memory latencies are reduced. In one embodiment, in response to memory requests from a computer system processor, memory accesses to the DRAM memory are made on a page-wise basis. As each memory page is accessed, a page-miss, page-hit or page-hit state is produced. Depending on the page access states, which generally will reflect the locality characteristics of (an) application(s) accessing the memory, a page-close set point is adjusted. When a timing count corresponding to the page exceeds the page-close set point, the memory page is closed.

Programmable conductor random access memory and a method for writing thereto

Abstract: The present invention provides an improved write circuit and method for writing a programmable conductor random access memory (PCRAM) cell. The method comprises precharging a bit line to a first voltage and applying a second voltage to a first terminal of a chalcogenide memory element. A second terminal of the chalcogenide memory element is selectively coupled to the bit line to produce a voltage across the memory element sufficient to write a predetermined resistance state into the element. The first voltage may take on two different values to program two different resistance states into the memory element.

High density random access memory in an intelligent electric device

Abstract: Methods and devices for monitoring distributed electric power are disclosed, including energy devices with a sensor for monitoring an electric circuit, and a memory to store sensor measurements. Various techniques are disclosed for using polymeric RAM, 1T-DRAM, enhanced SRAM, magnetoresistive RAM, organic RAM, chalcogenide RAM, holographic memory, PLEDM, single-electron RAM, fractal cluster glass memory and other technologies in energy devices with high-endurance, high-density, high-capacity, non-volatile, solid-state, or removable memories.

DRAM power management

Abstract: A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected memory access rate corresponds to a desired average memory power consumption rate. A first time interval is started as a current time interval. A memory system is accessed. If the memory access rate has not been exceeded, then the access is applied to the memory system. Alternatively, if the memory access rate has been exceeded, then the access is delayed until the current time interval has expired and a

Semiconductor memory, memory device, and memory card

Abstract: A memory apparatus packaged in one package is provided which includes first data terminals, first address terminals, a status terminal, and memory chips integrated in one semiconductor substrate, one of the memory chips being a nonvolatile memory. Each of the memory chips includes data terminals and address terminals. The data terminals of each of the memory chips are connected to the first data terminals, and the address terminals of each of the memory chips are connected to the first address terminals. The status terminal is arranged to output a status signal which indicates when the nonvolatile memory is in a ready status or in a busy status.

System and method for multi-modal memory controller system operation

Abstract: A memory controller system for processing memory access requests comprising a first memory controller operable to address a first plurality of memory modules a second memory controller operable to address a second plurality of memory modules, the first and second memory controllers configurable to process a memory transaction in an operational mode of the memory controller system selected from the group consisting of an independent cell mode, a multiplexer-mode (mux-mode), and a lockstep mode, and a bus interface block operable to convey the memory transaction to both of the first and second memory controllers is provided.

Methods and apparatus for backing up a memory device

Abstract: A memory module for a computer-based system. The memory module includes at least one memory device that requires periodic refresh signals to maintain data and is mounted on the memory module, and a circuit mounted on the memory module and configured to retain data stored on the memory device when the computer-based system loses power. In a separate embodiment, a control circuit is configured to logically detach at least one memory device from at least one memory controller when a computer-based system loses power, and retain data stored on the memory device when the computer-based system loses power.

Pulsed write techniques for magneto-resistive memories

Abstract: A magneto-resistive memory that has a shared word line and sense line is disclosed. By providing the shared word line and sense line, the number of relatively large drivers required to drive the word line and sense line currents can be reduced. This reduces the peripheral overhead of the memory, and may increase the overall density and reduce the overall power of the memory.

Semiconductor memory module and register buffer device for use in the same

Abstract: In a semiconductor memory module having a plurality of DRAMs, when an input command is detected as a refresh command according to external control signals externally input for command-execution to a register buffer, internal control signals for a partial number of the DRAMs preliminarily selected among the plurality of DRAMs are delayed. Thus, the refresh command is executed with a time difference, and the semiconductor memory module prevents the plurality of dynamic semiconductor memories from simultaneously entering refresh modes to cause a great peak current to flow, and thereby implementing a stable operation.

Back up power embodied non-volatile memory device

Abstract: A back up power embodied non-volatile memory device comprising a connection port, a power supply unit and a memory system. A host machine provides data and power to the connection port through an external bus. The memory system holds the data received from the connection port temporarily and transfers the data to a non- volatile memory unit inside the memory system. The power supply unit provides necessary power to complete the transfer of temporarily stored data inside the memory system to the non-volatile memory unit to become readable data when host power suddenly fails.

Memory configuration for a wireless communications device

Abstract: The present invention provides a method and system that uses serial, writable, nonvolatile memory (serial memory) in a portable radio telephone. According to an object of the present invention, the serial memory may be integral to a cell phone or attached to a cell phone via an add-on card or the like. According to another object, the serial memory may be embedded in a cell phone accessory or attached to an accessory via an add-on card or the like. In both objects, once the portable radio telephone is powered on, data stored in serial memory is transferred into onboard random access memory (RAM), which in turn is utilized by the CPU and/or other cell phone systems. Serial memory includes, but is not limited to, NAND-type flash memory, as well as, flash and EEPROM memories that utilize the following interface architectures: the mircowire bus, the I 2 C bus, the SPI bus and/or the MPS bus. Among other things, serial memory may store the operating system, applications, and radio calibration parameters.

Automatic data migration for reducing energy consumption in multi-bank memory systems

Abstract: An architectural solution to reducing memory energy consumption is to adopt a multi-bank memory system instead of a monolithic (single-bank) memory system. Some recent multi-bank memory architectures help reduce memory energy by allowing an unused bank to be placed into a low-power operating mode. This paper describes an automatic data migration strategy which dynamically places the arrays with temporal affinity into the same set of banks. This strategy increases the number of banks which can be put into low-power modes and allows the use of more aggressive energy-saving modes. Experiments using several array-dominated applications show the usefulness of data migration and indicate that large energy savings can be achieved with low overhead.

Method of refreshing an electrically erasable and programmable non-volatile memory

Abstract: A method (1110 a ;1110 b) of refreshing an electrically erasable and programmable non-volatile memory (100) having a plurality of memory cells (Mhk) is proposed. The method includes the steps of: verifying (1106-1114; 1152-1162) whether a memory cell has drifted from a correct condition (i.e., a predetermined voltage and/or voltage range), and individually restoring (1116-1130) the correct condition of the memory cell if the result of the verification is positive.

A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs

Abstract: A new compact memory architecture is proposed for embedded dynamic random access memory (eDRAM) cells. By exploiting the floating body effect of partially depleted silicon on insulator (SOI) devices, a one-transistor memory cell can be integrated in a pure logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high performance eDRAM applications while reducing the cell area by a factor of two.

Dynamic random access memory system with bank conflict avoidance feature

Abstract: A memory system having multiple memory banks is configured to prevent bank conflict between access requests. The memory system includes a memory controller and a plurality of memory banks operatively coupled to the memory controller, with each of the memory banks configured for storing a plurality of data items. More particularly, a given data item is stored as multiple copies of the data item with a given one of the multiple copies in each of a designated minimum number of the memory banks. The memory controller is adapted to process requests for access to the data items stored in the memory banks in accordance with a specified bank access sequence. The minimum number of memory banks for storage of the multiple copies of the given data item may be determined as a function of a random cycle time and a random bank access delay of the memory banks, e.g., as an integer greater than or equal to a ratio of the random cycle time to the random bank access delay. The memory system is preferably operable in the above-described bank conflict avoidance mode as well as a standard random access mode. The memory system is particularly well-suited for use in an application involving an unbalanced ratio of read and write accesses, e.g., as an external tree memory for a network processor integrated circuit, but can also be used in numerous other processing device memory applications.