Showing papers on "Metal gate published in 1991"

Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance

Abstract: An insulated-gate vertical FET has a channel region and gate structure that is formed along the sidewall of trench in a P-type semiconductor substrate. The drain and source regions of the FET are formed in the mesa and the base portions of the trench. All contacts to the gate, drain, and source regions can be made from the top surface of the semiconductor substrate. One or more sidewalls of the trench are oxidized with a thin gate oxide dielectric layer followed by a thin polysilicon deposited film to form an insulated gate layer. A reactive ion etch step removes the insulated gate layer from the mesa and the base portion of the trench. An enhanced N-type implant creates the drain and source regions in the mesa and the base portions of the trench. The trench is partially filled with a spacer oxide layer to reduce gate-to-source overlap capacitance. A conformal conductive polysilicon layer is deposited over the insulated gate layer. A portion of the conductive polysilicon layer is extended above the surface of the trench onto the mesa to form a gate contact. A field oxide covers the entire surface of the FET, which is opened in the mesa to form gate and drain contacts, and in the base to form the source contact.

A MOS gate drive with resonant transitions

Abstract: A resonant gate-drive circuit for MOS power transistors is described. The gate drive provides quasi-square-wave gate-to-source voltage with low impedance between gate and source terminals in both on and off states. Input capacitance of the power MOS transistor is charged and discharged in a resonant circuit so that switching losses in the gate drive are eliminated. This is particularly important in high-frequency and low-power applications. A detailed loss analysis yields closed-form solutions for gate-drive and total switch losses. These results are used to select the MOS power transistor with minimum losses, and to compare the gate drive with resonant transitions against the conventional gate drive. >

Self-aligning contact and interconnect structure

Abstract: An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

An intelligent MOS transistor featuring gate-level weighted sum and threshold operations

Abstract: A novel functional MOS transistor which behaves much more intelligently than a mere switching device has been developed The device has a floating gate whose potential is controlled by a plural number of input gates via capacitive coupling The transistor is called a 'neuron MOSFET' due to its similarity to biological neurons in that the transistor turns on when the weighted sum of all input signals exceeds a certain threshold value Test devices were fabricated using a double-polysilicon NMOS process The analysis of the basic device operation and its experimental verification are presented A number of interesting applications of the neuron MOSFET are described which include a variable threshold transistor, a neuron circuit, a single-gate D/A (digital-to-analog) converter, and a soft hardware logic circuit >

MOS-type semiconductor integrated circuit device

Abstract: A MOS-type semiconductor integrated circuit device is provided in which MOS transistors are formed in a vertical configuration. The MOS transistors are constituted by pillar layers formed on the substrate. The outer circumferential surfaces of the pillar layers are utilized to form the gates of the MOS transistors. Thus, large gate widths thereof can be obtained within a small area. As a result, the total chip area of the MOS transistors can be significantly reduced while maintaining a prescribed current-carrying capacity.

Adaptable MOS current mirror

Abstract: An adaptable current mirror includes first and second MOS transistors. The first MOS transistor has its gate connected to its drain. A MOS capacitor structure is connected in series between the gate of the first MOS transistor and the gate of the second MOS transistor. Electrons may be placed onto and removed in an analog manner from a floating node associated with the second MOS transistor, usually the gate of the transistor, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. A plurality of adaptable current mirrors communicating with a plurality of current-carrying lines may be employed for indicating the output of the one of the plurality of current-carrying lines through which the most current is flowing.

A method for the fabrication of low leakage polysilicon thin film transistors

Abstract: A method of manufacturing a thin film transistor having a low leakage current including depositing a layer of silicon oxide on a semiconductor substrate or on a layer of silicon nitrate deposited on a glass substrate, depositing a polysilicon layer, at a temperature of 520°-570° C., on the silicon oxide layer, annealing this polysilicon layer in a nitrogen atmosphere at a temperature of less than 650° C., forming islands in this polysilicon layer, forming a gate oxide layer on one of the islands by oxidizing the island under high pressure at a temperature below 650° C., forming a gate from a heavily doped polysilicon layer deposited on the gate oxide layer, forming lightly doped source and drain areas laterally adjacent to the gate, providing a thin layer of silicon oxide on the gate and the source and drain access, heavily doping areas of the first silicon layer adjacent to the source and drain areas, annealing the source and drain areas at a temperature below 650° C. and hydrogenating the resistive transistor with a hydrogen plasma.

Gate oxide damage from polysilicon etching

Abstract: Damage to thin gate oxides from etching of polysilicon gates was studied using gate oxide breakdown histograms and time‐dependent dielectric breakdown measurements. The effect of various polysilicon etch parameters was investigated in a radio frequency (rf) triode etcher. Increasing rf power caused a substantial increase in damage. Reducing bias at constant power also resulted in an increase in damage, indicating that ion energy is not the only cause of damage. Area, isolation edge, and source/drain edge contributions to gate oxide defect densities were calculated as a function of rf power during polysilicon etch. As rf power was increased, the area contribution increased the most, indicating that gate oxide damage from polysilicon etching is not an edge phenomenon but a surface phenomenon. The effect of gate oxide thickness was investigated. Damage increased significantly as gate oxide thickness was reduced. Finally, the rf triode etcher was compared with a microwave electron cyclotron resonance (ECR) et...

Erase performance improvement via dual floating gate processing

Abstract: A process for fabricating floating gates for electrically programmable and electrically erasable memory cells of the flash EPROM or EEPROM type. The floating gates are a three layer structure. The first layer of the floating gate is a thin polysilicon layer of approximately 300-500 Å thickness. The second layer is a silicon dioxide layer of approximately 20-30 Å. The third layer is polysilicon of approximately 1000-1500 Å thickness. The third layer is doped by implantation of phosphorous. This dopant is driven through the oxide layer to dope the first, thin polysilicon layer in a separate diffusion step or in subsequent high temperature processing. The grain size of the first, thin polysilicon layer is small and uniform from gate to gate due to the thinness of this layer and its light doping. This reduces variations in threshold voltage from gate to gate due to variable polysilicon grain size and orientation. This in turn results in improved yield and cycling endurance.

Silicide formation on polysilicon

Abstract: An integrated circuit includes a doped polysilicon/silicide ("polycide") gate electrode. The doped polysilicon layer comprises sub-layers. The sub-layers are formed by varying the silicon deposition conditions, typically including the deposition rate, while decreasing the dopant concentration. The metal silicide layer is then formed on top of the doped polysilicon layer. An improvement in uniformity and planarity of the structure is obtained as a result of stress accommodation. In addition, the sub-layers reduce the channeling effect that occurs during high energy source/drain dopant implantation. These effects allow for a reduced stack height of the gate electrode, resulting in improvements in very small (sub-micron) device structures.

Manufacturing method for SOI-type thin film transistor

Abstract: An SOI-type thin film transistor having a transparent insulating substrate a first gate electrode, a first gate insulating film, a semiconductor layer, a second gate electrode and a second gate insulating film which are respectively formed on the transparent insulating substrate, wherein the width of the first gate electrode and that of the second gate electrode are different from each other and as well as the thickness of the first gate insulating film and that of the second gate insulating film are different from each other

Positive control of the source/drain-gate overlap in self-aligned tfts via a top hat gate electrode configuration

Abstract: Positive control over the length of the overlap between the gate electrode and the source and drain electrodes in a thin film transistor is provided by a gate conductor layer comprising two different conductors having differing etching characteristics. As part of the gate conductor pattern definition process, both gate conductors are etched to expose the underlying material and the upper gate conductor layer is etched back to expose the first gate conductor layer in accordance with the desired overlap between the gate electrode and the source and drain electrodes. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the second gate conductor layer using a planarization and non-selective etch method.

Semiconductor device with reduced time-dependent dielectric failures

Abstract: An insulated gate field-effect transistor or similar semiconductor-insulator-semiconductor structure has an increased time-dependent dielectric failure lifetime due to a reduction in the field across the gate insulator. The electric field in the gate insulator is reduced without degrading device performance by limiting the field only when the gate voltage exceeds its nominal range. The field is limited by lowering the impurity concentration in a polysilicon gate electrode so that the voltage drop across the gate insulator is reduced. In order to avoid degrading the device performance when the device is operating with nominal voltage levels, a fixed charge is imposed at the interface between the gate electrode and the gate insulator, so at a gate voltage of about the supply voltage level the response changes to exhibit less increase in the drop across the gate insulator for higher voltages. Also, the impurity level in the gate electrode may be low enough so that the gate is in deep depletion for transient increases in gate voltage, thereby limiting the drop across the gate insulator.

Vertical floating-gate transistor

Abstract: An electrically erasable, programmable, read-only-memory, floating-gate, metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate. The floating-gate transistor is comprised of two source-drain regions, a channel region, a floating gate, a programming gate, and gate-oxide layers and is characterized by a floating-gate to channel capacitance that is small relative to the programming-gate to floating-gate capacitance, thereby allowing charging of the floating gate using programming and erasing voltages of less magnitude than might otherwise be necessary.

Circuit having charge compensation and an operation method of the same

Abstract: A residual charge removing circuit connected to a node in a power-on reset pulse generating circuit for removing positive charges which remain in this node when a power supply is turned off is disclosed. This residual charge removing circuit is formed of two N-channel MOS transistors connected in series between the node and the ground, and one capacitor. Out of the two N-channel MOS transistors, the transistor near the node has a grounded gate. The capacitor is connected between a gate of the transistor, out of the two N-channel MOS transistors, which is distant from the node, and a power supply. The gate of the transistor distant from the node is connected to a connection point between the two N-channel MOS transistors. Therefore, when a supply potential lowers below a threshold voltage Vth of the MOS transistors due to the power-off, the transistor distant from the node is turned off, so that a potential of the connection point becomes -Vth owing to a discharge of negative charges from the capacitor. This turns on the transistor near the node, so that the residual charges in the node are offset by the negative charges in the connection point.

High voltage lateral semiconductor device

Abstract: The present invention provides an improved lateral drift region for both bipolar and MOS devices where improved breakdown voltage and low ON resistance are desired. A top gate of the same conductivity type as the device region with which it is associated is provided along the surface of the substrate and overlying the lateral drift region. In an MOS device, the extremity of the lateral drift region curves up to the substrate surface beyond the extremity of the top gate to thereby provide contact between the JFET channel and the MOS channel.

Process for fabricating polysilicon resistors and interconnects

Abstract: A process for faricating polysilicon resistors and polysilicon interconnects coupled to MOS field-effect devices in a silicon substrate includes the steps of depositing and etching a first polysilicon layer to form the gates of the MOS devices; then depositing a second layer of polysilicon between the gates. The second polysilicon layer is then etched so that its upper surface is substantially coplanar with the gates. Contact openings are then defined to the source, drain and gate members of the devices through an insulative layer formed over the first and second polysilicon layers. Next, a metal layer is deposited to fill the openings and is patterned to define electrical contacts to the devices. The patterning step also defines the interconnect lines in the metal layer. A third polysilicon layer is then deposited and patterned to define the polysilicon resistors and interconnects.

Method of producing insulated-gate field effect transistor

Abstract: A polysilicon layer of approximately 500Å in thickness and a PSG layer approximately 3000Å in thickness are sequentially layered on a silicon wafer on which a gate insulating layer is formed; an opening having been formed in the PSG layer. After forming a side wall layer made of PSG of predetermined thickness in the opening, a second polysilicon layer for a leg portion of an inverse-T gate is embedded in the opening and both PSG layers are removed. Then, n - impurities are doped by ion implantation by using the second polysilicon layer as a mask, forming a LDD region. Another side wall layer is formed on the second polysilicon layer, and then, the first polysilicon layer, exposed outside of the second polysilicon layer and the side wall layer, is etched. Under the side wall layer, that polysilicon layer constituting a top of the inverse-T gate remains. Ion implantation is implemented by using the second polysilicon layer and the side wall layer as masks, such that a n + source and n + drain are formed. Since the n - impurities are doped by the ion implantation through the first polysilicon layer having an even thickness, the junction depth in the LDD region is constant. Additionally, since the thickness of the first polysilicon layer is small, the gate insulating layer reliably functions as an etch-stop in patterning the polysilicon layer.

CMOS semiconductor device with (LDD) NMOS and single drain PMOS

Abstract: A MOS semiconductor device and the methods for constructing the device. The MOS device provided with first and second MOS transistors are formed on two identical wafer sections. The impurity region of the first transistor and a first group of gate side wall spacers are aligned to the gate of the first transistor. The impurity region of the second transistor and a second group of gate side wall spacers are aligned to the gate of the second MOS transistor. The second group of gate side wall spacers have a thickness different from that of the first group of gate side wall spacers.

Bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture

Abstract: A floating gate electrically erasable MOS transistor comprising a silicon substrate having source and drain regions and a channel region disposed between the source region and the drain region. The source and drain regions are formed from a semiconductor material having one conductivity type, and the channel region is formed from a semiconductor material having a conductivity type opposite the conductivity type of the semiconductor material forming the source and drain regions. A control gate region is formed in the silicon substrate horizontally spaced apart from the channel region. The gate region is formed from a semiconductor material having the same conductivity type as the semiconductor material forming the source and drain regions. A polysilicon layer bridges the control gate region and the channel region for communicating an electrical potential from the first gate region to the channel region. A silicon dioxide layer is disposed between the polysilicon layer and the control gate and channel regions for insulating the polysilicon layer from these regions. The polysilicon layer thus serves the function of a floating gate, and is selectively controlled through the first gate region for forming a conductive channel between the source and drain regions. The drain region of the MOS transistor is coupled to the base terminal of a bipolar sensing transistor for forming an EEPROM.

Method of making extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor

Abstract: For a structure with an overlapping gate region, a first insulator layer is placed on a substrate. A source/drain polysilicon layer is placed on the insulator layer. The source/drain polysilicon layer is doped with atoms of a first conductivity type. A second insulator layer is placed on the source/drain polysilicon layer. A gap is etched in the second insulator layer and the source/drain polysilicon layer to expose a portion of the first insulator layer. The exposed portion of the first insulator layer and an additional amount of the first insulator layer under the second insulator is etched so as to enlarge the gap and to undercut a portion of the source/drain polysilicon layer. Two polysilicon filler regions are formed which fill a portion of the gap including the undercut area under the source/drain polysilicon layer. A gate polysilicon region is formed in the gap and extends over the source/drain polysilicon layer. The gate polysilicon region is separated from the source/drain polysilicon layer and the polysilicon filler regions by a dielectric region. Source/drain regions are formed by atoms in the source/drain polysilicon layer diffusing through the polysilicon filler regions into the substrate.

A method of simultaneously fabricating an insulated gate-field-effect transistor and a bipolar transistor

Abstract: An insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to another embodiment, the drain end of the conductive gate (434) is disposed on top of a thick insulator region (432) that also acts to mitigate the high electric fields present when the transistor is subjected to a high voltage transient.

The fabrication of metal–oxide–semiconductor transistors using cerium dioxide as a gate oxide material

Abstract: Cerium dioxide was employed as a gate insulator for an enhancement‐type n‐channel metal–oxide–semiconductor (MOS) transistor. Cerium was evaporated in a tungsten boat and immediately oxidized for oxide uniformity. The use of CeO2 as a gate oxide in MOS transistor yielded a low positive threshold voltage with negligible interface charge effects. This resulted in the transistor performing as an enhancement type device.

Gate drive circuit for insulated gate semiconductor device and flash controller using the circuit

Abstract: A gate drive circuit comprises first and second reverse-blocking switches, each composed of a serially connected transistor (101, 102) and diode (105, 106), which are connected in series between a gate drive power source (V GG ) and a ground for switching a gate drive current of an insulated gate semiconductor device (3). An inductance element (108) are provided between the junction point of the first and second reverse-blocking switches and the gate of the insulated gate semiconductor device (3) to induce LC resonance by the inductance of the element (108) and the gate input capacitance of the insulate gate semiconductor device (3). Thus, both small peak switching current of the switches and high speed switching of the semiconductor device (3) can be attained. Further, a flash controller can be reduced in its size and cost by using the above gate drive circuit for on/off driving an insulated gate semiconductor device inserted in a flash main circuit.

MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode

Abstract: A gate oxide layer, a polysilicon layer, and an oxidation-resistant layer are formed in sequence on a semiconductor substrate, the oxidation-resistant layer is patterned, then high-pressure oxidation is performed, oxidizing at least part of the polysilicon layer not covered by the oxidation-resistant layer and leaving, under the oxidation-resistant layer, a polysilicon gate electrode with tapered sides. The oxidized portions of the polysilicon layer are removed and two ion implantation steps are carried out with different accelerating energies and impurity doses, one step creating heavily-doped source and drain areas, the other step creating lightly-doped offset layers. The lightly-doped offset layers are at least partially located under the tapered sides of the gate electrode.

Static RAM memory cell using N-channel MOS transistors

Abstract: A floating gate NMOS enhancement mode transistor is utilized in an NMOS SRAM thereby reducing power consumption, size, and circuit complexity of the memory cell. The gate of the load transistor is allowed to float with no galvanic connection to the memory cell circuit. A bias voltage is induced on the gate of the load transistor by capacitances of the gate with the source, the drain, and the bulk semiconductor, and the conductance is maintained below conduction threshold. Gate bias is established by tailoring of the gate capacitances and by the removal of charge using UV light as necessary.

Non-volatile semiconductor memory cell

Abstract: Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

Thin film transistor having an improved gate structure and gate coverage by the gate dielectric

Abstract: A thin film transistor includes a two-layer gate metallization comprising a relatively thin first layer of a first conductor and a relatively thick second layer of a second conductor with the second conductor being capable of being etched with an etchant that produces substantially no etching of the first conductor layer. During device fabrication, the thick gate metallization layer (second conductor) is selectively etched until all of that material is removed in the openings in the mask. The thin lower layer (first conductor) is then etched with a minimum of etching into the substrate. The gate dielectric and subsequent layers deposited over this gate metallization have high integrity and highly reliable continuity because of the sloped nature of the gate metallization sidewalls, and because of the shallow gate metallization topography due to minimization of substrate etching during gate metallization patterning.

Method for manufacturing a multi-layer gate electrode for a mos transistor

Abstract: A multi-layer gate electrode is provided to prevent dopant depletion of a polysilicon in the manufacture of the electrode containing doped polysilicon and metal silicide. First, a multi-layer structure is produced containing a doped polysilicon structure, a diffusion barrier structure and a silicon structure. After deposition of a metal layer covering the multi-layer structure, a metal silicide structure is produced from the silicon structure and the metal layer in a tempering process. The diffusion barrier structure thereby prevents diffusion of dopant out of the polysilicon structure into the metal silicide structure. This may be used in a salicide process.

Process for producing an electrically conductive diffusion barrier at the metal/silicon interface of a MOS transistor

Abstract: An integrated circuit such as a MOS transistor, having an electrically conductive diffusion barrier at the metal/silicon interface and a method of manufacture therefor is disclosed. The metal/silicon interface is formed by selective metal deposition onto silicon. According to the method, the interface is subjected to a nitrogen-based plasma during a period of at least five minutes. The interface is brought to a temperature greater than 500° C. during this period, in order to create a diffusion barrier comprising a silicon nitride layer. The interface is then subjected to an annealing treatment under a neutral atmosphere so as to remove the nitrogen previously introduced into the metal. The diffusion barrier forms a linking and protecting interface between each source drain or gate zone of the MOS transistor and the corresponding layer of metal covering the latter.