Showing papers on "Mixed-signal integrated circuit published in 1985"

Inductive Fault Analysis of MOS Integrated Circuits

Abstract: Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integrated circuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statistical data from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classification of faults types and ranking of faults based on their likelihood of occurrence Hence, given the layout of an IC, a fault model and a ranked fault list can be automatically generated which take into account the technology, layout, and process characteristics. The IFA procedure is illustrated by its applications to an example circuit. The results from this sample led to some very interesting observations regarding nonclassical faults.

The Design of High-Performance Analog Circuits on Digital CMOS Chips

Abstract: Devices available in digital oriented CMOS processes are reviewed, with emphasis on the various modes of operation of a standard transistor and their respective merits, and on additional specifications required to apply devices in analog circuits. Some basic compatible analog circuit techniques and their related tradeoffs are then surveyed by means of typical examples. The noisy environment due to cohabitation on the chip with digital circuits is briefly evoked.

Bipolar and MOS Analog Integrated Circuit Design

Abstract: Integrated-Circuit Fabrication. Active Devices in Integrated Circuits. Passive Components: Diodes, Resistors, and Capacitors. Bias Circuits. Basic Gain Stages. Analog Design with MOS Technology. Operational Amplifiers. Wideband Amplifiers. Analog Multipliers and Modulators. Voltage Regulators. Integrated-Circuit Oscillators and Timers. Phase-Locked-Loop Circuits. Integrated-Circuit Filters. Data Conversion Circuits: Digital-To-Analog Converters. Data Conversion Circuits: Analog-To-Digital Converters. Index.

A 20-V four-quadrant CMOS analog multiplier

Abstract: A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range of input voltages. The MSO version of Gilbert's six-transistor cell (GSTC) is the basis for this multiplier. A simple source-coupled pair is used to study the MOS GSTC. Then, a technique is introduced for linearizing the source-coupled circuit. This scheme is extended to the MOS GSTC. The voltage ranges are further increased by introducing the folded CMOS GSTC.

A CMOS 8-Bit High-Speed A/D Converter IC

Abstract: A novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC. A 20-MHz sampling rate with 350-mW power dissipation from a single 5-V power supply has been realized. Integral linearity of /spl plusmn/ 1/2 LSB to 8-bit conversion has been achieved through intensive transistor dimension optimization applied to the comparator circuit, instead of employing an offset canceling technique.

A Wafer-Scale Digital Integrator Using Restructurable VSLI

Abstract: Wafer-scale integration has been demonstrated by fabricating a digital integrator on a monolithic 20-cm/sup 2/ silicon chip, the first laser-restructured digital logic system. Large-area integration is accomplished by laser programming of metal interconnect for defect avoidance. This paper describes the technology for laser welding and cutting, the design methodology and CAD tools developed for wafer-scale integration, and the integrator itself.

Performance comparison of analog and digital circuits

Abstract: It is the purpose of this paper to compare analog and digital semiconductor circuits. Using simple models, performance of these circuits will be evaluated as far as signal-to-noise ratio, power dissipation, bandwidth, and system capacity are concerned.

A monolithic silicon photodetector/amplifier IC for fiber and integrated optics application

Abstract: Described below are the primary primary design considerations, fabrication techniques, and measured performance bounds on a monolithic silicon photodetector/amplifier integrated circuit. The IC was designed for utilization in short- to medium-haul fiber-optic data links, performing signal processing, and isolation functions at data ratesup to 500 Mbit/s. Consisting of a p-i-n photodiode integrated monolithically with a multistage amplifier/limiter circuit, the device was fabricated with planar high-frequency bipolar transistors commonly used for ECL logic circuits. Circuit features include dc coupling, wide-band operation, and capability of driving 50 Ω at the output to 0.5 V (peak-peak). Measured device yield is an impressive 35 percent, indicating amenability to production constraints. Complimenting the IC design is a novel and practical optical coupling/packaging technique that renders the packaged device quite compact and compatible with accepted high-speed electronic layout techniques.

Electrical Characterization of Packages for High-Speed Integrated Circuits

Abstract: Advances in silicon bipolar and GaAs FET technology have enabled digital circuits of medium complexity to be fabricated for operation at gigabit rates. However, signal degradation caused by the packaging of these new devices will limit their useful application. A theoretical model to help assess this problem is discussed, and its predictions are compared with results from time domain reflectometry (TDR) and network analysis measurements. Also described is a novel exlension of the TDR technique based on the use of fast Fourier transform (FFT) analysis, including the design of test fixtures and the analysis software which is run on a desktop computer. The results presented demonstrate that both the model and the FFT measurement technique accurately represent the electrical performance of all those packages tested.

Remote testing system for electrical circuits

Abstract: An apparatus for remotely testing electrical circuits, such as telephone circuits, includes a stand-alone unit which is located in the end office, for example, for remote access by use of an ordinary push-button telephone set sending dual tone multiple frequency signals. The apparatus has a twin-bus structure wherein one of the busses is an analog bus through which the telephone link is made and over which analog test signals are communicated; the other bus is a digital bus for communicating digital control and data signals with a microcomputer included within the apparatus. Operating between the two busses are suitable interface circuits for receiving the control signals from the telephone set and for communicating the analog test signals to a selected electrical circuit to be tested. The analog test signals are generated by an analog test signal circuit also connected between the analog and digital busses. The microcomputer, connected only to the digital bus, controls the operation of the apparatus in response to dual tone multiple frequency control signals received from the telephone set. Responses from the test are transmitted to the remote site as synthesized speech signals for verbally communicating the results through the telephone set.

Fast Programmable 256K Read Only Memory with On-Chip Test Circuits

Abstract: A 32K X 8 bits EPROM which satisfies all requirements for a high-density EPROM, has been developed. The fast programming time is achieved by introducing a DSA structure into the memory cell. The low power consumption and fast access time are realized by utilizing n-well CMOS peripheral circuits. Various test circuits are implemented to alleviate lengthy screening time. Typical programming time, access time, and power dissipation are 3/spl mu/byte, 100 ns, and 5 mA, respectively.

A Receiver IC for a 1 + 1 Digital Subscriber Loop

Abstract: A receiver IC for a 1 + 1 digital transmission system is presented. It includes all the functions necessary for data recovery (high-pass filtering, automatic gain control (AGC), clock extraction, decision circuitry) and for supplying the control code to a separately integrated echo canceller. A total switched-capacitor (SC) approach with digital control is used and a complete description of the receiver architecture is given. The techniques for combatting errors introduced in the analog domain by clock feedthrough and digital crosstalk are described. A special purpose program is described which simulates the whole receiver and overcomes the problems arising from the mixed sampled data/digital nature of the design. The IC has been fabricated in a 3- /spl mu/m p-well CMOS process.

A Design Style for VLSI CMOS

Abstract: CMOS is an attractive technology for the realization of VLSI systems. However conventional static CMOS design techniques lead to circuits which are slower and much less densely packed than equivalent NMOS circuits. After a brief review of precharge-discharge techniques, a novel method for designing clocked dynamic CMOS is described. This uses a four-phsse clocking scheme that is free from race and charge-sharing problems and results in faster, more compact layouts. A test chip and a full custom 25 000 transistor serial signal processing chip have been designed using this technique. Results obtained by probing the test ship are presented.

Integrated circuit device testable by an external computer system

Abstract: An integrated circuit device for an electronic equipment having an internal bus, the integrated circuit device comprising a plurality of input terminals, a switch circuit connected to the plurality of input terminals for selecting any one of a respective plurality of input signals via the plurality of input terminals, a switch control circuit for controlling the switch circuit to select any one of the input signals in dependence on a selection signal, an analog-to-digital converter for converting the selected input signal from the switch circuit into a corresponding serial digital signal, and a bus interface circuit connected to the internal bus for sending the serial digital signal from the analog-to-digital converter to the internal bus and for sending the selection signal from the internal bus to the switch control circuit.

A data-driven multiprocessor for switch-level simulation of vlsi circuits

Abstract: In this dissertation I describe the algorithms, architecture, and performance of a computer called the FAST-1--a special-purpose machine for switch-level simulation of VLSI circuits. The FAST-1 does not implement a previously existing simulation algorithm. Rather its simulation algorithm and its architecture were developed together. The FAST-1 is data-driven, which means that the flow of data determines which instructions to execute next. Data-driven execution has several important attributes: it implements event-driven simulation in a natural way, and it makes parallelism easier to exploit. Although the architecture described in this dissertation has yet to be implemented in hardware, it has itself been simulated using a 'software implementation' that allows performance to be measured in terms of read-modify-write memory cycles. The software-implemented FAST-1 runs at speeds comparable to other software-implemented switch-level simulators. Thus it was possible to collect an extensive set of experimental performance results of the FAST-1 simulating actual circuits, including some with over twenty thousand transistors. These measurements indicate that a hardware-implemented, uniprocessor FAST-1 offers several orders of magnitude speedup over software-implemented simulators running on conventional computers built using similar technology. Additional speedup over a uniprocessor can be obtained using a FAST-1 multiprocessor, that is constructed using multiple FAST-1 uniprocessors that are interconnected by one or more broadcast busses. In order for a FAST-1 multiprocessor to exploit the parallelism available in simulations, the FAST-1 representation of circuits must be carefully partitioned onto the processors. Although, even simple versions of the partitioning problem are NP-complete, I show that an additional order of magnitude speedup can be obtained by using a multiprocessor FAST-1 and fast heuristic partitioning algorithms.

Hierarchical Circuit Verification

Abstract: One of the crucial steps in designing VLSI circuits is to verify the correctness of the layout of the circuitry. Traditionally, this verification step is done by first flattening out the circuit hierarchy. This approach requires a substantial amount of computational overhead even for circuits that are relatively small. In this paper, a connectivity verification algorithm which exploits circuit hierarchy is presented. This algorithm works most efficiently with big circuits and is therefore useful for verifying VLSI circuits.

Gutting chip-testing costs: Designing VLSI circuits for testability is the most efficient way to reduce the relative costs of assuring high chip reliability

Abstract: Testing now accounts for 10% of the total cost of manufacturing a 1-kb random-access-memory chip. For a 64K RAM chip, the figure rises to 40%. New techniques, however, promise to hold down costs by tackling the circuit-testing problem in the design stage. The new methods include computer programs that assess during design how easily a circuit can be tested, scan-design techniques for testing sequential circuitry, and ways of partitioning chips into blocks of manageable size for testing. Random testing and built-in self-testing are also employed in some cases to avoid exhaustive testing for every possible fault in a circuit. These new methods are described.

Device for translating a test sequence to a burn-in sequence for a logic circuit and/or a digital circuit, a method for burn-in operation of a logic circuit and/or a digital circuit

Abstract: In order to translate a test sequence into a sequence for burn-in operation of integrated logic circuits and digital circuits, the invention provides a method and a device for automatic translation of a test truth-table into a burn-in truth-table. In addition to the reduction in cost achieved by automatic generation of test sequence, a test performed after burn-in operation of a circuit permits reliable detection of a circuit fault since the same type of sequence is adopted both for burn-in and for testing.

Circuit for temporarily storing digital signals

Abstract: The circuit is based on the complementary integrated technique. The object is to design the circuit in such a way as to allow great tolerances of the characteristic values and consequently realisation on a relatively small semiconductor surface area, without needing to demand particular requirements of the geometrical form of this area. This is achieved by one circuit input (E) being connected via the series circuit of a field-effect transistor (T1) of the first channel type and two inverters (I1, I2) to a circuit node (Z), by the two inverters (I1, I2) being provided with a common feedback branch (1) which includes a field-effect transistor (T2) of the second channel type, and by the gate electrodes of the two field-effect transistors (T1, T2) being wired to a common clock voltage connection (TA). A development of the circuit envisages that a similarly constructed circuit (T3, T4, I3, I4), in which merely the channel types of the two field-effect transistors (T3, T4) are interchanged, is added, the circuit input of this further circuit being connected to the circuit node (Z). The range of applications comprises circuits for digital signal processing, in particular for the filtering of television signals.

A General CAD Tool for Large-Signal GaAs MESFET Circuit Design

Abstract: An accurate and general CAD tool for large-signal GaAs MESFET design has been developed It is based upon incorporation of an accurate GaAs MESFET model in the SPICE circuit simulation The tool has been utilized in the analysis of microwave power amplifiers, oscillators and mixers, and GaAs digital IC's Examples of some of these studies are presented

Integrated circuit devices

Abstract: An integrated circuit device (2) for an electronic equipment (1) having an internal bus (6), the integrated circuit device (2) comprising a digital-to-analog converter (11) for converting a serial digital control signal to a corresponding analog control signal, a plurality of circuits (A to E) subject to control in response to the analog control signal for performing specific functions, a switch circuit (12) for selecting any one of the plurality of circuits (A to E), a switch control circuit (13) for controlling the switch circuit (12) to select any one of the plurality of circuits (A to E) according to a received selection signal, an analog-to-digital converter (14) for converting an output signal from the switch circuit (12) into a corresponding digital signal, and a bus interface circuit (10) for sending the serial digital control signal from the internal bus (6) to the digital-to-analog converter (11) and for sending the selection signal to the switch control circuit (13).

Signal processing integrated circuit with AD or DA converter.

Abstract: In an IC used for a PCM communication system, for example, a CODEC circuit, the signal level in the circuit is required to be kept exactly to a specific value. In such a circuit, it is very difficult to keep a specific gain of the circuit because of the effects of filters and parasitic capacitances or parasitic resistances of the circuit, and so forth. The present invention provides a trimming circuit for the reference voltage of an AD or DA converter, by which the conversion gain of the AD or DA converter, and hence the gain of the CODEC circuit, can be trimmed in steps by blowing built in fuses. The present invention also provides a switched resistor circuit, by which the conversion gain can be switched, allowing processing of signals conforming to different conversion laws.

0.5-2.6 GHz Si--Monolithic Wideband Amplifier IC

Abstract: Using Si, an excellent performances, 0.5-2.6GHz bandwidth and 23dB gain, monolithic wideband amplifier IC has been developed, of which input and output impedances are matched to 50 Omega. The f/sub T/=10GHz DNP-11 manufacturing process with optimization for microwave analog ICs has been developed for this IC. And a single-ended three stages circuit with local feedback adopted for this monolithic amplifier loops is circuit.

High speed and high accuracy analog to digital converter

Abstract: An improved analog to digital converter in which an approximate digital representation is provided by a parallel analog to digital converter and the conversion is completed by a successive approximation analog to digital converter.

Spectrum spread communication system

Abstract: PURPOSE:To reproduce easily a carrier even if S/N ratio of a received signal is low, by providing a four phase PSK modulating circuit in the transmission side and providing a delay detecting circuit including a delay circuit and an LPF in the reception side and operating correlations between the output of the delay detecting circuit and a PN code having a phase different from that of the transmission-side PN code in the matched filter system. CONSTITUTION:A transmitting circuit of the spectrum spread communication system shown in a figure (a) is provided with a mixer 30, a PN code generator 31, and a four phase PSK modulator 32. In this transmitting circuit, a data signal d(t) and a PN code P(t) are mixed by the mixer 30, and the output is modulated by the four phase PSK modulator 32 and is outputted. Meanwhile, a receiving circuit shown in a figure (b) consists of a delay detecting circuit 41 which extracts a mixed signal of the data signal and the PN code from a received signal, a correlating circuit 42 which operates correlations between the output of the circuit 41 and the PN code having a certain relation to the transmission-side PN code, and a data signal demodulating circuit 43 which demodulates the data signal from the output of the circuit 42.

CMOS integrated circuits for multivalued logic

Abstract: The use of CMOS integrated circuits in the design of multivalued logic systems is extended. Circuit design of basic quaternary operators (inverters, NAND, NOR, cycling and inverse cycling gates) is presented. These basic quaternary operators can be used as building blocks in four-valued digital systems. The extension of these circuits to implement five-valued systems is also discussed.