Showing papers on "Multiplexer published in 1986"

A Markov Modulated Characterization of Packetized Voice and Data Traffic and Related Statistical Multiplexer Performance

Abstract: We study the performance of a statistical multiplexer whose inputs consist of a superposition of packetized voice sources and data. The performance analysis predicts voice packet delay distributions, which usually have a stringent requirement, as well as data packet delay distributions. The superposition is approximated by a correlated Markov modulated Poisson process (MMPP), which is chosen such that several of its statistical characteristics identically match those of the superposition. Matrix analytic methods are then used to evaluate system performance measures. In particular, we obtain moments of voice and data delay distributions and queue length distributions. We also obtain Laplace-Stieitjes transforms of the voice and data packet delay distributions, which are numerically inverted to evaluate tails of delay distributions. It is shown how the matrix analytic methodology can incorporate practical system considerations such as finite buffers and a class of overload control mechanisms discussed in the literature. Comparisons with simulation show the methods to be accurate. The numerical results for the tails of the voice packet delay distribution show the dramatic effect of traffic variability and correlations on performance.

Characterizing Superposition Arrival Processes in Packet Multiplexers for Voice and Data

Abstract: This paper analyzes a model of a multiplexer for packetized voice and data. A major part of the analysis is devoted to characterizing the aggregate packet arrival process resulting from the superposition of separate voice streams. This is done via the index of dispersion for intervals (IDI), which describes the cumulative covariance among successive interarrival times. The IDI seems very promising as a measurement tool to characterize complex arrival processes. This paper also describes the delays experienced by voice and data packets in the multiplexer using relatively simple two-parameter approximations.

Digital communication network architecture for providing universal information services

Abstract: A switched integrated wideband and narrowband multiservices digital network (FIGS. 1 and 2) is an ISDM providing universal information services based on wideband and narrowband voice, data, and video communications. It comprises a plurality of service areas (100, 101), each served by a central switching node (110). The central node is connected to a plurality of remote nodes (103) by feeder optical fibers (107) and a control bus extension (106). Network interface equipment (104) at subscribers' (102) premises is connected to remote nodes by distribution optical fibers (105). Each distribution fiber is wavelength-division multiplexed and carries modulated (pulse-analog, pulse-code, or differential pulse-code) wideband digital channels (205) and a multiplexed channel (206) comprising 32 time-division-multiplexed narrowband digital channels (207). One narrowband channel (207D) carries all signaling messages. Feeder fibers are wavelength-division multiplexed and carry modulated wideband digital channels (305), and multiplexed channels (306) each comprising a plurality of time-division-multiplexed distribution multiplexed channels. Each remote node comprises a digital space-division switch (505) for wideband channels, and a digital time-division multiplexer and demultiplexer (506) for multiplexed channels. Each central node comprises a digital space-division switch (606) for wideband channels, and a digital time-division switch (607) for narrowband channels. All switches are controlled by a central node control complex (612) over a control bus (116) and its extensions. Signaling messages are transferred between the signaling-message-carrying narrowband channels and the central node complex by a subscriber signaling subsystem (613) via the narrowband switch and the control bus. A central node optionally includes interfaces (615-618) to other communication systems, and trunk communication fiber (112) and CCIS signaling fiber (117) connections to other central nodes of the network.

Speech and data multiplexor optimized for use over impaired and bandwidth restricted analog channels

Abstract: The present invention relates to an apparatus and method for the simultaneous transmission of analog speech and modulated data, such apparatus and method being optimized for use over impaired and bandwidth restricted analog channels, or digital representations of such channels. In each instance of use, an evaluation is made of the available channel bandwidth, with a frequency division multiplex scheme allocating a voice sub-band, with data transmission allocated to sub-bands above, below, or around, this selected voice sub-band. The speech and data sub-band allocations are made by the multiplexor in response to user input of either a requested speech quality, a requested data rate, or a value indicating the relative user weighting of speech quality and data rate. A multi-carrier multi-mode modulation scheme is employed for data transmission, with this scheme having the ability to fully utilize the remaining bandwidth, and further, being capable of adapting to the impairments most likely present on the fringes of bandwidth restricted analog channels. When the analog channel employed is the standard voice-grade telephone circuit, good speech quality simultaneously with 3000 bps data transmission may be expected. The further ability to automatically switch to full bandwidth data transmission when voice transmission is not being attempted is also provided.

Holographic multiplexer/demultiplexer and its manufacturing method

Abstract: A holographic multiplexer and holographic demultiplexer, which has a diffraction grating formed of a hologram with an interference pattern produced by interference of two wave fronts, of which at least one wave front is of an aspherical wave and the other is of, for example, a spherical wave, and its manufacturing method are disclosed. The aspherical wave is used for correction of aberration and provided by obtaining the phase function φ G of the aspherical wave using a computer generated hologram and through an optical method or an electron-beam direct drawing method. The hologram serving as the diffraction grating for the holographic multiplexer/demultiplexer is produced by a two-beam interference method of an electron-beam direct drawing method. As the result, a holographic multiplexer/demultiplexer having a high degree of multiplexing, which is compact in size, and exhibiting low loss of light can be provided.

Apparatus for testing auto electronics systems

Abstract: An interactive system and method for testing vehicle electronics systems is disclosed in which various vehicle subsystems are exercised under the control of the tester unit while the performance of associated subsystems are monitored to detect and isolate malfunctions. The tester includes interchangeable program cartridges that can be easily inserted to adapt the unit for a variety of different vehicles and test procedures, and also optional interchangeable input/output cartridges for test procedures in which additional access to or from the tester or peripheral devices is necessary. The test unit accesses the vehicle's electronics data bus by means of an assembly line diagnostic link, the access being accomplished via a multiplexer that makes it possible to locate faults on the data bus itself. The tester greatly reduces the time and effort necessary to analyze malfunctions in the field, and is considerably more comprehensive than prior test equipment.

Optical fiber transducer driving and measuring circuit and method for using same

Abstract: Disclosed in an optical fiber transducer system with energy generating means for transmitting pulsing energy at various frequencies to bidirectional couplers for each frequency. The couplers record the intensity and further transmit the pulsing energy to a wavelength multiplexer/demultiplexer. The wavelength multiplexer/demultiplexer combines the plurality of energy supply means into a single output for an optic fiber which includes an optical delay sufficient to time separate the pulsing waves of energy. Reflected energy is transmitted back through the same wavelength multiplexer/demultiplexer, bidirectional coupler so that the recorded intensity of transmission and reflectance are comparable without system influence. A method is also shown for use of an optical fiber system including the components set forth and the system requires the generation and combination of the various frequencies of energy in a multiplexer/demultiplexer, the delay for time separation and the detection in a bidirectional coupler of transmitted and reflected energy.

Circuit breaker with digital solid-state trip unit fitted with a calibration circuit

Abstract: Microprocessor-based solid-state trip unit (48) processing digital signals derived from analog signals supplied by current sensors (16). The analog signals are applied to a calibration circuit (34), which adapts the output range of the analog circuits to that of the logic circuits, to obtain with an 8-bit Analog-to-Digital Converter (50) associated with a Multiplexer (29) a range equivalent to that of 12-bit processing systems.

Servo-control device for steering an articulated vehicle

Abstract: A servo-control device for steering an articulated vehicle comprising four analog detectors (30, 31, 32, 33, 34) respectively connected to control amplifiers (30', 31', 32', 33') whose outputs are connected to the inputs (30", 31", 32", 33") of a multiplexer (40). The latter is connected to the input of a converter (41) which converts the analog signals of the detectors into digital signals transmitted to a digital calculator (42) powered by an energy source (43). The output of the calculator (42) is connected to a converter (44) whose output signal amplified by the amplifier (45) is directed to a servo-control device.

Birefringent optical multiplexer with flattened bandpass

Abstract: A birefringent optical wavelength multiplexer/­demultiplexer (Fig. 2) includes a first polarization beam-­splitter (PBS), a first reflector (TIR), a plurality of birefringent elements (C1, C2, C3), a second reflector (TIR), and a second polarization beam-splitter (PBS). The plurality of birefringent elements are so oriented that each element introduces an additional sinusoidal component to the transfer function of the device that tends to effectuate a flattened transfer function.

Servo steering device for an articulated vehicle

Abstract: The present device comprises four analog sensors (30, 31, 32, 33) respectively connected to setting amplifiers (30', 31', 32', 33') of which the outputs are connected to the inputs (30'', 31'', 32'', 33'') of a multiplexer (40). Said multiplexer is connected to the input of a converter (41) which transforms the analog signals from the sensors into digital signals transmitted to an analog computer (42) supplied by a power source (43). The output of the computer (42) is connected to a converter (44) of which the output signal amplified by the ampifier (45) is sent to a servo-control device.

Two-dimensional finite impulse response filters

Abstract: A two-dimensional finite impulse response (FIR) filter comprises a demultiplexer (30) for demultiplexing an input data signal comprising adjacent digital words into p (e.g. 2) slower data signals each having a slower rate equal to 1 /p (e.g. 1 2) of the data rate of the input signal and each comprising every pth (e.g. every alternate) word of the input signal. The slower data signals are passed to p(e.g 2) filter portions (80, 82) each comprising a horizontal FIR filter (32, 34)and a vertical FIR filter (84, 86). The horizontal filters (32, 34) are each connected to receive all of the slower data signals and all of them are operative simultaneously to effect horizontal filtration by periodically processing sets of adjacent words of the input signal, the sets of adjacent words being processed at any one time by the respective horizontal filters (32, 34) being offset with respect to one another by one word. A multiplexer (36) receives output signals of the filter portions (80, 82) to form a filtered output data signal having a data rate equal to that of the input data signal.

Design and performance of blocked-impurity-band detector focal plane arrays

Abstract: Blocked-Impurity-Band (BIB) extrinsic silicon (Si:As) detectors have demonstrated high sensitivity and quantum efficiency in the long wavelength infrared (LWIR) spectral region (to 28 microns) as well as wide frequency response, low optical crosstalk, nuclear radiation hardness, and stable, predictable performance. Furthermore, it has been demonstrated that SWItched mosFET (SWIFET) multiplexers provide a low noise readout approach for use with BIB detectors. This paper describes the state-of-the-art of multiplexed BIB detector hybrid focal plane arrays (HFPAs). The principle of operation and performance of optimized BIB and Back Illuminated BIB (BIBIB) detectors are presented. The SWIFET multiplexer, including necessary circuitry for BIBIB detector readout, has been designed and fabricated using a newly developed process for cryogenic (<20K) MOS electronics which avoids anomalies (lack of device isolation, excess noise, and long time constants) associated with conventional silicon processes. A description of the design and operation of this multiplexer is given. A number of uniform, highly responsive, 500 element HFPAs have been fabricated and their performance evaluated. The characterization measurements, to be described in the paper, include evaluation of detector dark current, responsivity, noise for various operating conditions, and uniformity of array characteristics. The results obtained and presented demonstrate that focal plane arrays with excellent, unprecedented, LWIR performance have been realized with Blocked-Impurity-Band detector technology.

Semiconductor memory device

Abstract: PURPOSE:To obtain a semiconductor memory device which uses a dynamic RAM by a performing memory access or a refreshing operation which is requested earlier on priority basis by using a contention evading circuit. CONSTITUTION:The contention evading circuit LOG generates the control signal -RR or -MR of a multiplexer MPX as an address selector which supplies an address signal RADD for refreshing or MADD for memory access selectively to memory blocks MB0 and MB1 according to either of signals -R0+-R1 and -MAQ which arrive earlier. The refreshing operation signal -RR generat ed by the contention evading circuit is utilized as a stepping pulse of a refresh address generating circuit ADC.

Dynamically focused linear phased array acoustic imaging system

Abstract: An acoustic imaging system having an array of N transducers arranged for transducing transmit electrical signals into acoustic pulses and for transducing acoustic pulse echos into electrical receive signals has a transducer multiplexer that connects in substantially cyclic order any one of a selected group of M adjacent transducer elements to one of a plurality of substantially identical transmit or receive channels. Each channel includes phase changing means for dynamic focusing, such as a mixer driven by one of a plurality of individually phased clocks. A control demultiplier orders connection of an appropriate one of the differently phased clocks to the mixer of each channel in an order precisely corresponding to the cyclic ordering of the transducer connections by the transducer multiplexer as groups of M adjacent transducer elements are selected to form acoustic scan lines stepped across the entire array.

A Conceptional Design on Optical Frequency-Division-Multiplexing Distribution Systems with Optical Tunable Filters

Abstract: Optical frequency-division-multiplexing distribution systems providing more than ten frequency multiplexed optical signals separated by on the order of gigahertz, distribute signals to plural receivers, where one of the signals is selected by a frequency selection switch (FS-SW). This paper describes the design of an optical frequency-divisionmultiplexing distribution system. Investigation is made of periodic filters for frequency division multiplexers and FS-SW, and the optical source, as well as single-mode fiber polarization mode dispersion. Preliminary transmission experiments using a bit rate of 450 Mbits/s, fiber length of 13 km, and frequency spacing of 11 GHz are also demonstrated at a 1.5 μm wavelength to show the design's suitability.

Arithmetic logic and shift device

Abstract: A device which includes an arithmetic logic unit and a data shifter--e.f. a barrel shifter. The outputs of these are cross-coupled to their inputs by separate feedback connections. A third feedback connection is provided between the output of the arithmetic logic unit and another of its inputs. For added versatility in operation, registers at the output of the arithmetic logic unit and the barrel shifter may include each a selectable by-pass and/or additional registers may be included in parallel therewith. The device is reconfigured by the control of input multiplexers interposed between the feedback connections and the arithmetic logic unit and the barrel shifter.

Apparatus for providing cost efficient power measurement

Abstract: Power measuring apparatus including a first multiplexor having its inputs responsive to the polyphase voltage and current inputs being measured. The multiplexor reads these inputs in sequence based on address signals provided by a program controlled microprocessor. The output of the multiplexor is coupled to an RMS to DC converter, the output of which is coupled to a second multiplexor. The voltage inputs are coupled to a voltage averaging device, the output thereof being coupled to additional inputs of the second multiplexor, the output of the second multiplexor being coupled to the microprocessor via an analog to digital converter. The microprocessor reads and compares the voltage output from the averaging circuit and the corresponding voltage at the output of the converter and generates a correction factor and responds thereto. The microprocessor to periodically adjusts the digital value of the voltage from the averaging circuit in response to the correction factor, the adjusted signal being coupled to display means for visual readout. A third multiplexor is provided to detect polyphase voltages and currents. The outputs of the third multiplexor are coupled under the control of the microprocessor to an analog multiplier in a time shared manner via voltage and currents scaling devices such that each phase voltage and corresponding current is simultaneously coupled to the multiplier. The output of the multiplier is coupled to a low pass filter, the output of which corresponds to the kilowatt power consumed for that phase. The microprocessor is capable of calculating a system power factor.

Report: Parallel scrambling techniques for digital multiplexers

Abstract: Scrambling of a digital bit stream is required in order to reduce interference (by randomizing a bit stream), to provide a high transition rate, and to suppress static pattern-dependent jitter.1,2 Two fundamental scrambling techniques, self- and frame-synchronous scrambling, are widely used in transmission systems. Self-synchronous scrambling has an error multiplication effect and may not work properly for consecutive input of zeros and ones.3 For a certain periodic input, the scrambled sequence has a periodicity the same as that of the input.1

Wavelength division optical multiplexer/demultiplexer

Abstract: A wavelength division multiplexing or demultiplexing optical coupler of the diffraction grating type includes a pure fused silica optical element having a convex spherical surface on one end and a diffraction grating on a portion of its other end The remaining portion of its other end receives a multiple fiber array for transmitting and receiving the light to be multiplexed or demultiplexed

Higher order digital transmission system including a multiplexer and a demultiplexer

Abstract: Higher order digital transmission system including a multiplexer having N parallel inputs to which tributary input signal streams are applied, and a demultiplexer having N parallel outputs from which the tributary signal streams are taken. The signal processing operations, such as scrambling, justifying, line coding, error monitoring and word synchronization are effected before the multiplexer and after the demultiplexer, consequently not at the full line rate.

Data processing system

Abstract: A data processing system having an arithmetic unit is designed for a multiplication of n-place numbers in 2's complement according to the Booth algorithm, and for division of unsigned numerals. A 2n-stage shift register is connected over a logical control circuit to the operation code inputs of an ALU. The control circuit automatically forms instruction code signals to the ALU as a function of informational bits derived from the shift register, whereas other operation code input signals are directly connected to the operation code inputs. The control circuit is a sequential circuit having a multiplexer for the selective through-connection of the multiplication code signals, the division code signals, or other operation code signals to the operation code inputs of the ALU.

A 4:1 time-division multiplexer IC for bit rates up to 6 Gbit/s based on a standard bipolar technology

Abstract: A 4:1 time-division multiplexer (MUX) IC for future communication systems is described which can be operated up to 6 Gb/s at a supply voltage of 5 V. It was fabricated in a silicon planar technology similar to current production technologies with rather conservative 2-/spl mu/m design rules but without needing poly-silicon emitter and super self-aligned processes. The high operating speed was mainly achieved by using a two-stage circuit concept and by careful optimization.

Memory access control circuit

Abstract: Memory address signals (UA, LA) consisting of upper and lower address signals output from a memory access circuit (11) are retained by an address counter (12). An address comparator (16) compares the upper address signal retained by the address counter (12) and the next upper address signal (UA) from the memory access circuit (11). If these upper address signals coincide with each other, a multiplexer (13) is controlled by a timing control circuit (17), and only the lower address signal (LA) held by the address counter (12) is supplied to a memory (18) via an address bus (14). However, if the above upper address signals do not coincide with each other, the multiplexer (13) is controlled by the timing control circuit (17). In this case, the upper and lower address signals retained by the address counter (12) are multiplexed, and the multiplexed signals are supplied to the memory (18) via the address bus (14). The timing control circuit (17) also supplies a row address strobe signal (R AS) and a column address strobe signal (C AS to the memory (18).

Remotely controlled sound mask

Abstract: A sound masking apparatus especially useful for setting background noise levels in discrete zones includes a signal source, power amplifier, programmable attenuator and remote control. The remote control is a short range radio transmitter that sends a series of pulses that are decoded to control the attenuator. The attenuator selects among discrete possible volume levels using serially-connected analog multiplexers, the multiplexer-selected lines connecting the signal to a desired part of a resistor network defining voltage dividers. The short range radio control makes a single remote controller operable to control volume levels in any zone of a multiple zone installation without direct access to the signal source, whereby the user can change volume levels in small increments to accomodate changing conditions or preferences and to slowly bring sound masking units to full volume levels.

Programmable logic device with buried registers selectively multiplexed with output registers to ports, and preload circuitry therefor

Abstract: A programmable array logic device including a programmable logic array, at least one register pair, a multiplexer coupled to the register pair so that they can share a common I/O pin, and an observability buffer for controlling the multiplexer. A dual clock buffer is provided so that registers within the register pair can be clocked singly when in a preload mode or together when in a logic or verification mode. When in the logic mode, either the output of a buried state register or an output register is observed at the I/O pin under the control of a product term generated by the logic array. When in the preload mode the register to be preloaded is selected by an externally provided preload select signal. In the verification mode, which typically follows a programming mode, individually selected product terms within the logic array can be observed by clocking them into the register pairs.

Data packet multiplexer/demultiplexer

Abstract: A Multiplexer/Demultiplexer for transmitting packetized data between a processor and a Pulse Code Modulation (PCM) bus. First-in First-Out (FIFO) shift registers, serial-to-parallel and parallel-to-serial converters and associated timing and control circuits are utilized to perform the packetized data transmission.

Cellular processor apparatus capable of performing floating point arithmetic operations

Abstract: A processor apparatus which is capable of performing floating point arithmetic. The processor apparatus includes a plurality of individual processing cells which are interconnected from left to right in a chain so that any of the processor cells can operate to receive a bit of any slice in a digital word. Each cell includes a memory which essentially is coupled via a multiplexer to an arithmetic logic unit, a controllable multiplier quotient store, a controllable loop path, and controllable status path device. Each of these devices are under control of a control mechanism which is included in the cell, and therefore each path can be connected to any other path via various multiplexers utilized in the circuitry. Essentially, each cell includes a multiport RAM, programmable logic arrays which implement the control logic plus path logic which provides the communication between neighboring cells. In order to command a particular 1-bit processor to perform as a particular bit in a floating point word, a multiplicity of slice types is defined. Hence the floating point implementation requires 15 slice types to handle all different combinations of bit operations that must be performed. The logic is such that defective 1-bit processors appear invisible so that data can flow across them without interference. The cell is a relatively unified structure whereby each cell can be thus commanded to perform a particular operation on a particular slice of a given word independent of the operation of any other cell.

Semiconductor memory having multiple continuous access functions

Abstract: A pseudo static RAM is provided which uses a one MOSFET dynamic RAM cell, in which two functions of a page mode and a static column mode are realized by using an address buffer having a function to transmit address signals fed from external terminals as they are and a latch function to latch the address signals fed from the external terminals in synchronism with predetermined control signals fed from the external terminals The address buffer also has a multiplexer function to selectively incorporate the address signals from the external terminals and the address signals produced in the inside of the RAM so that the address buffer and an internal address signal generating circuit may be controlled by external control terminals to make possible the continuous access by the internal address signals

Exact Simulation and Sensitivity Analysis of Multiplexing Networks

Abstract: This paper presents a novel approach to the simulation and sensitivity analysis of multiplexing networks. All computations are performed efficiently utilizing the concept of forward and reverse analysis which is elegant and effective in cascaded circuit analysis. Formulas are derived for such responses as input or output reflection coefficient, common port and channel output port return losses, insertion loss, gain slope, and group delay. Exact sensitivities w.r.t. all variables of interest, including frequency, are evaluated. The fundamental assumption is that the transmission matrices for the individual components of the network and their sensitivities w.r.t. possible variables inside them are available. An explicit algorithm is provided describing the details of the computational aspects of our theory. The formulas are applied to the optimal design of practical contiguous or noncontiguous band multiplexer consisting of multicavity filters distributed along a waveguide manifold. An example of optimizing a practical 12 channel, 12-GHz contiguous band multiplexer without dummy channels, which is the state-of-the-art structure used as the output multiplexer in satellite transponders, is presented.