Showing papers on "Nanoelectronics published in 1995"
Journal Article•
TL;DR: The International Nuclear Track Society (INTS) as discussed by the authors is a non-profit organization dedicated to the registration of ion trajectories in optical microscopes, which is based on the concept of "etch tracks".
Abstract: It is known since about half a century ago tha.t energetic ions, after their passage through most insulating materials, modify a certain zone aloiig tlieir trajectory, the so-called latent ion track, whicli is permanently visible in e.g. the transmission electron microscope (TEM). The possibility to document iii this way tlie existence and fate of individual ions has had a big impact on many fields of science and teclinology, sucli as geology, mineralogy, oil exploratioii, paleontology, medicine, biology, materials science, space science, planetary science, nuclear physics, and nuclear chemistry. In most cases however, one does not observe nowadays these latent tracks themselves, but instead one makes use of a very specific property of them, whicli is the enhanced etchability in agressive (mostly alkaline and oxydizing) solutions a property whicli may exceed the one of tlie corresponding bulk materials by orders of magnitude. Thus, by removing the chemically modified and hence sensitive part of the latent tracks, holes are created with diameters in the order of inicrometers (so-called \"etch tracks\"), whicli are easily visible in optical microscopes, and thus open the way for more rapid ion tracli registration. Due to the importante of this technology, even an international society has been formed tlie \"Nuclear Track Societyl\" l , which holds ma' The International Nuclear Track Society (INTS), Secretary: Dr. P.Vater, Phillips-Universitat Marburg, Germany ; temporary president: Dr. V.P. Perelygin, Dubna, Russia jor meetings in different places of tlie world every two years[ll.
32 citations
TL;DR: In this paper, the authors used electron beam evaporation of graphite for covering the surface of Si substrates and obtained multilayer Iidjima tubules standing close to each other.
18 citations
TL;DR: In this article, a new approach to the fabrication of model structures for nanoelectronics with characteristic sizes down to 10 nm is proposed, which consists in electron-beam-induced fabrication of self-supporting structures of nanometre sizes in a through slit formed in the substrate, followed by the deposition of a required material onto the structure, which serves as an active layer in a nanometric-scale device.
Abstract: A new approach to the fabrication of model structures for nanoelectronics with characteristic sizes down to 10 nm is proposed. The approach consists in electron-beam-induced fabrication of self-supporting structures of nanometre sizes in a through slit formed in the substrate, followed by the deposition of a required material onto the structure, which serves as an active layer in a nanometre-scale device. Features of the fabrication steps are discussed. Bismuth nanobridges were fabricated and their voltage-current characteristics were measured, which demonstrated features of electron transport in these bridges connected with their small sizes and inner structures.
18 citations
07 Aug 1995
TL;DR: In this article, a new proposal for silicon nanoelectronics based on STM/AFM lithography, selective deposition of epitaxial silicides, and heterolayer overgrowth is presented.
Abstract: This paper outlines a new proposal for silicon nanoelectronics based on STM/AFM lithography, selective deposition of epitaxial silicides, and heterolayer overgrowth. The all-UHV process we envision is completely planarized, and could eventually permit fabrication of 3-dimensional devices and circuit architectures with an unlimited range of possibilities.
4 citations
IBM1
TL;DR: The ability to reduce device features to increasingly smaller dimensions offers the potential for remarkable circuit performance and low power consumption as discussed by the authors, however, continued scaling of devices beyond 100 nm dimensions faces various fundamental limitations.
Abstract: The ability to reduce device features to increasingly smaller dimensions offers the potential for remarkable circuit performance and low power consumption. CMOS (Complementary Metal-Oxide-Semiconductor) devices with 100 nm channel lengths offer a 2X performance gain over 0.25 μm technology at a reduced power supply as well as the potential for a 20X reduction in active power at comparable performance levels. Continued scaling of devices beyond 100 nm dimensions faces various fundamental limitations. Overcoming these limitations will require technological innovation in both device design and fabrication.
1 citations
01 Jan 1995
TL;DR: In this paper, a numerical simulation of the dynamics of electrons entering a two-dimensional mesoscopic region through a point contact is presented, and the simulation results show that the point contact can be used to estimate the velocity of the electrons.
Abstract: Ballistic and quasi ballistic transport in mesoscopic systems is, today, a fundamental tool for the investigation of electronic processes in semiconductors, leaving alone its potential interest for sophisticated nanoelectronics. In the present paper we present some results of a numerical simulation of the dynamics of electrons entering a two-dimensional mesoscopic region through a point contact.
06 Jun 1995
TL;DR: In this paper, the behavior of electrons in devices can be treated with the effective mass approximation and the random phase approximation, and new circuit implementation techniques are to be explored in nanoelectronics.
Abstract: Microelectronics is a semi-classical electronics from the viewpoint that the behavior of electrons in devices can be treated with the effective mass approximation and the random phase approximation. On the other hand nanoelectronics is a quantum-mechanical electronics with full use of properties of electron waves, of artificial mini-Brillouin zones, of size dependent energy eigenstate structures and of Coulomb blockade of electron tunneling. New circuit implementation techniques are to be explored in nanoelectronics.