Showing papers on "Page layout published in 1997"

Optimal Layout Design in Multipurpose Batch Plants

Abstract: Plant layout is concerned with the spatial arrangement of processing equipment, storage vessels, and their interconnecting pipework. Deciding a good layout is an important activity in the design of chemical and process plants. A good layout will facilitate a correct operation of the plant. It will also provide an economic acceptable balance between the often conflicting constraints deriving from safety, environment, construction, maintenance, operation, space for future expansion, and process relationships such as those determined by gravity flow. This paper presents a mathematical formulation for addressing the problem of allocating items of equipment in a given two- or three-dimensional space. The objective function to be minimized is the total pumping, connection, and floor construction cost. Detailed cost factors are used to account for the flow direction between two connected units. The problem is formulated as a mixed integer linear programming model. Specific attention is paid to constructing a for...

System, method, and program for using animations to show page layout combinations in a user interface for submitting print jobs

Abstract: The system, method, and program of this invention allows a user to specify one of a plurality of print layout combinations Upon specifying a specific combination, an animation, embedded in the graphical user interface and within the dialog for making the selection, shows the page layout and rotates the sheet, about the applicable axis of the sheet, from front to back to show how the selected page layout would appear Numbers on the animated sheet are used to show the layout of sequential pages Numbers are used instead of displaying specific page content The animation gives a clear practical way of visually conveying to a user how a specified page layout combination would appear when printed

A Methodology for Optimally Designing Console Panels for Use by a Single Operator

Abstract: A seven-step methodology is presented to determine a dimensionally correct optimal layout of a console panel for a single operator. This methodology integrates the steps in the layout design process and uses a mathematical optimization model from facility design to obtain the optimal panel layout. A major difference in this methodology from previous work is that the mathematical optimization model incorporates factors that are only partially included in previous mathematical models. In addition, it includes the areas of the panel components as a new factor. This methodology is illustrated by the design of a nuclear power plant console panel.

Automatic Yellow-Pages pagination and layout

Abstract: The compact and harmonious layout of ads and text is a fundamental and costly step in the production of commercial telephone directories ("Yellow Pages"). We formulate a canonical version of Yellow-Pages pagination and layout (YPPL) as an optimization problem in which the task is to position ads and text-stream segments on sequential pages so as to minimize total page length and maximize certain layout aesthetics, subject to cons~aints derived from page-format requirements and positional relations between ads and text. We present a heuristic-search approach to the YPPL problem. Our algorithm has been applied to a sample of real telephone-directory data, and produces solutions that are significantly shorter and better than the published ones.

Layout design apparatus

Abstract: A layout design apparatus for arranging circuit elements and routing the circuit elements to perform a layout design of a logical circuit, includes path delay analysis means for performing delay analysis processing on a layout result which is obtained by performing a layout design of a logical circuit with a predetermined method, relay buffer insertion means for performing a logical alteration of the logical circuit to reduce the delay error when a delay error exists in the layout result through the delay analysis processing, and incremental routing means for rerouting the layout result in accordance with the result of the logical alteration by the logical altering means.

Optimal Robot Motion Planning and Work-Cell Layout Design

Abstract: This paper describes an interactive software system, developed at the Robotics and Automation Laboratory at UCLA to demonstrate innovative approaches to off-line robot programming and work-cell layout design. The software computes the time-optimal motions along specified paths, local optimal paths around an initial guess, and the global optimal path between given end-points. It considers the full robot dynamics, actuator constraints, on the payload acceleration or the gripping force, and any number of polygonal obstacles of any shape. The graphic displays provide a useful tool for interactive motion planning and workcell design.

LSI layout design method capable of satisfying timing requirements in a reduced design processing time

Abstract: An LSI layout design technique is disclosed which has the ability to satisfy LSI timing constraints in a short processing time. A netlist descriptive of a target circuit that is designed is fed to a computer, and a flip-flop netlist representing information about connections among flip-flops relating to the timing constraints, is generated from the netlist. Such a flip-flop netlist is generated by clustering using a flip-flop as a seed. According to the generated flip-flop netlist, each flip-flop is placed and a flip-flop region to place therein a cell relating to a flip-flop is determined. A cell relating to a corresponding flip-flop is placed in a flip-flop region and the cell arrangement is improved throughout the placement region. Based on the improved cell arrangement, a layout is designed.

Copying device and control method therefor

Abstract: PROBLEM TO BE SOLVED: To copy data and the image of the original, which are inputted by image scanning on paper, and to transmit them to a network by using a copying machine for storing the image information on a page by associating it with page identification information, taking out image information corresponding to page identification information from a storage part and copying or printing information on paper SOLUTION: In a digital composite machine 1, master form printing is to allocate page ID peculiar to the page becoming a master form, to execute page printing with a graphic code showing page ID and to store printing data of the page by associating it with a given page ID Since the graphic code showing page ID is printed in a prescribed part on paper which is master form- printed, original printing data can be taken out by recognizing the graphic code showing page ID from the scanned data of the master form

Incorporating manufacturing objectives into the semiconductor facility layout design process: A methodology and selected cases

Abstract: This paper presents a methodology that provides a vehicle for the selection and ranking of layout design objectives. Moreover, the same methodology can be used to create a decision matrix to evaluate different alternative layouts under analysis. In this case, the methodology combines the ranking of the layout objectives with the relative performance of each layout alternative along each objective in order to recommend the "best" layout alternative. This structured methodology is based on a decision making tool known as the Analytical Hierarchy Process (AHP). These concepts are illustrated through several case studies taken from actual layout design projects in the semiconductor manufacturing industry.

Networked VR system: kitchen layout design for customers

Abstract: In this paper, we present our Virtual Reality (VI?) technology application, a networked VR-supported design system of a kitchen layout. This networked VR system was developed on personal computers to allow customers to design at home. Whh the VR system, customers can have a pseudo-experience of their “virtual kitchen”, modify the design of the kitchen, and make decisions by being provided with a good idea of their potential purchase. The VR system will also play an important role in user interface in the House Design Advisory System. This system, which we are currently developing, will give advice on house design, as well as on kitchen layout design, according to the customers’ diversified lifestyles. Category: applications

An approach to layout and process verification for microsystem physical design

Abstract: The physical phases of microsystem design are concerned with generating all data needed to fabricate microstructures. As lithography-based technologies are used to fabricate MEMS, this includes the design of two-dimensional mask layouts as well as the design of process step sequences and parameters which determine the object extensions in the third dimension. LIDO is a MEMS physical design system that supports this concurrent design strategy by providing tools to easily configure appropriate process sequences, to derive consistent sets of geometric layout design rules from them and to use these design rules to verify mask layouts.

Method and apparatus for automatically modifying document layout

Abstract: A method and apparatus for repositioning a content object on a page in response to a request to change the page framework associated with the page, the method including receiving a user request to change the page framework. The current page framework information associated with the page is retrieved including a description for each framework member in the current page framework. Alignment data for the content object is derived by determining if any edge of the content object aligns with a framework member. Thereafter, the page layout is redefined according to the user request. Finally, the content object is repositioned on the redefined page based on the alignment data.

Before dynamic simulation: systematic layout design from scratch

Abstract: Excellent production design and planning depends on accurate simulation of a high quality layout. A good layout project will always begin With an analysis of the production volumes of the products with common process sequences and tool requirements in order to create manufacturing families. For each of these families you can select the "best manufacturing practices" that need to be used and re-engineer the processes and tooling to fit the desired throughput and inventory requirements. Once you know the manufacturing practices to be used for each family, you can begin developing layouts through a systematic flow and non-flow evaluation process. Static flow and relationship analysis software tools FactoryFLOW and FactoryPLAN/OPT lend themselves to a systematic process leading to effective layout design in record time.

An incremental declarative modelling applied to urban layout design

Abstract: In this paper, we present an interactive declarative modelling approach devoted to the design of urban layout. Declarative modelling palliates the weaknesses of imperative techniques. The scene model is described by means of properties without knowing explicitly its geometrical model. From a scene description a set of solutions fitting the properties is obtained. In our approach, the designer describes the urban layout with a description language in an hierarchical and incremental way. The scene description is translated in a constraint graph which is instanciated to compute one solution or a few solutions using a constraint propagation algorithm and a scene generation model. From the scene generation model providing a particular solution, a geometric model (2D map) is extracted. A 3D model of the urban environment can be generated for urban simulations or virtual reality applications.

Method and device for designing plant layout

Abstract: PROBLEM TO BE SOLVED: To easily comprehend the contents of design by automatically preparing and displaying the layout according to constraint conditions of arranged equipments or the like when performing the layout design or the like through the three-dimensional (3D) model of a plant SOLUTION: At an arrangement information corrector 7, arrangement information is automatically corrected so as to reduce the evaluated value of the arrangement information Besides, the 3D model is prepared by using that information and the layout design is automatically performed through the 3D model of the plant When generating the 3D model, an attribute value such as a price is simultaneously generated and estimation work is automatically performed as well When the ground of construction is to be determined before or after the determination of arrangement of respective functions by using the arrangement information corrected by the arrangement information corrector 7 or group classification information, that determination can be made correspondent to timing of before or after the arrangement determination Further, the layout design result is displayed out through various methods so that everyone can easily comprehend the design contents

Layout design of integrated circuit and computer-readable record medium recorded with layout design program

Abstract: PROBLEM TO BE SOLVED: To estimate an optimum delay time and an optimum layout area which should be realized by a changed layout, before executing the changed layout in the layout design of an integrated circuit. SOLUTION: An original layout is generated by logic synthesis based on timing specifications, and then a delay time in the original layout is calculated. It is discriminated whether the calculated delay time meets a specified value. If it is satisfied, of the layout design is finished. In case it is not satisfied, logic synthesis is executed over again and cells are rearranged, based on the result of the logic synthesis to generate a new net list. Based on a coefficient of proportionality C determined based on an optimum cell spreading rate which is determined from the relation between the cell spreading rate and the delay time and the new net list, an area which is changed layout should have is estimated, and then a new layout is generated in a region having the changed area. Until the new layout meets the specified value, the process from the calculation of a delay time to the generation of a new layout is repeated. COPYRIGHT: (C)1999,JPO

Automatic layout apparatus and method used in analog LSI layout design

Abstract: An automatic layout apparatus for laying out elements includes a connection information storage area, an extracted-element storage area, a layout condition file, an element layout section, a layout candidate element extraction section, a layout candidate element selection section, and a selected-element determination section. An element is laid out by the element layout section. A layout candidate element is extracted by the layout candidate element extraction section on the basis of the result of the element layout section and information of the connection information storage area. Information about the extracted layout candidate element is stored in the extracted-element storage area. The layout candidate element is selected by the layout candidate element selection section on the basis of the result of the layout candidate element extraction section or the information stored in the extracted-element storage area and information stored in the layout condition file. The selection result is determined by the selected-element determination section. When a layout candidate element must be selected again on the basis of a determination result, a layout candidate element is selected by the layout candidate selection section. A layout method for the apparatus is also disclosed.

Solving regional constraints in components layout design based on geometric gadgets

Abstract: This paper proposes a new method for dealing with geometrical layout constraints. Geometrical layout constraints are classified into three classes of dimensional, regional, and interference constraints. Dimensional constraints are handled by using an existing methodology. A method is proposed to translate the other two classes of constraints into dimensional constraints. Thus, it is possible to uniformly deal with all of those geometrical layout constraints. The method is twofold. First, it converts regional, interference constraints into a set of simple inequalities. Then each inequality is solved by a geometric gadget, which is a structured set of dimensional constraints. A prototype system is developed and applied to some layout design examples.

Method and apparatus for fixed canvas presentations using HTML

Abstract: Apparatus, methods, systems, and computer program products are disclosed for displaying fixed canvas presentations, defined using HTML data on computer output devices of unknown sizes. The invention transforms the fixed canvas image to fit within a display view that of a size other than that of the display view used to construct the original image. This transformation maintains a page layout similar to that of the original but magnified or reduced to fit the available display area.

Software tools for integrated optics design

Abstract: The field of integrated optics design software tools is reviewed. Current status of main waveguide optics calculation tools is discussed. An example of design environment is described in more detail.Integrated optics design is divided into different areas: layout design, process modeling, waveguide device design and guided-wave circuit design. Typical present approach of software is emphasis on layout design and beam propagation method simulation, aimed mainly for device design, but somewhat limited in scope by the lack in addressing constructive device design viewpoint.© (1997) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Use of graphical simulation to design the layout of a robotic cell

Abstract: An approach to the layout design of a robot based flexible automation cell is described. A case study is presented for the design of a sixteen workstation laboratory automation system based around a track mounted robot, in which an exceptionally high level of operational flexibility is required. A graphical simulation model of the proposed system has been developed using AT&T Istel's "Witness" visual interactive simulation software. Visual feedback from the animated display provides process insight and aids in finding more effective workstation arrangements within the cell, reducing cycle time and allowing increased throughput and capacity. The development of the simulation model is described, including the features that allow it to be quickly reconfigured, the selection of a layout for the first iteration and the choice of appropriate evaluation criteria.

Layout design device

Abstract: PROBLEM TO BE SOLVED: To provide the layout design device which automatically perform a correcting process for arrangement wiring accompanied by logic alteration SOLUTION: The layout design device which arranges and wires circuit elements to design the layout of a logic circuit is equipped with a path delay analyzing means 104 which performs a delay analyzing process for the layout result obtained by performing the layout process of a specific logic circuit by a specific method, a repeating buffer inserting means 105 which eliminates a delay error by altering the logic of the logic circuit when there is the delay error in the layout result after the delay analyzing process, and an incremental wiring means 107 which rewrites the layout result according to the result of the logic alteration by the repeating buffer inserting means 105

Layout design method and timing verification method of semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To prepare a layout with excellent characteristic with a few kinds of cells by the both of a CMOS logic and a path transistor logic, to prepare the layout with stable characteristic in the case of the path transistor logic circuit, in particular, and to secure superiority of saving area, low power consumption and high speed operation, etc. SOLUTION: At first, an imparted logical circuit is separated into a combination circuit part and a register part in a processing 102. In a processing 104, each partial circuit with strong connectivity composing the combination circuit part separated in a processing 104 is converted into the circuit of a transistor level. Next, the layout cell of the partial circuit of the transistor level is generated in a processing 106. Subsequently, the layout cell corresponding to each register included in the register part and the layout cell for every partial circuit in the combination circuit part are defined as each unit cell, an arrangement wiring is performed in a processing 109 and the layout of a block is prepared.

New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area

Abstract: Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower poly-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.

Lsi automatic design method

Abstract: PROBLEM TO BE SOLVED: To execute the layout design of an LSI, where the area and the delay value of the LSI are optimized, in a short time. SOLUTION: After input of a net list between function macros, an outline layout processing 2 of function macros is performed based on this net list, and physical specifications of function macros are determined in accordance with this outline layout. Thereafter, a logic synthesis processing 3 is performed based on determined physical specifications, and next, the logic obtained by logic synthesis is laid out based on the outline layout of function macros. Consequently, an attention is paid to the layout from the stage of function design of a higher layer where the gate level is not settled, and re-execution of circuit synthesis or the like is considerably reduced, and thus, the layout design of the LSI where the area and the delay value of the LSI are optimized is completed in a short time.

Bonding property verification system

Abstract: PROBLEM TO BE SOLVED: To lighten the burden of a worker and also, improve the design and verification efficiency by performing the verification of the layout at the same time with the verification of bonding property, based on the verification standard data, when performing the modification and edition of the position of each pad. SOLUTION: The verification of the layout is performed at the same time with the verification of the bonding property, based on the bonding property verification standard data 10 and the layout verification standard data 13, by means of a modification pad position bonding property verification means 2, for the layout design information requiring change when having modified and edited the position of each pad by a pad position modification and edition means 1. Next, the vertification result is displayed in real time by a verification result and modified pad position indicating means 3. Then, when the bonding property verification is finished for all pad positions, the pad position, the layout design information corresponding to it and the verification result are stored by a bonding property verification information storage means 4, and they are sent to a layout design process and a layout verification process.