Showing papers on "Pass transistor logic published in 1981"

Optical logic gates using liquid crystal light valve: implementation and application example

Abstract: In this paper, we propose a new method of optically implementing digital logic gates capable of performing all logic operations and give the technique for construction of an array of n-bit parallel adders as a typical application circuit. These gates are implemented using a Hughes liquid crystal light valve operated in the parallel off-state configuration. It is found that all possible functions of two binary variables are realizable with these gates, some as bright-true-logic and some as dark-true-logic. Experimental results will be given using the portions of a single liquid crystal light valve demonstrating the feasibility of AND, NOR, XOR, etc. gate arrays. As an example of implementation of combinatorial circuits, a design for an array of binary adders will also be given.

Multiple-Valued Logic Charge-Coupled Devices

Abstract: A new method to implement multiple-valued logic in large scale integrated circuits is introduced. The data are represented by discrete amounts of charge in a charge-coupled device. In this paper the design principles and realizations in four-valued logic of a minimum and maximum circuit, a complement circuit, a literal a successor, and an adder are presented. Also, the designs of a binary-to-quaternary converter and vice versa are discussed. Charge-coupled devices offer low-power consumption, high-packing density, and the possibility to perform MOST-IC compatible multiple-valued logic in any arbitrary radix.

Programmable logic array interconnection matrix

Abstract: An interconnection matrix is disclosed for connecting inputs and outputs of logic circuit of a programmable logic array (PLA). The interconnection matrix consists of row conductors each connected to an input of a logic circuit and segments of column conductors each connected to an output of a logic circuit. By limiting the interconnection capability of each column conductor several column conductors each electrically isolated from each other can share the same column of the interconnection matrix. The resulting PLA can perform various logic functions using an interconnection matrix which does not grow geometrically with an increase in the number of logic circuits.

Feedback-controlled substrate bias generator

Abstract: A semiconductor circuit supplies a substrate back bias voltage that is feedback controlled as a function of the sum of the positive threshold voltage of one field-effect transistor (FET) and the negative threshold voltage of a second FET. Preferably, one of the FET's is an enhancement-mode device, and the other is a like-polarity depletion-mode device. This arrangement enables the bias voltage to vary from chip to chip in such a manner as to speed up the logic gates on a chip containing the slowest gates and to slow down the logic gates on a chip containing the fastest logic gates, thereby decreasing the chip-to-chip spread in gate propagation delay and average power dissipation. The worst-case noise margin increases slightly.

Symmetrical programmable logic array

Abstract: A programmable logic array is provided by symmetrically arraying drivers around the periphery of a substrate. These drivers are essentially OR/NOR gates having latched complementary outputs. The latched complementary outputs enable these logic gates to be implemented into flip-flop elements, and the complementary outputs allow these logic gates to be implemented into AND logic gates. Selectable feedback paths are also provided to add greater flexibility to the programmable logic array. Altogether, the symmetrical logic array provides a simple one-to-one representation of most logic designs to form a universal logic design board in the form of a random logic or programmable state machine.

A switch-level simulation model for integrated logic circuits

Abstract: The switch-level model describes the logical behavior of digital integrated circuits implemented in metal oxide semiconductors (MOS) technology. A network in this model consists of a set of nodes connected by transistor "switches." Many aspects of MOS circuits can be described which cannot be expressed in the Boolean logic gate model, such as bidirectional pass transistors, dynamic storage, and charge sharing. Furthermore, the logic network can be extracted directly from the mask specification of a circuit by a relatively straightforward computer program. Unlike analog circuit models, however, the nodes in a switch-level network assume discrete logic states 0, 1, and X (for unknown), and the transistors assume discrete states "open," "closed," and "unknown." This model can form the basis of a logic simulator for MOS circuits with performance comparable to logic gate simulators. This dissertation presents a rigorous development of the switch-level model and several simulation algorithms.

Devices and circuits for bipolar (V)LSI

Abstract: It is shown that bipolar circuits can continue to play an important role in high-performance LSI and VLSI circuits, because power supply voltages and logic swings can be minimized independently of dimensions, and because the speed degradation due to on-chip wiring capacitances is less severe than in MOSFET/MESFET types of circuit General performance improvements (in speed and packing density) of logic gates are obtained by increasing transistor f T , and decreasing parasitic capacitances, series resistances and device areas, by using oxide isolation, self-aligned techniques and polysilicon electrodes Fast switching diodes (such as Schottky barrier diodes and lateral polydiodes) improve the flexibility of circuit design Logic circuits (such as I2L, LS, DTL, ISL, STL, ECL, and NTL), which already perform in LSI and VLSI circuits or are realistic proposals for them, are discussed

Field effect current mode logic gate

Abstract: Disclosed is a field effect current mode logic gate comprised of a current source for supplying a constant current, and a differential amplifier having first and second branches for passing respective portions of the constant current. The first branch includes a plurality of parallel-coupled or serially-coupled enhancement field effect transistors having a positive threshold voltage and having respective gates for receiving respective input logic signals; and the second branch includes a depletion field effect transistor having a negative threshold voltage, and a grounded gate. The magnitudes of the current portions in the first and second branches are representative of the magnitude of the input logic signals relative to the positive threshold voltage plus the absolute value of the negative threshold voltage.

A 1.5 V single-supply one-transistor CMOS EEPROM

Abstract: Describes a 1.5 V single-supply one-transistor p-channel CMOS EEPROM array which is fabricated with a double polysilicon gate 7-mask CMOS technology. Avalanche injection and Fowler-Nordheim emission are used as very low power programming mechanisms. A thin oxide of 28 nm allows write and erase voltages below -30 V. They are generated on-chip by voltage multipliers and fed by 1.5 V logic circuitry to the matrix array. Results measured on a 16/spl times/4 bit word-erasable test array are presented.

Unitary exclusive or-and logic circuit

Abstract: A unitary logic circuit for performing the function of an EXCLUSIVE OR logic gate, the output terminal of which forms a first input terminal to an AND logic gate. Implemented in emitter-coupled logic technology, the circuit has a fast response time with low power consumption.

Gigabit Logic Circuits with Scaled nMOS

Abstract: Logic circuits made with a new scaled n-channel MOSFET technology have been clocked at gigabit rates. This new nMOS technology employs X-ray lithography and reactive ion etching to obtain 1 ?m features and submicron channel lengths. Two ring oscillator designs are presentea: (1) circuits witra propagation aelays of 30 ps and power-delay products of 44 fJ and (2) circuits with power-delay proaucts of 5 fJ that have propagation delays of 75 ps. A practical logic circuit, a four-stage frequency divider or counter, is aescribed that has been operated at clock frequencies up to 2.5 GHz.

Majority logic gate

Abstract: A majority logic gate is comprised of a plurality of depletion mode switching devices and includes Schottky diodes for both level shifting and clamping the high logic level output voltage to ground. A plurality of MESFET input devices each have their gate electrode coupled to one input of the majority logic gate. Each MESFET input device has a source coupled to ground and a drain coupled to a current load device. The voltage level at the drain at each of the input devices changes from a logical "0" to a logical "1" state depending upon the number of inputs which are at a logical "1" level. The drain voltage is then level shifted down. The high logic level output voltage is clamped to ground by means of two Schottky diodes the first of which has a cathode coupled to ground and an anode coupled to the anode of the second diode, the cathode of the second diode being coupled to the output of the circuit.

Method of testing a logic system and a logic system for putting the method into practice

Abstract: A method for testing a logic system of the type having points not directly accessible from the exterior, and logic systems including means for carrying out the method. A particular logic state may for test purposes be applied (set) at a particular, normally-inaccessible point in the system; or the logic state at a particular, normally-inaccessible point in the system may be sampled. To accomplish these functions, there are a plurality of flip-flops and associated selective gating circuitry, for example AND-OR select gates, arranged selectively either to connect the flip-flops in series to form a shift register configuration whereby data defining particular logic states to be set, or particular logic states which have been sampled, may be clocked in or clocked out by accessing only the input of the first flip-flop or the output of the last flip-flop; or to connect the inputs and outputs of the various flip-flops to particular points in the system for the purposes of setting and sampling logic states. The logic system may, for example, be either a single integrated circuit chip, or a circuit module having a limited number of external connections.

High-entrance high-speed logic operator which has a complex digital function and utilizes at least one quasi-normally off MESFET

Abstract: In the field of large-scale-integrated digital GaAs circuits, a high-entrance high-speed logical operator utilizing so-called "quasi-normally-off" Schottky-gate field-effect transistors (MESFETS) having a low threshold voltage. By means of a single very-high-speed logic gate, the operator thus performs AND - NAND - OR functions by utilizing in an input branch a saturable resistive load in series with a pair of quasi-normally-off MESFET's each having a maximum of two Schottky gates, the drains of the transistors being connected to an output transistor of the same type. Two identical portions of circuit are mounted in parallel with an output half-branch comprising a diode in series with another saturable resistive load.

A Logic Design Theory for VLSI

Abstract: Classical switching theory fails to account for some key structural and logical properties of the transistor circuits used in VLSI design. This paper proposes a new logic design methodology called CSA theory which is suitable for VLSI. Three kinds of primitive logic devices are defined: connectors (C), switches (S), and attenuators (A); the latter have the characteristics of pullup/pulldown components. It is shown that four new logic values are required, in addition to the usual Boolean 0 and 1 values. These values introduce a concept of gain or drive capability into logic design; they also account for the high-impedance state of tri-state devices. The elements of CSA theory and its application to some basic VLSI design problems are described. It is demonstrated that CSA theory provides a more powerful and more rigorous replacement for the mixed logic/electronic methods currently used in VLSI design.

Accurate logic simulation models for TTL totempole and MOS gates and tristate devices

Abstract: The two logic values, 0, 1, and the unknown, are not sufficient for accurately simulating the behavior of TTL totempole and MOS gates and tristate devices. Furthermore, the classical fault modes (output stuck and input open) are not sufficient to cover the faulty behavior of MOS devices. A previous solution to the simulation modeling required the addition of pseudo gates, which have no physical meaning. This paper develops methods of modeling fault-free and faulty tristate devices for logic simulation. The model does not require any additional circuitry, but the existence of a simulator capable of simulating any number of logic values is assumed.

The interdependence of geometrical, thermal, and electrical limitations for VLSI logic

Abstract: With the trend towards further minimization, VLSI chips containing random logic will approach various fundamental limits. The interdependency of geometrical, thermal, and electrical effects is discussed, showing that a 1 cm/SUP 2/ chip is about equally limited by these three effects.

Noninverting amplifier circuit for one propagation delay complex logic gates

Abstract: A noninverting amplifier circuit for one propagation delay complex logic gates. The noninverting amplifier circuit is compatible with field effect transistor logic, including depletion-mode Schottky barrier field effect transistor (MESFET) inverting logic, gates. The basic noninverting amplifier circuit, utilizes field effect transistors (FET) and diodes, and comprises input interface means for receiving an input voltage signal, amplifier means for providing noninverted amplification of the input voltage signal, and buffer means for driving, and shifting the voltage level of the amplified input voltage signal. In another embodiment, additional circuit means for enabling performance of the "AND" logic function is included in the basic noninverting amplifier circuit. In a third embodiment, additional circuit means for enabling performance of the "OR" logic function is included in the basic noninverting amplifier circuit. The input and output voltages of the various embodiments which utilize the noninverting amplifier logic circuit are compatible with those of inverting logic circuits. Some examples of higher level complex one propagation delay logic gates which utilize the circuit in combination with inverting logic circuitry are also illustrated.

A MOS/LSI Oriented Logic Simulator

Abstract: A logic simulator capable of efficiently modelling complex MOS/LSI circuits is presented. The circuit is simulated at the combinational logic and transmission gate level using a set of six node-states. Gate models have inertial delay and assignable nominal rise and fall delays. Both unidirectional and bidirectional transmission gates are accurately simulated, and functional models are provided for ROM, RAM, etc.

A bipolar 2500-gate subnanosecond masterslice LSI

Abstract: A bipolar 2500-gate subnanosecond masterslice LSI has been developed for use in computer mainframes. A walled-emitter structure has been realized by using double boron ion implantation with an n-type epitaxial layer to obtain high performance and high packing density. A new cell composed of a pair of adjacent gates provides high utilization of input transistors. A gate delay of 0.58 ns with power dissipation of 0.54 mW/gate has been achieved. The masterslice has been applied to an 18-bit memory data register circuit consisting of 1983 internal logic gates and has been mounted on a new 224-pin plug-in package.

A MOS Modelling Technique for 4-State True-Value Hierarchical Logic Simulation or Karnough Knowledge

Abstract: Modelling strategies and techniques are given for static and dynamic MOS transistors in a 4--state (0/low, 1/high, Z/high-impedance, U/undefined) logic simulator environment. General MOS modelling problems are presented and a set of workable solutions are developed. Experience with these techniques is shown along with examples of NMOS simulation applications. This paper discusses a technique with specific conventions for modelling MOS devices at the "logical transistor" gate level. The technique is not the optimal general solution, but was found to be satisfactory for retrofitting an existing 4--state logic simulator to include MOS capabilities. The technique is not meant to replace analog circuit simulation, but is aimed at increasing the accuracy of MOS logic (gate level) simulations. We begin with a general bus model and extend it to handle transistors, pullups and pulldowns, and dynamic MOS transfer gates. Extensions are shown for a bidirectional transfer gate model that can be connected in any topological configuration.

Voltage regulator for direct current power supply

Abstract: A power supply (17) having a regulator featuring a series pass transistor (150) connected as a common collector amplifier is shown. The power supply is turned on and off by switching devices (11, 151, 160, 159) which control base current only to a transistor switch (155, 170) operating analog circuitry (157) which controls the pass transistor. Microcomputer control (181) of the power supply and self latching embodiments are also shown. The power supply shown herein can successfully regulate output voltages which differ from the raw DC input by no more than the saturation voltages of series pass transistor.

Fail soft tri-state logic circuit

Abstract: A tri-state logic circuit which, upon failure of its operating potential, produces a high impedance between its output terminals. The tri-state logic circuit includes first and second complementary conductivity type transistors each with a control electrode and with a conduction path. The paths are connected in series to the operating potential. The control electrode of the first transistor is connected to an intermediate point in a series switching circuit the ends of which are connected to the operating potential. The series circuit is responsive to the presence of the operating potential and to binary data and control signal inputs of given values for causing the conduction path of the first transistor to assume a low impedance state. The series circuit also includes on both sides of said intermediate point devices responsive to a loss in the operating potential for causing the first transistor to assume a high impedance state irrespective of the value of the data and control signals.

Fast logic operator with high fan-in and complex logic function, using at least two low-threshold field effect transistors

Abstract: The invention relates to the realization in integrated circuit, fast logical operators, using field-effect transistors with low threshold voltage, so-called "quasi-normally-off", to ensure a large entrance with logic functions more or less complex. The operator thus produced fills with one very fast logic gate, the functions "ET- OR NOT - OR", using an input branch in a saturable resistive load (CS Applying to the logic transistors effetde field on gallium arsenide.

Logic inverter, and a multi-output logic operator derived from this inverter, using at least two low-voltage-threshold field-effect transistors

Abstract: A high-speed logic inverter, in the form of an integrated circuit, with a single supply source, using field-effect transistors of the "quasi-normally-off" type, and the logic operators having several inputs and several outputs which derive therefrom. One embodiment of the invention starts from an inverter with input, through a diode, on a field-effect transistor gate, and with its output at the source of a field-effect transistor. This basic diagram is added to by providing the input (between supply pole and input terminal) with two pairs of diodes ending at the gates of a dual-gate transistor, and by providing independent outputs obtained by connecting the common drain connected transistor gates to the supply pole distinct from ground.

Integrated high-voltage/Low-voltage MOS devices

Abstract: A new high voltage device structure and a corresponding fabrication process have been developed. The device has a planar, integrable, closed geometry structure that utilizes a highly resistive polysilicon field relief electrode (field plate) to control device breakdown voltage and transconductance. The active device area is totally covered by polysilicon or metal, contributing to long term stability and reliability. The closed geometry structure is self-isolating and thus multiple high voltage devices and low voltage NMOS logic can be integrated on the same chip. Operation in excess of 500 Volts has been demonstrated and an array of 16 such devices driven by low voltage logic has been designed, fabricated, and tested, Principal applications for this technology are displays and electrographic printing.

Means for enhancing logic circuit performance

Abstract: Disclosed is a means for enhancing logic circuit performance and more particularly, for enhancing the switching speeds of a variety of logic circuits. What is involved is the insertion of a so called "snap" or enhancement transistor connected to a common node defining an output of a basic logic circuit. In one example, the emitter of this "snap" transistor is connected to an output node in the circuit, which in conventional practice would be charged during an upgoing transition by a fixed RC time constant. In accordance with the present improvement, however, the "snap" transistor, due to charge stored therein, remains conducting--although the associated logic device is turned off. This current discharges as reverse base current and the output provides what appears to be an inductive voltage spike. The effect is that a temporary source of current is available to charge the common node. As a result, the transition time involved in going from one voltage level to another at the output node is substantially reduced.

TTL Output circuit having means for preventing output voltage excursions induced by negative current reflections

Abstract: A transistor-transistor logic circuit includes an output stage comprising a pull-up and pull-down transistor and an input stage for receiving one or more binary logic signals. First and second current drive transistors regulate base drive to the pull-up and pull-down transistors respectively. A first switching transistor turns said first current drive transistor off when the binary signals reach a first logic level. A second switching transistor turns the second current drive transistor on when the binary logic signals reach the first logic level. In this manner, negative reflections at the output of the circuit will not result in the pull-up transistor and its associated current drive transistor being turned off.

Logic safety system

Abstract: A logic safety system is disclosed having four redundant channels with each channel constituted by a logic circuit for controlling the triggering of a protective action, a logic alarm circuit connected to the control circuit and a logic inhibition circuit which makes it impossible to simultaneously inhibit several alarm circuits. Any attempt at inhibiting the alarm circuit of a second channel while an alarm circuit of a first channel is already inhibited will result in the automatic appearance of a protective action control signal at the output of the second channel regardless of the signal received at the input of the alarm circuit of the second channel.

High speed write control for synchronous registers

Abstract: An electronic circuit for regulating the entry of new data into a static synchronous register comprising a bank of D type, master-slave flip-flops. The circuit selectively passes the first phase of a two-phase, nonoverlapping clock signal used for synchronization and control of the data. A bootstrap operated, series pass, transistor configuration couples the first phase signal to the electrode actuating the master stage of each flip-flop. With provisions for the series pass transistor to transition into a conductive state prior to the onset of the first phase signal, the circuit ensures substantial replication of the first phase signal characteristics in terms of both time and amplitude.