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Showing papers on "Pixel published in 1980"


Journal ArticleDOI
TL;DR: Experimental results show that in most cases the techniques developed in this paper are readily adaptable to real-time image processing.
Abstract: Computational techniques involving contrast enhancement and noise filtering on two-dimensional image arrays are developed based on their local mean and variance. These algorithms are nonrecursive and do not require the use of any kind of transform. They share the same characteristics in that each pixel is processed independently. Consequently, this approach has an obvious advantage when used in real-time digital image processing applications and where a parallel processor can be used. For both the additive and multiplicative cases, the a priori mean and variance of each pixel is derived from its local mean and variance. Then, the minimum mean-square error estimator in its simplest form is applied to obtain the noise filtering algorithms. For multiplicative noise a statistical optimal linear approximation is made. Experimental results show that such an assumption yields a very effective filtering algorithm. Examples on images containing 256 × 256 pixels are given. Results show that in most cases the techniques developed in this paper are readily adaptable to real-time image processing.

2,701 citations


Journal ArticleDOI
Turner Whitted1
TL;DR: Consideration of all of these factors allows the shader to accurately simulate true reflection, shadows, and refraction, as well as the effects simulated by conventional shaders.
Abstract: To accurately render a two-dimensional image of a three-dimensional scene, global illumination information that affects the intensity of each pixel of the image must be known at the time the intensity is calculated. In a simplified form, this information is stored in a tree of “rays” extending from the viewer to the first surface encountered and from there to other surfaces and to the light sources. A visible surface algorithm creates this tree for each pixel of the display and passes it to the shader. The shader then traverses the tree to determine the intensity of the light received by the viewer. Consideration of all of these factors allows the shader to accurately simulate true reflection, shadows, and refraction, as well as the effects simulated by conventional shaders. Anti-aliasing is included as an integral part of the visibility calculations. Surfaces displayed include curved as well as polygonal surfaces.

1,559 citations


Journal ArticleDOI
TL;DR: In this article, a set of color features, (R + G + B) 3, R − B, and (2G − R− B) 2, were derived by systematic experiments of region segmentation.

965 citations


Proceedings ArticleDOI
Kenneth I. Laws1
23 Dec 1980
TL;DR: In this article, the texture energy approach requires only a few convolutions with small (typically 5x5) integer coefficient masks, followed by a moving-window absolute average operation.
Abstract: A method is presented for classifying each pixel of a textured image, and thus for segmenting the scene. The "texture energy" approach requires only a few convolutions with small (typically 5x5) integer coefficient masks, followed by a moving-window absolute average operation. Normalization by the local mean and standard deviation eliminates the need for histogram equalization. Rotation-invariance can also be achieved by using averages of the texture energy features. The convolution masks are separable, and can be implemented with 1-dimensional (vertical and horizontal) or multipass 3x3 convolutions. Special techniques permit rapid processing on general-purpose digital computers.

635 citations


Journal ArticleDOI
TL;DR: In this article, the authors introduce a characterization of skeletal pixels in terms of how many arcs of the boundary pass through a pixel and a new algorithm is proposed which proceeds by peeling off successive contours of the set to be thinned while identifying pixels where disjoint parts of boundary have been mapped.

238 citations


Journal ArticleDOI
Robert M. Haralick1
TL;DR: In this article, a unified view of edge and region analysis is provided based on the sloped-facet model which assumes that regions of image segments are maximal areas which are sloped planes.

201 citations


Journal ArticleDOI
TL;DR: An algorithm is presented for constructing a quadtree from the array representation of a binary image that examines each pixel in the image once and only once, and never requires temporary nodes.

119 citations


Patent
12 May 1980
TL;DR: In this article, a set of overlay images are established within a stack of memory maps for superpositioning over a host image on a raster display, which are primarily empty background with few actual image pixels.
Abstract: A set of overlay images are established within a stack of memory maps for superpositioning over a host image on a raster display. The overlay images include legends, grids, cursors, graphs, formats, etc. which are primarily empty background with few actual image pixels. Overlay conflict between corresponding image pixels from different images is resolved by priority logic in accordance with the order of the image planes within the stack. The background pixels maintain a video switch in the host mode for continuing the flow of host data. The absence of background pixels in any plane (that is the presence of overlay image pixels in any plane) keys the video switch to the insert mode for substituting the overlay pixels for corresponding pixels of host data. The resulting composite data stream is decoded and presented to a D/A for display on a CRT. One overlay code is dedicated to background pixels in the overlay memory map, for indicating the absence of overlay pixels to control the status of the video switch. The background code is not decoded and therefore does not pass through the D/As to produce a visible display characteristic. The corresponding code in the host data may therefore represent a visible characteristic unique to the host image, such as keying a window within the host display to incorporate a secondary host image.

99 citations


Journal ArticleDOI
TL;DR: In experiments using a color image of a house, the relaxation approach gave markedly superior performance; relaxation eliminated 4-8 times as many errors as the other methods did.
Abstract: Three approaches to reducing errors in multispectral pixel classification were compared: 1) postprocessing (iterated reclassification based on comparison with the neighbors' classes); 2) preprocessing (iterated smoothing, by averaging with selected neighbors, prior to classification); and 3) relaxation (probabilistic classification followed by iterative probability adjustment). In experiments using a color image of a house, the relaxation approach gave markedly superior performance; relaxation eliminated 4-8 times as many errors as the other methods did.

86 citations


Patent
06 Mar 1980
TL;DR: In this paper, a reader system for optically scanning a bar code and processing the resulting video signals to produce corresponding digital signals is disclosed, which comprises a camera having an image sensor which converts the varying black and white bar code image into a corresponding analog video signal.
Abstract: A reader system for optically scanning a bar code and processing the resulting video signals to produce corresponding digital signals is disclosed. The scanner comprises a camera having an image sensor which converts the varying black and white bar code image into a corresponding analog video signal. This signal is fed to a dynamic threshold detector which tracks the midpoint voltage value of the video signal and applies this value to a comparator, where it is compared to the analog video signal. The output of the comparator provides a train of logic states "0" and "1" representing video levels below and above the midpoint voltage value, respectively, thus producing a digitalized video signal corresponding to the bar code. The digital signals are filtered to mask single bit aberrations, with the filter producing a series of logic "0"'s and "1"'s at the clock rate of the system, each of which represents the output of a single "pixel", or picture element, of the image sensor, the output level indicating whether the pixel has sensed a black or white bar. The number of consecutive pixels having "0" or "1" output levels are counted and compared to preset values to determine whether wide or narrow code bars are being sensed, and this information is stored in digital form in one of two serial memories. At the same time, the total number of bars scanned is counted, and the memory is inhibited when the count equals the number of bars in the code. At the completion of a first scan of the bar code image, the storage of informatiion is switched to the other serial memory and the bar code scanning process is repeated while the data just stored in the first memory is processed, for example, in a conventional bar code-to-numeric or alpha-numeric converter for display. Multiple scans of the bar code insure an accurate readout.

71 citations


Patent
15 Aug 1980
TL;DR: In this article, a system for analyzing images represented by a serial stream of digital electrical signals corresponding to values of pixels in a matrix of points constituting an image is presented, which includes a pipeline of substantially identical neighborhood transformation stages.
Abstract: A system for analyzing images represented by a serial stream of digital electrical signals corresponding to values of pixels in a matrix of points constituting an image. The system includes a pipeline of substantially identical neighborhood transformation stages. Each stage includes a processor portion for analyzing the pixel values and a memory portion communicating with the processor portion for sequentially providing a window of neighboring pixels to the processor for analysis. A central programmable controller communicates with the pipeline over a single communication link which provides both the pixel value data to the pipeline and transformation control instructions to the processor portions of each stage. The memory portion preferably includes a random access memory which serves as a line storage device which may be readily adjusted to accommodate different raster scan line lengths from various image sensors. Each stage includes improved logic circuitry capable of performing a wide variety of analyses on both two-dimensional image data represented by binary pixel values and three-dimensional image data represented by multi-valued pixel values. Image border or off-image detection circuitry is also disclosed which is capable of detecting nonlinear boundaries for the image matrix.

Proceedings ArticleDOI
01 Jul 1980
TL;DR: A new algorithm is presented for continuous rotation and zoom, free from the disturbing aliasing artifacts introduced by traditional methods, based on a digitized code for lines on rasters generalized to an interpolation scheme capable of executing all linear geometric transformations.
Abstract: Raster graphics images are difficult to smoothly rotate and zoom because of geometric digitization error. A new algorithm is presented for continuous rotation and zoom, free from the disturbing aliasing artifacts introduced by traditional methods. Applications include smooth animation. No matrix multiplication of pixel coordinates is executed. Instead row and column parallel operations which resemble local digital filters are used. This suggests real time implementation with simple hardware. Anti-aliasing is inherent in the algorithm which operates solely on pixel data, not the underlying geometric structures whose images the pixels may depict. Zoom magnification is achieved without replicating pixels and is easily attained for any rational scale factor including but not restricted to the integer values which most existing commercial raster graphics systems use.The algorithm is based on a digitized code for lines on rasters, generalized to an interpolation scheme capable of executing all linear geometric transformations. Samples of images which have been rotated and zoomed by a software implementation of the algorithm are presented.

Patent
Koichi Ejiri1
19 Nov 1980
TL;DR: In this paper, a process of geometrically deforming an original picture by changing the picture element pitches, weight coefficients g calculated for the picture elements according to preselected magnification variation factors were read out of a first memory whenever original picture data F are read successively, the contents Fg of a second memory are read out according to addresses defined by the data g and F, and the addition result of the data Fg is divided by the added result of data g, thereby to obtain a geometrical deformed picture from the original picture.
Abstract: In a process of geometrically deforming an original picture by changing the picture element pitches, weight coefficients g calculated for the picture elements according to preselected magnification variation factors are read out of a first memory whenever original picture data F are read successively, the contents Fg of a second memory are read out according to addresses defined by the data g and F, and the addition result of the data Fg is divided by the addition result of the data g, thereby to obtain a geometrically deformed picture from the original picture.

Patent
22 Sep 1980
TL;DR: In this paper, a real-time image enhancement system was proposed, where the video image from each video frame of M 1 columns and M 2 rows of video pixels is multiplexed serially by row, each image pixel corresponding to an address in said video frame; image enhancement processing is performed in real time, using r programmable processors operating on successive kernels comprising L 1 rows and L 2 columns of the image pixels.
Abstract: A very high speed video imaging system wherein the video image from each video frame of M 1 columns and M 2 rows of video pixels is multiplexed serially by row, each image pixel corresponding to an address in said video frame; image enhancement processing is performed in real time, using r programmable processors operating on successive kernels comprising L 1 rows and L 2 columns of the image pixels. Real time image processing is made possible by multiple image copying means which furnishes multiple copies of the image pixels to the r processors, wherein each one of the processors receives a copy of only those image pixels having an address lying within an assigned range, which limits the amount of data handled by each processor for each video frame. The use of multiple image copies permits each processor to process pixels at an average rate which is reduced from the video data rate by a factor proportional to 1/r, thus permitting programmable processing to occur in real time despite the relatively slow speed of the processors and the high video data rate. The invention thus eliminates time sharing or arbitration among the plurality of processors.

Patent
26 Jun 1980
TL;DR: In this paper, the color subcarrier cycle pixel groups are recorded on separate tracks with those to be replayed during the Moviola mode on a single track so that Moviola pixel groups on the single track can be repeated in sequence when reconstructing the color Moviola picture and thereby supply instantaneously coherent information.
Abstract: Moviola color picture quality is improved for a record and replay system wherein video sampled at a predetermined multiple of the color subcarrier frequency is recorded with each frame or field being disposed on a set of multiple tracks and with only a portion of the recorded information being intended for replay to reconstruct the color Moviola signal. Only pixel groups relating to entire color subcarrier cycles are recorded on the tracks so that a video signal having proper color information can be readily reconstructed therefrom during the Moviola mode. In one preferred embodiment, sequential color subcarrier cycle pixel groups are recorded on separate tracks with those to be replayed during the Moviola mode on a single track so that Moviola pixel groups on the single track can be repeated in sequence when reconstructing the Moviola picture and thereby supply instantaneously coherent information.

Patent
Remo J. D'Ortenzio1
04 Aug 1980
TL;DR: A separable two dimensional Finite Impulse Response (FIR) digital image processing filter with X-dimension filter section having a delay buffer series to which digitized image signals or pixels are first input.
Abstract: A separable two dimensional Finite Impulse Response (FIR) digital image processing filter with X-dimension filter section having a delay buffer series to which digitized image signals or pixels are first input. The buffer inputs and output are tapped and pixels tapped off are processed by preset multiplier factors and input to an adder where the processed pixels are summed. The summed pixels are fed to a line buffer series of a Y-dimension filter section, tapped off from the filter inputs and output, and processed by further preset multiplier factors. The processed pixels are input to a second adder and summed to provide filtered output pixels. In a second embodiment, the filter is symmetric and has a center point response of unity. In a third embodiment, the filter X and Y dimension filter sections are reversed.

Patent
12 Nov 1980
TL;DR: In this article, the first page for the first pixel of each incoming ray is determined by logic which subtracts the ray or column number from eight, modulo 8. Subsequent pages are generated by incrementing repetitively within the range 0, 1, 2... for each subsequent incoming pixel, after being set to said first page number.
Abstract: Imaging information characterizable as a pixel grid or matrix of 256 image columns and 512 image rows is supplied by a scanning transducer means delivering a series of ray lines of information where each ray corresponds to an image column. The incoming pixels of the rays are converted into digitized data words, and stored for scan conversion by being routed, in simultaneous blocks of eight words, to a respective one of eight different page memories, in accordance with an image memory organization scheme assigning a different page routing number to each pixel of a block for the entire image matrix, to enable parallel memory access for both input and output operations. The first page for the first pixel of each incoming ray is determined by logic which subtracts the ray or column number from eight, modulo 8. Subsequent pages are generated by incrementing repetitively within the range 0, 1, 2 . . . for each subsequent incoming pixel, after being set to said first page number. Each page is associated with a corresponding element of an input buffer, to receive the corresponding pixel for each incoming column block. All elements of the full buffer are dumped in parallel to the eight page memories simultaneously. This occurs repetitively for all blocks of each ray/column until each pixel of a frame is stored at an individually separate page address determined by simple arithmetical logic. For output, the page memories are read out in rows, in simultaneous parallel row blocks of eight, one block element from each page, to an output buffer having an element connected to each page, with the page address for each pixel of a row block determined by a simple arithmetical operation. The output buffer elements are fed serially to a video display subsystem in an order determined by the page routing numbers of the rows of the image memory organization scheme. Simple circuitry determines the order of buffer element readout, with the first page/buffer element number being simply the number of the image row being read out, (Modulo 8), and subsequent page/buffer element numbers of that row being generated incrementing repetitively within the range 0, 7, 6 . . . 1, after being set to said row first page number. Such readout in successive rows of course effects conversion to a conventional video format for display.

Journal ArticleDOI
TL;DR: In segmenting an image by pixel classification, the sequence of gray levels of the pixel's neighbors can be used as a feature vector that yields classifications at least as good as those obtained using other local properties as features.

Patent
Patricia P. Wiener1
25 Aug 1980
TL;DR: In this paper, a bit structuring apparatus with a font memory for storing alpha-numeric characters and tonal definitions in a window representing a pixel space is presented, which includes a programmable divide-by-N counter selectively operable to reduce the frequency of the pixel stream and expand the characters along the X-axis.
Abstract: A bit structuring apparatus having a font memory for storing alpha-numeric characters and/or tonal definitions in a window representing a pixel space. The alpha-numeric characters thus stored can include both the character and required character spacing. The font memory is addressable by coded address data to output a stream of pixels representative of the characters selected. The apparatus includes a programmable divide-by-N counter selectively operable to reduce the frequency of the pixel stream and expand the characters along the X-axis, line buffers for buffering the pixels pending discharge to a remote output, a return bus for re-circulating pixels in the line buffers, a multiplexer for selectively coupling individual line buffer outputs to the remote output and a programmable counter for controlling the number of times each line buffer discharges pixels to the remote output, each additional discharge expanding the characters along the Y-axis. Additionally, data from other sources, i.e. computer, CRT, facsimile, scanner, memory, etc., representing a fixed definition may be received independently, both for storage and manipulation. The apparatus can, by programming or switching, alter size and effectively expand or reduce the data on a line by line basis in the same manner as alpha-numeric data from the font memory.

Proceedings ArticleDOI
01 Jul 1980
TL;DR: A frame buffer architecture is presented that reduces the overhead of frame buffer updating by three means: the bit-map memory is (x,y) addressable, whereby a string of pixels can be accessed in parallel, and multiple objects in the frame buffer are addressable simultaneously by a set of address registers.
Abstract: A frame buffer architecture is presented that reduces the overhead of frame buffer updating by three means. First, the bit-map memory is (x,y) addressable, whereby a string of pixels can be accessed in parallel. Second, the pixel-change operation is performed by hardware in a single read-modify-write cycle. Third, multiple objects in the frame buffer are addressable simultaneously by a set of address registers. The remaining task of generating (x,y) addresses and providing new data can be managed rapidly by current microprocessors or DMA-devices.With a modest expenditure of hardware, this architecture eliminates all the bit-shifting, bit-masking, and bit-manipulation conventionally associated with frame buffer graphics, while retaining the full generality of user-programmable control. The particular implementation described allows raster manipulation at full bit-map memory bandwidth. It can paint a 16×16 pixel character into the frame buffer in 16 microseconds and can modify a 1024×1024 pixel raster in 64 milliseconds.

Patent
15 Aug 1980
TL;DR: In this paper, a system for analyzing images represented by a plurality of raster scan lines of pixel values employs at least one neighborhood transformation stage, which includes a processor portion for analyzing windows of neighboring pixel values and providing a transformation output as a function of the pixel values contained in the window.
Abstract: A system for analyzing images represented by a plurality of raster scan lines of pixel values employs at least one neighborhood transformation stage. The stage includes a processor portion for analyzing windows of neighboring pixel values and providing a transformation output as a function of the pixel values contained in the window. A random access memory (RAM) repetitively stores a given plurality of successive pixel scan lines fed to the stage. Selected pixel values from the RAM are loaded into the processor portion so as to sequentially access the neighborhood windows for analysis. The RAM serves as a recirculating line storage device for accommodating different raster scan line lengths.

Patent
14 Jul 1980
TL;DR: In this article, a digital TV system reduces the data rate by transmitting or recording only bytes representing half of the sampled pixels, and steering bits are also transmitted that tell which of the transmitted bytes are the closest match to the untransmitted bytes so the pixels represented by the later can be reconstructed.
Abstract: A digital TV system reduces the data rate by transmitting or recording only bytes representing half of the sampled pixels. Steering bits are also transmitted that tell which of the transmitted bytes are the closest match to the untransmitted bytes so the pixels represented by the later can be reconstructed.

Proceedings ArticleDOI
01 Jan 1980
TL;DR: In this article, the authors present the results of an extensive series of laboratory tests aimed at exploring the accuracy limits of the star image center-finding technique and conclude that tracking accuracy better than 1/50 pixel can be achieved.
Abstract: Star trackers based on the use of charge-coupled device (CCD) imaging arrays have demonstrated substantial performance gains relative to more conventional designs. For many space applications, the most important gain is the accuracy improvement associated with a stable, precisely known, CCD geometry. This inherent accuracy can be fully exploited using star image centerfinding techniques to measure the image location to a small fraction of a CCD picture element. In this paper we present the results of an extensive series of laboratory tests aimed at exploring the accuracy limits of this technique. Simulated star images were moved over the CCD, permitting measurement of tracking errors as small as 1/1000 pixel. After tests on both frontside and backside illuminated (thinned) CCDs, we conclude that tracking accuracy better than 1/50 pixel can be achieved.© (1980) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Proceedings ArticleDOI
01 Jan 1980
TL;DR: Star trackers employing several novel techniques for maximizing the efficiency with which information can be extracted as well as corrected for electronic and opto/ mechanical distortions are described.
Abstract: Recent star tracker developments at JPL which utilize microprocessor-controlled large area imaging CCD arrays have included several novel techniques for maximizing the efficiency with which information can be extracted as well as corrected for electronic and opto/ mechanical distortions. Scanning algorithms which maximize the rate of obtaining target information, coupled with autonomous control of CCD and signal chain parameters, result from efficient task allocations between electronic hardware elements and operating software. Trade-offs between optical system and image processing software complexity allow sub-pixel star and image tracking using badly aberrated point spread functions by means of power series correction equations which define ideal image centroids from the aberrated image centroids. Star trackers employing these techniques currently under development at JPL are described.

Journal ArticleDOI
TL;DR: In this article, local operators are used to detect linear features in Landsat data for an area where such features are typically less than 1 pixel in width, and two postprocessing techniques are described which reduce this noise by utilizing contextual information in the data.
Abstract: Local operators are used to detect linear features in Landsat data for an area where such features are typically less than 1 pixel in width. A modification to existing techniques is made which gives improved results. The choice of threshold for the detector algorithm is investigated by considering line and background intensity, linewidths, and line alignment with respect to the pixel boundaries and spatial autocorrelation in the data set. It is found that results will always contain a significant amount of noise. Two postprocessing techniques are described which reduce this noise by utilizing contextual information in the data.

Journal ArticleDOI
TL;DR: This paper describes a high resolution scanning transmission electron microscope data collection, storage, and display system included are a novel analog‐to‐digital converter, a digital hardware divider, a direct memory access interface to a PDP 11/20, a flicker‐free gray scale TV display, two new gray scale hardcopy devices, and a software description of the system.
Abstract: This paper describes a high resolution scanning transmission electron microscope data collection, storage, and display system. Included are a novel analog‐to‐digital converter, a digital hardware divider, a direct memory access interface to a PDP 11/20, a flicker‐free gray scale TV display, two new gray scale hardcopy devices, and a software description of the system. The system described here accepts three 8‐bit channels of image data from a single picture element every 30 μs. Each picture element intensity is measured simultaneously by three detectors. Scans of 64, 128, 256, or 512 lines of picture elements are provided. All the data are stored on one of eight disk files, and one of the three simultaneous data channels is displayed on a digitally refreshed TV screen in real time. Production of hard‐copy images and magnetic tape images, and other manipulations of the data are provided after data accumulation is terminated.

Patent
Peter A. Crean1, Martin A. Agulnek1
07 Mar 1980
TL;DR: In this paper, a binary rate multiplier was used for image size control along the X-axis, the multiplier being programmed to the size image desired to vary the frequency of the pixel clock signals output by the multiplier, together with a control flip-flop astride the image pixel stream and driven by multiplier clock signals to speed up or reduce the rate at which image pixels are output.
Abstract: A control system for controlling the size of the image produced by pixels generated by a raster scanner employing a binary rate multiplier for image size control along the X-axis, the multiplier being programmed to the size image desired to vary the frequency of the pixel clock signals output by the multiplier, together with a control flip-flop astride the image pixel stream and driven by the multiplier clock signals to speed up or reduce the rate at which image pixels are output. For image size control along the Y-axis, a phase lock loop is provided for controlling scanning carriage speed in response to the frequency of the signals output by a programmable frequency generator.

Journal ArticleDOI
TL;DR: Source encoding for digital image transmission is revisited with an energy distribution approach in the perceptual domain and the cosine transform is utilized on a partitioned image, suggesting a more rapid hardware implementation.
Abstract: Source encoding for digital image transmission is revisited with an energy distribution approach in the perceptual domain. Past investigations have utilized power spectral density in conjunction with the Frei eye model and full image Fourier transform coding. In this investigation, the cosine transform is utilized on a partitioned image. A cosine energy function is defined and weighted by the eye model. This results in a circular symmetric form of a bit map which simplifies source coding. This approach outperforms a standard bit allocation procedure allowing graceful degradation at 1, .75, and .5 bits/pixel. Analysis includes the perceptual mean square error and peak signal-to-noise ratio as metrics of performance. This procedure suggests a more rapid hardware implementation.

Patent
Gary L. Engle1
03 Nov 1980
TL;DR: In this paper, the pixel data stored in a display memory of an ultrasonic scanning system is updated in response to new pixel data generated from a reflected ultrasonic wave and stored pixel data.
Abstract: Pixel data stored in a display memory of an ultrasonic scanning system is updated in response to new pixel data generated from a reflected ultrasonic wave and stored pixel data. A lookup table of pixel values is provided in a second memory, and the second memory is addressed using the new pixel data and the stored pixel data. The value stored in the second memory at the address is then used to update the display memory.

Journal ArticleDOI
TL;DR: Experimental results indicate that the CCD imager can be used to combine real-time analog image processing with subsequent digital processing to form a powerful image acquisition and processing system.
Abstract: A new type of silicon charge coupled device (CCD) imager which provides nine simultaneous video outputs representing a 3X3 pixel block that scans the imaging array has been used to emphasize edges and fine detail in various images. The device can also compensate for nonuniform scene illumination. Experimental results indicate that the device can be used to combine real-time analog image processing with subsequent digital processing to form a powerful image acquisition and processing system.