Showing papers on "Process corners published in 1999"

A 2 GHz VCO with process and temperature compensation

Abstract: A CMOS VCO with inherent compensation for temperature and process variations is presented. In the new design, the VCO input control is divided into two parts. One is controlled by a temperature and process compensation bias circuit and the other is controlled by an external input. A phase locked loop is used as the temperature and process compensation bias circuit. Two ideally identical VCOs are used. The control voltage of the VCO in the PLL will track the temperature and process variations. This control voltage is fed back to the VCO outside the loop. Simulation results show the total variation in the VCO frequency over a 100/spl deg/C temperature range and over the fast and slow process corners is about /spl plusmn/1.7%. This is a reduction of in excess of a factor of 12 when compare to a conventional VCO design based on the same delay stage.

Circuit impact and skew-corner analysis of stochastic process variation in global interconnect

Abstract: This paper details the impact of the stochastic interconnect process variation on the circuit performance of global interconnects in deep-submicron logic chips. Signal delay, rise time, and crosstalk variations of global interconnect circuits were first calculated by Monte Carlo simulations using a finite-difference field solver and a SPICE circuit simulator. These circuit performance matrices were subsequently expressed as a response surface function (RSF) of line width, line thickness, and dielectric thickness. The circuit impact was then gauged by a product of sensitivity obtained from the RSF and standard deviation derived from the manufacturing line. Furthermore, the RSF and the joint probability function (JPF) were combined to efficiently generate statistics-based 3-/spl sigma/ process corners. These process corners significantly improved circuit performance bounds in chip design, as compared to the overly pessimistic, conventional worst-case skew-corners.

Semiconductor integrated circuit and method of switching source potential of transistor in semiconductor integrated circuit

Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

Circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit

Abstract: A circuit configuration with a temperature-dependent semiconductor component self-test and repair logic circuit, in which at least one temperature sensor is provided in a semiconductor chip having a semiconductor component. In addition, the semiconductor component is connected in the semiconductor chip with the self-test and repair logic circuit.

Semiconductor integrated circuit and manufacturing method therefore

Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

Measuring the radiated emissions from a family of microprocessors using a 1-GHz TEM cell

Abstract: This paper presents a series of measurements of the radiated emissions from 8 and 16 bit microprocessors. The radiated emissions were measured using a 1-GHz TEM cell that incorporates the device under test (DUT) into the cell structure itself. For the 16 bit processor, samples from each of the manufacturer's identified process corners were measured and compared. Two separate fabrication lines were compared for process variability. The spatial location on the wafer was measured for emissions variation. In addition, emissions were measured for a 16 bit processor as a function of the operating temperature. Finally a comparison was made between discrete implementations of a module digital core and the same circuit implemented as an multichip module (MCM).

Integrated circuit device and semiconductor wafer having test circuit therein

Abstract: An integrated circuit device capable of testing manufacturing errors such as variations in dimensions at a masking step or the like or misalignment at an alignment step in a plurality of directions with a test circuit having a monitor transistor. The integrated circuit device has a functional circuit for performing a function assigned to the integrated circuit device and a test circuit. The test circuit comprises a plurality of MIS (Metal-Insulator-Semiconductor) transistors each having a gate electrode projecting from a gap between a source region and a drain region, respective gate electrodes projecting in directions different from one another. Typically, the integrated circuit device has a rectangular shape in which the test circuit is disposed inside of each vertex thereof. The test circuit is typically formed from four MOS (Metal-Oxide-Semiconductor) transistors having gate electrodes projecting in directions different from one another by approximately 90 degrees.

A monolithic 1.25 Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver

Abstract: This paper describes a monolithic CMOS clock/data recovery PLL circuit for 1.25 Gbits/sec fibre channel transceiver. Features include a fully differential high speed phase detector, high speed charge pump, and a 4-stage ring oscillator which is optimized to have enough tuning range to cover all process corners as well as temperature variation from 0/spl deg/C/spl sim/100/spl deg/C. The circuit was designed in 0.35 /spl mu/m single-poly, triple metal CMOS process. Simulations indicate that the core circuit along with the output buffer consumes 220 mW from a single 3.3 V supply in which 60 mW is dissipated by the core circuit itself.

Integrated circuit having reduced probability of wire-bond failure

Abstract: The present invention provides an improved integrated circuit technique for increasing the reliability of wire-bonds in an integrated circuit by increasing the contact angle between certain pins and their respective wire-bonds, particularly those pins otherwise most susceptible to wire-bond failure, i.e., those pins conventionally located toward the corners of a conventional integrated circuit. By doing so, the overall length of the wire-bonds in a chip will be reduced, which in turn can result in further reduction of the probability of wire-bond failures. In a disclosed embodiment, a five or more sided integrated circuit shape is introduced wherein pads on up to four sides of an integrated circuit wafer chip are bonded to pins supported on eight edges of an integrated circuit package. An integrated circuit having at least five pin-supporting edges renders more robust wire-bond angles for any given integrated circuit package size.

Clock skew determination from parameter variations at chip and wafer level

Abstract: Clock skews are determined by measuring device and metal line parameters as a function of position over chip and wafer. Experimental results are separated into a basic random fluctuation part and processing related contributions at chip and wafer level. Different clock tree circuits are simulated based on the measured data, and characterized with the delay, power consumption, layout area and temperature as parameters. Simulations yield a worst case skew of 42 ps for a 0.25 /spl mu/m process and a metal-3 H-clock tree.

Semiconductor integrated circuit and duty deterioration preventing method thereof

Abstract: A first circuit having deteriorated duty is connected to a second circuit having the same circuit arrangement and the same layout as that of the first circuit. The first and second circuits are connected to each other by means of an inversion logic. The difference between a rising time tr and a falling time tf generated in each circuit block of the first circuit is canceled by the circuit block of the second circuit corresponding to that of the first circuit. Accordingly, duty deterioration derived from types of blocks, branching and wiring capacity is prevented without the influence of process variation.

Fabrication of integrated circuits on both sides of a semiconductor wafer

Abstract: The present invention compactly fabricates integrated circuits of an electronic system on a semiconductor wafer by fabricating the integrated circuits of the electronic system on both sides of a semiconductor wafer. A first face of an area of the semiconductor wafer is processed with an integrated circuit fabrication process step to fabricate part of a first integrated circuit thereon. In addition, a second face of the area of the semiconductor wafer is processed with the integrated circuit fabrication process step to fabricate part of a second integrated circuit thereon. The first face and the second face are processed for a plurality of integrated circuit fabrication process steps until the first integrated circuit is completely fabricated on the first face and the second integrated circuit is completely fabricated on the second face. The first face and the second face of the area of the semiconductor wafer may both be processed simultaneously or may be processed one face at a time depending on the fabrication process step. That area of the semiconductor wafer is then cut from the rest of the semiconductor wafer such that the first integrated circuit and the second integrated circuit are on a die to be used within an electronic system. The present invention may be used to particular advantage when the first integrated circuit includes at least one processor and when the second integrated circuit includes at least one processor. In that case, the die having the first integrated circuit and the second integrated circuit is used within a multiprocessor system. With the present invention, integrated circuits of an electronic system are compactly fabricated onto both sides of a semiconductor wafer.

Semiconductor device having steady substrate potential

Abstract: A semiconductor device having an SOI structure having a contact for making steady the potential of a semiconductor substrate without involvement of an increase in the surface of the semiconductor device. In a semiconductor chip, an integrated circuit is fabricated within an internal circuit region, and a plurality of buffer circuits are fabricated within buffer regions. Wiring layers for supplying steady potential are formed in the area of the semiconductor chip other than the internal circuit region and the buffer regions; for example, at four corners of the semiconductor chip, and contacts for connecting the wiring layers and the semiconductor substrate are formed in the area of the integrated circuit which is not assigned for fabrication of integrated circuits, thus eliminating a necessity for ensuring a location specifically allocated for formation of the contacts.

Method of manufacturing semiconductor device and semiconductor integrated circuit device

Abstract: PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device and a semiconductor integrated circuit device which can be tested in a short time and can suppress increase of chip area. SOLUTION: A plurality of semiconductor integrated circuits 101 and a plurality of TEG circuits 103 are lined up on the board 100 of this semiconductor device. A built-in test circuit 102 is provided in a region opposite to and across a dicing region 150 to the semiconductor integrated circuit 101, in the plural TEG circuit 103. The built-in test circuit 102 and the semiconductor integrated circuit 101 are connected with each other by the wiring 104 provided on the dicing line region 150. The wiring 104 is cut at chip separation.

Error analysis method for integrated circuit device formed in several multi-chip wafer processes

Abstract: After each process, a new error is detected which was caused by the process in a new region of the wafer, which is next to a region where an error occurred in a previous process. After a number of processes, an error judgment is performed on the integrated circuit on a number of chips, and the existence of new errors is determined, so that the chips can be classified into groups. An Independent claim is also given for a process control method.

A new method for calculating one-dimensional process margin in consideration of process variations

Abstract: Yield and device characteristics in VLSI become more sensitive to process variations with finer patterns and enlargement of wafer size. Thus, process integration should take account of the inter- and intra-wafer process variations for elimination of yield loss. However, it is difficult to perform experiments which cover possible process variations because of cost and time. In this paper, we describe a new method for calculating a process margin for processes such as etching and deposition with consideration of process variations using the Monte Carlo method.