Showing papers on "Programmable logic array published in 1995"

A programmable logic device which stores more than one configuration and means for switching configurations

Abstract: A programmable logic device includes a configuration memory expanded to store two or more complete sets of configuration data. A switch on the output of the configuration memory controls the selection of the configuration data applied to the configurable logic block. Each configurable logic block has one data storage device per set of configuration data. The configurable logic blocks may be re-configured within a user's clock cycle. During a first period, the switch on the output of the configuration memory selects and passes configuration data from the first set of configuration data. The configurable routing matrix and configurable logic block are configured according to this first set of configuration data and store results in a first storage device. During a second period, the switch selects and passes the second set of configuration data. Then the configurable routing matrix and configurable logic block are configured according to the second set of configuration data, the function generator performs the second logic function, and the outputs are passed or stored by the second output device. At the end of the last period the function is available to the user.

Dynamically programmable gate array with multiple contexts

Abstract: An integrated dynamically programmable gate array comprises a two dimensional array of programmable gates. These gates can be implemented as look up tables but hardwired gates with programmable interconnections are also possible. Each one of the gates receives plural input logic signals from plural other gates. Consequently, a broad range of logic combinations are possible. The gates further include locally stored multiple contexts dictating different combinatorial logic operations performed by the gates. The contexts increase the logic operations performable by the gate and the fact that the contexts are locally stored enables better integration and speed. Only a context instruction needs to be distributed among programmable gates. A context signal generator is included that generates a context signal indicating a change in an active one of the contexts. This active context dictates the logic operations of the gates that commonly receive by the signal. Since the contexts information is stored on the gate array, and specifically locally, the context signal can change as fast as every clock cycle of the programmable gate array. To increase functionality, context memory arrays, which store context programming information, are separately addressable so that a new truth table is storable in a first one of the context memory arrays while a truth table of a second one of the context memory arrays is dictating the logic operations performed by the gates. As a result, the functionality of each programmable gate can be increased by increasing the number of available functions for that programmable gate.

Frequency driven layout system and method for field programmable gate arrays

Abstract: A device independent, frequency driven layout system and method for field programmable gate arrays ("FPGA") which allow for a circuit designer to specify the desired operating frequencies of clock signals in a given design to the automatic layout system to generate, if possible, a physical FPGA layout which will allow the targeted FPGA device to operate at the specified frequencies. Actual net, path and skew requirements are automatically generated and fed to the place and route tools. The system and method of the present invention evaluates the frequency constraints, determines what delay ranges are acceptable for each electrical connection and targets those ranges throughout the layout.

DPGA-coupled microprocessors

Abstract: A single chip microprocessor or memory device has reprogrammable characteristics according to the invention. In the case of the microprocessor, a fixed processing cell is provided as is common to perform logic calculations. A portion of the chip silicon real-estate, however, is dedicated a programmable gate array. This feature enables application-specific configurations to allow adaptation to the particular time-changing demands of the microprocessor and provide the functionality required to best serve those demands. This yields application acceleration and in system-specific functions. In other cases the configurable logic acts as network interface, which allows the same basic processor design to function in any environment to which the interface can adapt. The invention also concerns a memory device having a plurality of memory banks and configurable logic units associated with the memory banks. An interconnect is provided to enable communication between the configurable logic units. These features lessen the impact of the data bottle-neck associated with bus communications, since the processing capability is moved to the memory in the form programmable logic, which can be configured to the needs of the specific application. The inherently large on-chip bandwidth can then be utilized to increase the speed at which bulk data is processed.

Optimizing and operating a time multiplexed programmable logic device

Abstract: A method of optimizing a time multiplexed programmable logic device (PLD) includes entering a circuit design for the PLD, mapping the design to the physical resources of the PLD (wherein the physical resources include configurable logic elements), determining an appropriate micro cycle for each configurable logic element in the design, placing the resources on the PLD, and connecting the resources Optimizing the design may include reducing the number of look up tables or reducing the logic depth of the look up tables If the configurable logic elements include sequential logic elements, then the optimizing step includes rescheduling the sequential logic elements A method of operating a time multiplexed PLD in a logic engine mode includes programming the PLD to implement a design in stages, wherein each stage is one configuration, sequencing the PLD through all the configurations, and storing the results of the logic performed in one configuration in a plurality of micro registers for use in subsequent configurations In one embodiment, the PLD includes a plurality of combinational elements and sequential logic elements, wherein the values stored by the sequential logic elements are stored in the micro registers

Programmable logic array device with grouped logic regions and three types of conductors

Abstract: A programmable logic array device in which programmable logic regions are arranged in groups of four is provided. The device includes direct connect conductors for carrying signals totally within one group of four regions as well as to certain adjacent programmable logic regions, local conductors for carrying signals within groups and among adjacent groups, and global conductors for carrying device-wide signals. Connections among the various conductors, and between conductors and programmable logic regions, are provided to optimize the connection resources by avoiding switched conductor paths wherever possible.

A time-multiplexed FPGA architecture for logic emulation

Abstract: This paper presents an architecture for a FPGA oriented towards logic emulation, to achieve maximum usable logic density per unit silicon area, and fast mapping. Logic circuits are translated into a program that is executed sequentially by a network of processor elements. Overall, a sevenfold increase in raw logic blocks, and a 25-fold increase in usable logic blocks compared to a FPGA-based logic emulator is expected for a given silicon area.

Interconnect architecture for field programmable gate array using variable length conductors

Abstract: An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

Look-up table based logic element with complete permutability of the inputs to the secondary signals

Abstract: A logic element for a programmable logic device. The logic element includes a look-up table (400) for implementing logical functions, a programmable delay block (415), a storage block (430) configurable as a latch or a flip-flop, and a diagnostic shadow latch (435). A plurality of inputs (410) to the logic element and complements of these inputs are available to control the secondary functions of the storage block (430).

Digital Logic Circuit Analysis and Design

Abstract: 0. Introduction. 1. Number Systems and Codes. 2. Algebraic Methods for Analysis and Synthesis of Logic Circuits. 3. Simplification of Switching Functions. 4. Modular Combinational Logic. 5. Combinational Circuit Design with Programmable Logic Devices. 6. Introduction to Sequential Devices. 7. Modular Sequential Logic. 8. Analysis and Synthesis of Synchronous Sequential Circuits. 9. Simplification of Sequential Circuits. 10. Asychronous Sequential Circuits. 11. Sequential Circuits with Programmable Logic Devices. 12. Logic Circuit Testing and Testable Design. 13. Design Examples.

Implementation Approaches for Reconfigurable Logic Applications

Abstract: Reconfigurable FPGAs provide designers with new implementation approaches for designing high-performance applications. This paper discusses two basic implementation approaches with FPGAs: compiletime reconfiguration and run-time reconfiguration. Compile-time reconfiguration is a static implementation strategy where each application consists of one configuration. Run-time reconfiguration is a dynamic implementation strategy where each application consists of multiple cooperating configurations. This paper introduces these strategies and discusses the implementation approaches for each strategy. Existing applications for each strategy are also discussed.

Programmable logic module and architecture for field programmable gate array device

Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

Programmable array interconnect latch

Abstract: A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of the given interconnect and an output node coupled to a second portion of the given interconnect. A selective buffer circuit selectively outputs a buffered output signal to the output node that is related to a logic state at the input node. A signal storage circuit is also connected to the input node for selectively storing the logic state received from the input node. In a further embodiment, the signal storage circuit comprises an LSSD regis ter. A primary latch of the LSSD register receives data selectively either from the input node, in accordance with a first clock signal, or alternatively from a secondary serial input node, in accordance with a second clock signal. A secondary latch of the LSSD register is selectively coupled, per a third clock signal, to receive and latch therein latched data of the primary latch. Data representative of data latched within the secondary latch is provided at a secondary serial output, and selectively provided at the primary output node when enabled per a programmable enable signal. In yet a further embodiment, the LSSD register is part of a serial scan chain for selectively interfacing an interconnect boundary of the select block of the configured circuitry within the programmable gate array.

Programmable logic device for real time video processing

Abstract: A real time video processing system adds a programmable logic device between a conventional frame buffer and a conventional digital to analog converter to provide real time and off-screen processing power to enhance video output capabilities. The system may include a history FIFO connected to deliver the preceding line to the programmable logic device, allowing operations on a pixel in the current line, modified as needed by the status of one or more nearby pixels. The system may also include inputs for multiple video sources and may include input FIFOs for more random access to portions of the input stream. An alternative form of the system includes a crossbar switch and multiple memory devices, to allow switching among several possible frame buffer devices. One or more processing units can be added to manipulate a memory which is not the active frame buffer. The programmable logic device can be loaded with a configuration file stored in an associated memory or loaded from a host computer.

Programmable logic device with hierarchical confiquration and state storage

Abstract: In accordance with the present invention, a programmable array includes hierarchical configuration and state storage. The array comprises an active storage for an active configuration and an active state as well as an inactive storage for one or more inactive configurations and one or more inactive states. The array further comprises logic and routing configured by the active configuration. The logic includes a plurality of combinational elements and a plurality of sequential logic elements for providing the states. Bits are transferred between the active and the inactive storage. The inactive storage is accessible for read or write operations by the active configuration by a structure comprising: a core including a plurality of configurable elements selectively coupled to each other, a memory controller for controlling the memory that configures the logic and routing in accordance with the active configuration, a command register to hold commands for the memory controller, a memory address register to address the memory, and a memory data register coupled to the memory and the plurality of combinational elements. In one embodiment, the array of the present invention includes a configurable routing structure for providing the active configuration access to the memory address register, the memory data register, and the command register. The configurable routing structure is generally controlled by signals from the user logic, thereby significantly increasing user flexibility in using the programmable array.

Nonvolatile SRAM cells and cell arrays

Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is static, nonvolatile, and reprogrammable. The layout of the memory cell is compact. In a first state, a logic high output from this memory cell (400) is at about VDD; and in a second state, a logic low output is about VSS. The memory cell (400) of the present invention includes a first programmable memory element (515) and a second programmable memory element (520). First programmable memory element (515) is coupled between VDD (505) and a sensing node (405). Second programmable memory element (520) is coupled between the sensing node (405) and VSS (510). In the first state, first programmable memory element (515) is not programmed, while the second programmable memory element (520) is programmed. In the second state, first programmable memory element (515) is programmed, while second programmable memory element (520) is not programmed. The memory cell (400) may be used to store the configuration information of a programmable logic device (121).

Performance-oriented placement and routing for field-programmable gate arrays

Abstract: This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wire-length. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks.

Effects of FPGA Architecture on FPGA Routing

Abstract: Although many traditional Mask Programmed Gate Array (MPGA) algorithms can be applied to FPGA routing, FPGA architectures impose critical constraints and provide alternative views of the routing problem that allow innovative new algorithms to be applied. This paper describes routing models provided by some commercial FPGA architectures, and points out the effects of these architectures on routing algorithms. Implicit in the discussion is a commentary on current and future research in FPGA routing.

Programmable logic array integrated circuits with enhanced output routing

Abstract: A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). A general interconnect structure (20, 30) is provided for interconnecting a LAB with other LABs. A LAB-based interconnect structure (24, 26) is provided for connecting inputs of the LEs in a LAB to a subset of the general interconnect. One or more of output signal lines (55) are included in the LAB-based interconnect structure and are connectable to device output pins. A digital information processing system incorporating the invention is disclosed.

Programmable logic device with memory that can store routing data of logic data

Abstract: A programmable logic device is disclosed which can be used either as a look-up table logic device or as a logic function generator This enables combinations to be provided such as the combination of a look-up table with a fixed gate field programmable gate array

Programmable logic device with regional and universal signal routing

Abstract: A programmable logic device having a plurality of logic cells (151-15N) arranged in groups defining separate logic regions (111-11N), both regional (191-19N) and multi-regional (13) bus lines, and a crosspoint switch matrix (37) which serves only to route signals from bus lines (391-39J and 401-40L) to inputs of the logic cells (311-31J) without logically combining two or more of the bus signals, i.e. without forming product terms. Rather, all logic is carried out by the logic cells (311-31J) themselves. In particular, the switch matrix (37) is constructed so that each bus line (391-39J and 401-40L) can connect to one or more logic cell inputs, but each logic cell input can meaningfully connect to only one bus line without shorting. In one embodiment, each logic cell (311-31J) feeds one logic signal back (411-41J) to a regional bus line (191) and can potentially feed back another logic signal through its region's universal select matrix (47) to a universal bus line (13). The select matrix (47) connects a subset of the region's potential feedback signals to the universal bus (13).

Programmable logic device including configuration data or user data memory slices

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

Input/output interface circuitry for programmable logic array integrated circuit devices

Abstract: In a programmable logic array integrated circuit device, various techniques are used to increase the flexibility with which the core logic of the device can be connected to the input and/or output pins of the device. While the techniques shown greatly increase circuit flexibility, they avoid the unnecessary overhead of interconnectivity which is completely general.

Using Programmable Logic to Accelerate DSP Functions

Abstract: Programmable logic offers an alternative solution for the computationally-intensive functions found in Digital Signal Processing (DSP). Programmable logic can provide increased DSP system performance at reduced system cost. Programmable logic combines the flexibility of a general-purpose DSP plus the speed, density, and low cost of an ASIC implementation. In some applications, programmable logic replaces the DSP processor entirely. In others, programmable logic works in conjunction with the DSP processor, offloading the computationally-intensive function and freeing the processor for other functions.

Circuit for selecting a bit in a look-up table

Abstract: This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

Memory in a programmable logic device

Abstract: A programmable logic device includes a plurality of logic blocks coupled to an interconnect matrix, wherein one of the plurality of logic blocks comprises configurable memory logic having control logic coupled to a storage element. The control logic receives a plurality of control signals from the interconnect matrix and performs substantially all logic functions required for the configurable memory logic to selectively function as each of a plurality of memory devices. The plurality of memory devices includes a first-in-first-out (FIFO) memory device, a last-in-first-out (LIFO) memory device, a single-port memory device (e.g. single-port SRAM) and a multi-port memory device (e.g. dual-port RAM). Additionally, multiple logic blocks may comprise configurable memory logic. Each logic block may perform a different memory function. These logic blocks can be cascaded together to form memory devices with greater memory depths and/or widths than possible with a single logic block with configurable memory logic.

Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems

Abstract: System Implementation Strategies. Review of Logic Design and Electrical Aspects. Introduction to FPGA Architecture. Design Process Flows and Software Tools. Case Studies. Computational Applications. Business Development. Recent Developments. Afterword. Glossary. Index.

A transconductor-based field-programmable analog array

Abstract: Field-programmable gate arrays for prototyping digital circuits are a widely endorsed approach for reducing time-to-market. Offering similar advantages, a field-programmable analog array (FPAA) for prototyping continuous-time analog circuits is reported here. Conceptually, a FPAA consists of configurable analog blocks (CABs) and interconnects. The function of each CAB and the connections among CABs are determined by the contents of an on-chip shift register. Different circuits can be instantiated using a FPAA by loading in different configuration bits. This IC strategy offers simplified analog circuit design with the advantages of instant prototyping, programmable topology, programmable parameters, CAD compatibility, and testability.

An implicit enumeration algorithm to generate tests for combinational logic circuits

Abstract: The D-Algorithm (DALG) is shown to be ineffective for t he class of combinational logic circuits that is used to implement Error Correction and Translation (ECAT) functions. PODEM (Path-Oriented D ecision Making) is a new test generation algorithm for combinational logic circuits. PODEM uses an implicit enumeration approach analogous to that used for solving 0 - 1 integer programming problems. It is shown that PODEM is very efficient for ECAT circuits and is significantly more efficient than DALC over the general spectrum of combinational logic circuits. its simplicity when compared to the D-Algorithm. PODEM is a complete algorithm in that it will generate a test if one exists. H euristics are used to achieve an efficient implicit search of the space of all possible primary input patterns until either a test is found or the space is exhausted. A distinctive feature of PODEM is

Non-reconfigurable microprocessor-emulated FPGA

Abstract: In accordance with the present invention, a microprocessor controlled device is provided which appears to a user to be a programmable logic device. Signals are taken from and placed on external pins in the same manner as would be done with a prior art programmable logic device. However, internal hardware which would be provided in a programmable logic device for performing the logic function is replaced by a microprocessor with associated memory. The microprocessor is programmable to read input signals from input pins, perform calculations related to the desired logic, and place signals onto output pins. Thus the function of the microprocessor controlled device as it appears from observing signals on external pins is the same as that of a prior art FPGA or other logic device. However, internally, a program which has been stored in the memory associated with the microprocessor causes the microprocessor to serially read signals from external pins, perform the necessary calculations, and place signals onto output pins. Multiple microprocessors in the same logic device can also be provided.