Showing papers on "Programmable logic device published in 1991"

Building and using a highly parallel programmable logic array

Abstract: A two-slot addition called Splash, which enables a Sun workstation to outperform a Cray-2 on certain applications, is discussed. Following an overview of the Splash design and programming, hardware development is described. The development of the logic description generator is examined in detail. Splash's runtime environment is described, and an example application, that of sequence comparison, is given. >

Programmable logic element interconnections for programmable logic array integrated circuits

Abstract: A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Improved logic synthesis algorithms for table look up architectures

Abstract: The authors address the problem of synthesis for a popular class of programmable gate array architecture-the table look-up architectures. These use lookup table memories to implement logic functions. The authors present improved techniques for minimizing the number of table look up blocks used to implement a combinational circuit. On average, the results obtained on a set of benchmarks are 15-29% better than results obtained by previous approaches. >

Ultra low power CMOS technology

Abstract: This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.

Versatile programmable logic cell for use in configurable logic arrays

Abstract: An improved programmable logic cell for use in a programmable logic array comprising cells which are arranged in a two-dimensional matrix of rows and columns and are interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), and one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell receives input(s) from each of its nearest neighbors and additional input(s) (from a bus, pin, or neighbor) and may be programmed to generate a variety of logical functions at its outputs which connect to the cell's four nearest neighbors. The core of the improved logic cell comprises two upstream gates, the outputs of which feed two downstream gates, one of which is an exclusive-OR gate which feeds a downstream register. Additional programmable connections and other logic augment the cell core to produce cell embodiments which can be configured to efficiently implement various logical functions. Among the functions which may be implemented by the improved cell are a number of two-level combinational functions (such as multiplexing) and sequential functions (such as counting and shifting). A variety of cell embodiments based on the improved cell core are illustrated.

Performance directed synthesis for table look up programmable gate arrays

Abstract: The authors address the problem of delay optimization for programmable gate arrays. The main considerations are the number of levels in the circuit and the wiring delay. The authors propose a two-phase approach: the first phase involves delay optimizations during logic synthesis before placement, while the second uses logic resynthesis in the case of a timing-driven placement technique. Results and comparisons on benchmarks are presented. >

Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets

Abstract: A reconfigurable sequential processor includes a data bank for storing data to be processed; a programmable logic block address generator for addressing data in the data bank; a programmable logic block arithmetic unit responsive to the data bank for processing the data addressed by the programmable logic block address generator; an address generator hardware configuration file having a plurality of configuration files for configuring the programmable logic block address generator in one of a plurality of addressing configurations in response to an address operational code; an arithmetic hardware configuration file having a plurality of configuration files for configuring the programmable logic block arithmetic unit in one of a plurality of processing configurations in response to an arithmetic operational code; and for delivering a series of operational codes to each configuration file for enabling the programmable logic block address generator and the programmable logic block arithmetic unit to be configured to perform sequentially a corresponding series of arithmetic logic operations on the data in the data bank.

Extraction of gate level models from transistor circuits by four-valued symbolic analysis

Abstract: The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The results model contains only four-valued unit and zero delay logic primitives, suitable for evaluation by conventional gate-level simulators and hardware simulation accelerators. TRANALYZE has the same generality and accuracy as switch-level simulation, generating models for a wide range of technologies and design styles, while expressing the detailed effects of bidirectional transistors, stored charge, and multiple signal strengths. It produces models with size comparable to ones generated by hand. >

Input/output macrocell for programmable logic device

Abstract: In a programmable logic device having a programmable logic array 15 adapted to receive a plurality of input signals and provide a plurality of output signals (product terms) through an AND logic which depend on the input signals and information stored in the logic array and a macrocell associated with the logic array, the macrocell including a first OR gate group 11 including a plurality of OR gates, each for ORing the predetermined number of the product terms from the logic array; a demultiplexor group 12 including a plurality of demultiplexors each coupled to output of the corresponding OR gate in the first OR gate group 11, each for generating two or more output signals per one input signal; a second OR gate group 13 including a plurality of OR gates each coupled to a corresponding one of outputs of each of the plurality of demultiplexors, each for ORing the corresponding outputs from the plurality of demultiplexors to form a sum data path for the product terms; and an input/output circuit 14 for receiving data from the plurality of sum data paths for the product terms provided by the plurality of OR gates in the second OR gate group 13 to transfer the received data to an output stage or feedback that to the logic array; whereby the plurality of sum data paths for the product terms are provided in one macrocell.

Method for operating a multiple page programmable logic device

Abstract: A PLA is formed using configurable logic elements. A plurality of pages are used to store information defining logic configuration patterns required to perform desired logical functions. The configurable logic elements are configured by downloading information from a desired one or more of said pages. If desired, page control is achieved in response to input signals to the configurable logic array.

Technology mapping for electrically programmable gate arrays

Abstract: We describe a new approach for technology mapping of electrically programmable gate arrays (EPGAs). These are arrays of uncommitted modules, where the personalization is achieved by fuselantifuse technology and can be modeled by stuck-at and/or bridging inputs. We present a matching algorithm that determines whether a portion of a combinational logic circuit can be implemented by personalizing a module. The algorithm has the advantage of considering the entire library of functions that can be implemented by the module without resorting to an explicit enumeration. The benefits are an increased efficiency in technology mapping, as well as portability to different types of electrically programmable gate arrays. Experimental results on standard benchmarks are reported.

Method and apparatus for converting a programmable logic device designed into a selectable target gate array design

Abstract: The present invention is a translation system that translates a definition of a prototyped programmable device defined in a programmable device specification into a generic behavioral model of the device and into lists of logic blocks and connections for implementing the device as a non-programmable device in an application specific target technology. The lists and behavioral models are used to create command files that drive logic synthesis and network connection list processing operations to generate a generic list of logic and network connections. The generic list and commands are used to create device test vectors for testing the behavior of the model and the target device design. The target technology lists and command files are processed to reduce redundant logic and are mapped into logic blocks and connection lists in the target technology. The operation of the target technology design is simulated using the target logic blocks and connections and the test vectors. The behavioral model is compiled to allow behavioral simulation of the operation of the device using the same test vectors. When the simulation of the target technology and the behavioral model produce identical outputs, the target non-programmable design exactly matches the operation of the prototype programmable device and the target technology design can then be used in mass production of the logic device.

A new vision system: programmable logic devices and digital signal processor architecture (PLD+DSP)

Abstract: The authors show a way to establish a good structure for an image processing system. Image processing algorithms are classified as a function of the input/output information structure. Then a whole system is created, with different processing architectures inside, one for each group in the classification. The main devices in the whole machine are a digital signal processor (DSP), and specific hardware designs into erasable programmable logic devices (EPLDs). It is shown how these specific designs can be made with a few different printed circuit boards, and specific circuits are loaded from a library into EPLD chips. This library is prepared in the computer, and the machine is easily adapted to a specific application. >

Method for programming programmable elements in programmable devices

Abstract: A method for programming programmable EPROM elements in programmable logic arrays. Multiple programming passes are made through the array, with the programming pulses decreasing in duration on each pass.

Design of robustly testable combinational logic circuits

Abstract: An integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests is proposed. Robustly testable static CMOS primitive logic circuit designs are presented for any arbitrary combinational logic function. They require no special gates, and fan-in and fan-out constraints do not affect the designs. Extra controllable inputs or additional hardware to achieve testability was not used. It is demonstrated that the method guarantees the design of CMOS logic circuits in which all path delay faults are locatable. >

Programmable power reduction circuit for programmable logic device

Abstract: According to the present invention, during programming of a programmable logic device, programming in formation corresponding to an input signal is loaded into a shift register. This input information is compared with programming information corresponding to a second, complementary input signal to determine if the two signals are used by the programmable logic device. If the two inputs are not used, a bit is stored in a memory cell indicating such nonuse. An input buffer is disabled when the bit in the memory cell indicates the complementary signals corresponding to that input buffer are not used.

Optimization of field-programmable gate array logic block architecture for speed

Abstract: The authors explore the effect of the choice of logic block on the speed of a field-programmable gate array (FPGA). A set of logic circuits was implemented as FPGAs, each using a different logic block, and the speed of the implementation was measured. While the result depends on the delay of programmable routing, experiments indicate that wide input PLA (programmable logic array)-style AND-OR gates, four- and five-input lookup tables, and certain multiplexer configurations produce the lowest total delay over the important values of routing delay. Furthermore, significant gains in performance (from 10% to 41% reduction in total delay) can be achieved by connecting a small number of logic blocks together using hard-wired connections. >

Minimization algorithms for multiple-valued programmable logic arrays

Abstract: The performance of various heuristic algorithms for minimizing realizations of multiple-valued functions by the charge-coupled device (CCD) and CMOS programmable logic arrays (PLAs) of H.G. Kerkhoff and J.T. Butler (1986) and J.G. Samson (1988), respectively, is analyzed. The functions realized by the PLAs are in sum-of products form, where the sum is ordinary addition truncated to the highest logic value and the product represents the MIN operation of functions of the input variables that are the interval literal operations. Three heuristics, proposed by G. Pomper and J.A. Armstrong (1981), P.W. Besslich (1986), and G.W. Dueck and D.M. Miller (1987), are compared over sets of random and random-symmetric functions. An exact minimization method that is a tree search using backtracking is described. A reduction in the search space is achieved by considering constrained implicant sets and by eliminating some implicants altogether. Even with this improvement, the time required for exact minimization is extremely high when compared to all three heuristics. The case involving only prime implicants is considered, and it is shown that such implicants have marginal value compared to constrained implicant sets. The basis of comparison is the average number of product terms. >

Integrated circuits having antifuses

Abstract: An integrated circuit has electrically programmable antifuses comprising hydrogenated amorphous silicon(11) and a transition metal(5,15). The antifuse, which has a high OFF state resistance and a low ON state resistance, is useful in electrically programmable read only memories, programmable logic arrays, and other integrated circuits in which electrical circuits have to be selectively closed.

Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix

Abstract: Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles

Abstract: A hardware simulator comprises a plurality of interconnected programmable logic devices (20) which are connected via a data bus (22) and a control bus (24). Address signals on control bus (24) are read by an interconnect logic block (18) associated with each device to selectively link the output latches and input latches of the devices (20) to the data bus (22). Accordingly, a series of signal transfers is carried out between the devices simulating the hardware. The interconnect logic blocks may be programmed to provide whatever connections between devices are required.

Programmable logic device with limited signal swing

Abstract: A programmable logic device is described. The programmable logic device includes a plurality of memory cells, each having a drain, a source, a floating gate, and a control gate. A first bit line is coupled the drain of each of the plurality memory cells. The bit line provides a voltage level. A second bit line is coupled to the source of each of the plurality of memory cells. The programmable logic device further includes means for controlling the voltage level to swing between a first voltage state and a second voltage state. The controlling means receives current from the first bit line to clamp the voltage level to the first voltage state when the voltage level exceeds the first voltage state. The controlling means provides current to the first bit line and limits current flow of the first bit line to maintain the voltage level to the second voltage state when the voltage level exceeds below the second voltage state.

A CAD system for the design of field programmable gate arrays

Abstract: Field Programmable Gate Arrays (FPGA’s) are a relatively new type of chip. This paper describes the software necessary to support two distinct but closely related aspects of them: the development of a new FPGA architecture, and the use of FPGA’s from an application viewpoint. The basic CAD support structure consists of a set of file formats and programs that successively bind and evaluate design decisions. The FPGA designer starts by specifying a block architecture as a schematic. This is analyzed, manipulated, and condensed into a set of files that characterize the routing capabilities and programming requirements of the proposed FPGA design. The application designer specifies a circuit in a standard format (SLIF). This is bound to the resources available in the generic FPGA. The result is a configuration file that maps the application onto the proposed FPGA fabric. During FPGA development, the efficiency of this mapping can be analyzed, and the architecture modified. Once the FPGA has been fabricated, the configuration data can be sent to the actual hardware.

Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs

Abstract: The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of nodes to be minimized, one first calculates sets of supports which are necessary to construct the functions for the given nodes by applying functional reduction. The functional reduction process guarantees that one can get the minimal support for each node. One then makes a covering table for the set of nodes to be minimized so that one can get the minimal supports to cover all the functions for the given set of nodes to be minimized. The authors present a preliminary implementation and its results for ISCAS combinational benchmark circuits combined with MIS2.1 standard script and a Boolean resubstitution minimizer, and show the effectiveness of the presented method. >

Three-level decomposition with application to PLDs

Abstract: A scheme for programmable logic array (PLA) decomposition that consists of one level of PLAs followed by a second level of simple two-input logic gates is presented. The propagation delay is therefore the sum of the delay through one level of PLA and one level of two-input gates. Since the delay through a two-input gate is significantly less than that through a PLA, the timing performance of the new scheme is generally superior to those of earlier PLA decomposition schemes. The sizes of the PLAs used depend on the choice of the two-input gates. An algorithm is presented that chooses the functionality of the gates such that the areas of the first-level PLAs are minimized, further improving performance. The new decomposition scheme was developed for the automatic programming of a programmable logic device (PLD) which had basically a three level architecture. The functional unit for such a PLD is described and the application of the algorithm to the programming of these functional units is discussed. Experimental results show that the new scheme significantly reduces the area over the single PLA implementation. >

A spreadsheet simulation of logic networks

Abstract: The authors present a method for simulating logic networks using spreadsheets. This method may be used to simulate combinational, sequential, synchronous and asynchronous networks. The characteristics of the method make it significant as an important tool in the analysis, design and test logic networks in education environments. >

Optical cellular logic image processor: implementation and programming of a single channel digital optical circuit.

Abstract: A diode-laser driven all-optical iterative processor has been constructed and tested. Results are presented showing operation equivalent to a single channel of the cellular logic image processor architecture. Functional features of the circuit include optically programmable logic, thresholding, and data synchronization. Essential elements such as cascadability, logic-level restoration, and data feedback have been demonstrated with the optical processor controlled by a conventional electronic computer. Serial processing algorithms for word recognition, comparison, full addition, and subtraction have been implemented. Comments on the reliability of operation and future plans for expansion are made.

Programmable logic device with multiple, flexible asynchronous programmable logic blocks interconnected by a high speed switch matrix

Abstract: An asynchronous high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programamble logic blocks. Each programmable logic block includes programmable output logic macrocells, programmable input/output macrocells, programmable input logic macrocells, a logic allocator and a programmable product term array. Further, the switch matrix provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix decouples the output logic macrocells from the product term array. The logic allocator decouples the product term array from the output logic macrocells, and the I/O macrocells decouple the output logic macrocells from the package I/O pins. Thus, the architecture of this invention is easily scalable to higher density devices without compromising speed. The logic allocator steers product terms from the product term array to selected logic macrocells so that no logic product terms are permanently allocated to a specific logic macrocell. Each output logic macrocell is provided three dedicated control product terms from the programmable product term array and each I/O macrocell is provided one control product term from the programmable product term array in one embodiment. These four dedicated product terms are used to implement asynchronous applications. Each asynchronous programmable logic device of this invention is derived from the core of a programmable logic device in a family of synchronous programmable logic devices.