Showing papers on "Residue number system published in 1997"

The digit parallel method for fast RNS to weighted number system conversion for specific moduli (2κ - 1,2κ, 2κ + 1)

Abstract: Residue number systems have computational advantages for addition and multiplication since operations on residue digits are performed independently and so these processes can be performed in parallel. However other operations such as input/output conversions are significantly more difficult. A method for conversion from a specific residue number system with moduli of the form (2 k - 1,2 k , 2 k + 1) to a weighted number system is presented here. The digit parallel method is significant, in that the largest number which must be handled is of the same order as the moduli, the digits of the result are calculated in parallel, and the required moduli operations are accomplished with addition or subtraction of a constant.

The digit parallel method for fast RNS to weighted number system conversion for specific moduli (2/sup k/-1,2/sup k/,2/sup k/+1)

Abstract: Residue number systems have computational advantages for addition and multiplication since operations on residue digits are performed independently and so these processes can be performed in parallel. However other operations such as input/output conversions are significantly more difficult. A method for conversion from a specific residue number system with moduli of the form (2/sup k/-1,2/sup k/,2/sup k/+1) to a weighted number system is presented here. The digit parallel method is significant, in that the largest number which must be handled is of the same order as the moduli, the digits of the result are calculated in parallel, and the required moduli operations are accomplished with addition or subtraction of a constant.

Circuit and system for modulo exponentiation arithmetic and arithmetic method of performing modulo exponentiation arithmetic

Abstract: In order to avoid large-scale arithmetic circuit and a complicated processing procedure in performing modular arithmetic such as a modular arithmetic exponentiation and modular multiplication in use for encrypting plaintext or the like, the method and apparatus of the present invention for performing the modular arithmetic which executes a first common equation of a modular multiplication arithmetic f(A, B)=A×BmodN ("mod" denotes modular arithmetic) to calculate a remainder of a product of an integer A and an integer B divided by an integer N, using a second common equation of Montgomery's replacement arithmetic f(A, B)=A×B×R'modN corresponding to the first common equation f(A, B)=A×BmodN (R' denotes a value to meet the equation R×R'modN=1 with respect to R which is an exponent of 2 slightly larger than modulus N), a first replacement arithmetic f1 '(RS modN×AT, BU) (S denotes one of 0, 1, and 2; T denotes one of 0 and 1; and U denotes one of 0 and 1), and a second replacement arithmetic f2 '{R2-S modN×AT ×f1 '(RS modN×AT, BU), RS modN×A1·T ×B1·U)} are performed.

Scaled and unscaled residue number system to binary conversion techniques using the core function

Abstract: The paper presents related techniques for converting a residue number system (RNS) number to binary, with and without scaling, that use the core function. The techniques remove the difficulties associated with conversion procedures based on the Chinese remainder theorem and the mixed-radix conversion technique. Two new methods for extracting the core of an RNS number are also presented that employ a parity bit to eliminate ambiguity.

Design and implementation of an RNS division algorithm

Abstract: In 1995 the authors introduced the main outlines of a new algorithm for division in residue number system, which can be applied to any moduli set. Simulation results proved that the algorithm was many times faster than most competitive published work. Determining the position of the most significant nonzero bit of any residue number in that algorithm is the major speed limiting factor. They customize the same algorithm to serve two specific moduli sets: (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) and (2/sup k/+1, 2/sup k/, 2/sup k/-1), and thus, eliminate that speed limiting factor. Based on this work, hardware needed to determine most significant bit position has been reduced to a single adder. Therefore, computation time and hardware requirements are substantially improved. This would enable RNS to be a stronger force in building general purpose computers.

A residue arithmetic extension for reliable scientific computation

Abstract: A reliable scientific computation approach, substantially different from the known ones, based on Residue Number System (RNS) floating-point arithmetic is described. In the approach, the real number is represented by an expression which consists of two parts, the approximate part and the interval error part. The approximate part, represented by an RNS floating-point number, shows an approximate value for the real number. The interval error value, represented by two RNS floating-point numbers, shows the left and the right limit of an interval containing the error. In parallel to the result of operation, the rounding error induced by that operation is determined and then summed up in each operation. When a series of operations is completed, the range of existence for the result can be determined from the result of the computation and the sum of interval errors. For the illustration of the proposed method, some examples are also given, which are said to be difficult to find exact solution in the usual floating-point calculation.

An RNS Montgomery modular multiplication algorithm

Abstract: The authors present a new RNS modular multiplication for very large operands. The algorithm is based on Montgomery's method adapted to mixed radix, and is performed using a residue number system. By choosing the moduli of the RNS system reasonably large, and implementing the system an a ring of fairly simple processors, an effect corresponding to a redundant high-radix implementation is achieved. The algorithm call be implemented to run in O(n) time on O(n) processors, where n is the number of moduli in the RNS system, and the unit of time is a simple residue operation, possibly by table look-up.

On the binary quadratic residue system with noncoprime moduli

Abstract: The residue number system (RNS) appropriate for implementing fast digital signal processors since it can support parallel, carry-free, high-speed arithmetic. A development in residue arithmetic is the quadratic residue number system (QRNS), which can perform complex multiplications with only two integer multiplications instead of four. An RNS/QRNS is defined by a set of relatively prime integers, called the moduli set, where the choice of this set is one of the most important design considerations for RNS/QRNS systems. In order to maintain simple QRNS arithmetic, moduli sets with numbers of forms 2/sup n/+1 (n is even) have been considered. An efficient such set is the three-moduli set (2/sup 2k-2/+1.2/sup 2k/+1.2/sup 2k+2/+1) for odd k. However, if large dynamic ranges are desirable, QRNS systems with more than three relatively prime moduli must be considered. It is shown that if a QRNS set consists of more than four relatively prime moduli of forms 2/sup n/+1, the moduli selection process becomes inflexible and the arithmetic gets very unbalanced. The above problem can be solved if nonrelatively prime moduli are used. New multimoduli QRNS systems are presented that are based on nonrelatively prime moduli of forms 2/sup n/+1 (n even). The new systems allow flexible moduli selection process, very balanced arithmetic, and are appropriate for large dynamic ranges. For a given dynamic range, these new systems exhibit better speed performance than that of the three-moduli QRNS system.

The Digit Parallel Method for Fast RNS to Weighted Number System Conversion for Specific Moduli

Abstract: Residue number systems have computational advantages for addition and multiplication since operations on residue digits are performed independently and so these processes can be performed in parallel. However other operations such as input/output conversions are significantly more difficult. A method for conversion from a specific residue number system with moduli of the form to a weighted number system is presented here. The digit parallel method is significant, in that the largest number which must be handled is of the same order as the moduli, the digits of the result are calculated in parallel, and the required moduli operations are accomplished with addition or subtraction of a constant.

Apparatus useful in floating point arithmetic

Abstract: A computer and a method of using the computer to separate a floating-point number into high and low parts and for evaluating a dominant arithmetic object and a remainder object. The dominant object is associated with the first arithmetic object by using the high parts of the floating-point number. The evaluation of a remainder arithmetic object associates the first arithmetic object with the high and low parts of the floating-point numbers. A sum of the dominant and remainder arithmetic objects returns a value corresponding to the first arithmetic object.

Eisenstein residue number system with applications to DSP

Abstract: A new approach for processing complex numbers has been proposed, Basically, it is aimed at the implementation of radix-3 FFTs, but it can be used in any situation where the requirement to process Eisenstein integers arises, The comparison between the quadratic residue number system and ERNS provides information on available primes and dynamic ranges for the two number systems, This information can be used to decide on which number system is more appropriate for specific processing requirements.

Design of testable multipliers for fixed-width data paths

Abstract: The usage of multipliers in fixed-width data-dominated architectures (also termed data paths) poses serious testability problems. Due to truncation of their outputs, the fault observability of the multipliers degrades, and the resulting output patterns are inadequate to completely test functional blocks that are driven by them. Consequently, the overall random pattern testability of data paths deteriorates substantially. In this paper, we propose new generic design schemes, based on residue number system arithmetic, to improve the overall testability of data paths. The approach uses, in the test mode, the truncated least significant bits of the product to increase the variety of patterns at the output of a multiplier. This, in turn, improves the fault detectability of multipliers, and consequently, have a remarkable impact on the overall testability of data paths. The proposed techniques can be incorporated with a minimal performance degradation and area overhead, and are independent of the multiplier architecture. Experimental analysis performed on four high-level synthesis benchmarks exhibits a significant improvement in the overall testability of the corresponding data-path implementations.

Fraction-free RNS algorithms for solving linear systems

Abstract: This paper is concerned with overcoming the arithmetic problems which arise in the solution of linear systems with integer coefficients. Specifically, solving each systems using (integer) Gauss elimination or its variants usually results in severe growth in the dynamic range of the integers that must be represented. To alleviate this problem, a residue number system (RNS) can be utilized so that large integers can be represented by a vector of residues which require only short wordlengths. RNS arithmetic, however, cannot easily handle any divisions that are needed in the solution process. This paper presents fraction-free algorithms for the solution of integer systems. This does involve divisions, but only divisions where the result is known to be an exact integer. The other principal contribution of this paper is the presentation of an RNS division algorithm for exact integer division which does not require any conversion to standard binary form. It uses entirely modular arithmetic, perhaps including a step equivalent to RNS base extension.

Area-time performance of VLSI FIR filter architectures based on residue arithmetic

Abstract: The area-time (A/spl middot/T) optimization of a particular class of residue number system (RNS)-based FIR processors is discussed in this paper. To facilitate the optimization procedure, a number of performance models are introduced. Furthermore, moduli bases are attained that lead to RNS FIR filter architectures of minimal A/spl middot/T/sup 2/ product. The A/spl middot/T/sup 2/ performance models include the binary-to-residue and residue-to-binary conversion complexity. In particular, efficient Chinese remainder theorem (CRT) architectures are derived, based on multiply-by-constant units (MCUs), which are systematically designed by an introduced methodology. The A/spl middot/T/sup 2/ performance of the derived residue FIR filter architectures is found to surpass equivalent binary structures under certain conditions.

A new RNS FIR filter architecture

Abstract: A fast architecture for the implementation of FIR filters based on the residue number system is proposed. High-speed is obtained by introducing residue arithmetic that permits the computation of the filter output by using N FIR subfilters of reduced dynamic range operating in parallel. Moreover, a new approach for the computation of the modulo operation on each term of the linear combination has been developed. The filter implementation is based on small look-up tables and fast multioperand carry-save adders.

Modular arithmetic using low order redundant bases

Abstract: N-digit, radix-/spl alpha/ bases are proposed for VLSI implementation of redundant arithmetic, mod m, where /sub m/=/spl plusmn/1, /sub m//spl ne//spl plusmn/1, for 0

Fault-tolerant performance of data transmission models based on redundant residue number system

Abstract: Fault-tolerant data transmission models based on the redundant residue number system are proposed in this paper; they can transmit data correctly between two ends unless the residue errors exceed the error-correction capability. The expressions for the probability of error are presented when the channel noise is additive Gaussian noise and each branch is M-ary orthogonal signaling modulation. The expressions of the probabilities of undetected and uncorrected error are also obtained when the redundant residue number system are single error-checking and single error-correcting model, respectively.

Circular Shift Registers

Abstract: The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed im- plementation of residue number system anthmetic. It is then sur rising that the successful recurrent operation of such a s&ft register has never been reported in the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits--the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, laten- cies and areas. These desi ns differ in the topology of the clock distribution networf as well as the ty e of storage element employed in the data path. Two fesigns show satisfactory parameter margins and large maximum clock frequency. I. INTRODUCTION Digital signal processors with multi-gigahertz clock rates and high bandwidth mixed-signal circuits (l) require fzst aid robust memory unit to store repeatedly used &ita. In Rapid single flux quantum (RSFQ) logic, serial memory imple- meuted with circular shift registers (CSR) is an ideal choice for this task. These registers can be used to store the coeffi- cients of a digital filter (2), the samples of an arbitraiy wave- foiin generator, etc. Circular shift registers are also used as tlie core element of computational units to perfoi-m residue nurn- ber system arithmetic (3). RSFQ circular shift registers com- bine short access time with high throughput and cai be easily interfaced to low-frequency, extei-nal semiconductor electrou- ics.

Application of the Residue Number System to Digital Communication Systems

Abstract: Digital signal processors (DSP) are beginning to dominate the communications industry. The demand of the industry is to provide smaller, lighter, lower powered communication technology without sacrificing performance. This study investi­ gates the application of an alternative method of implementation for a digital frequency modulation receiver, the cross-correlator. Instead of using a traditional fixed point DSP based platform, residue number systems (RNS) are applied to the application. The main focus of this work iey to evaluate the performance of an RlNS based cross-correlator receiver and compare it to the same receiver using traditional fixed point DSP techniques. Theoretical calculations are performed on the receiver and a model is developed. The model is developedto allow for the analysis of both the fixed point DSP based receiver as well as the RNS based receiver. This model is used to analyze the bit error rate (BER) performance of the receiver for various input signal to noise ratios. Comparison of the model's BER results indicates that an RNS based receiver using 6-bits for quantization of all receiver inputs and 6-bits at the output of the receiver performs as well as an 8-bit fixed point DSP based receiver. 11 The cross-correlator receiver is also simulated to determine the accuracy of the model. Both the RNS and DSP based methods of implementation are simulated. The BER results from the simulation show that the RNS based receiver using 6-bits for quantization and output does not perform as well as the 8-bit DSP based system. However by using 8-bits for the quantization of the low pass filter coefficients, the BER performance of the RNS based system significantly improves. The model and simulation provide similar performance ratings, however the model is not as affected by the characteristics of the low pass filters.

WSI oriented design for noise-tolerant systems based on the residue number system

Abstract: This paper presents a design method for noise-tolerant WSI systems in which the features of the residue number system and multiple clock pulses are effectively combined. The analysis shows that the reliability of the presented system is greatly improved and the redundant hardware is small.