Showing papers on "Residue number system published in 2018"

A Full RNS Variant of Approximate Homomorphic Encryption

Abstract: The technology of Homomorphic Encryption (HE) has improved rapidly in a few years. The newest HE libraries are efficient enough to use in practical applications. For example, Cheon et al. (ASIACRYPT’17) proposed an HE scheme with support for arithmetic of approximate numbers. An implementation of this scheme shows the best performance in computation over the real numbers. However, its implementation could not employ a core optimization technique based on the Residue Number System (RNS) decomposition and the Number Theoretic Transformation (NTT).

Reversible and Fragile Watermarking for Medical Images.

Abstract: A novel reversible digital watermarking technique for medical images to achieve high level of secrecy, tamper detection, and blind recovery of the original image is proposed. The technique selects some of the pixels from the host image using chaotic key for embedding a chaotically generated watermark. The rest of the pixels are converted to residues by using the Residue Number System (RNS). The chaotically selected pixels are represented by the polynomial. A primitive polynomial of degree four is chosen that divides the message polynomial and consequently the remainder is obtained. The obtained remainder is XORed with the watermark and appended along with the message. The decoder receives the appended message and divides it by the same primitive polynomial and calculates the remainder. The authenticity of watermark is done based on the remainder that is valid, if it is zero and invalid otherwise. On the other hand, residue is divided with a primitive polynomial of degree 3 and the obtained remainder is appended with residue. The secrecy of proposed system is considerably high. It will be almost impossible for the intruder to find out which pixels are watermarked and which are just residue. Moreover, the proposed system also ensures high security due to four keys used in chaotic map. Effectiveness of the scheme is validated through MATLAB simulations and comparison with a similar technique.

Montgomery reduction within the context of residue number system arithmetic

Abstract: This paper is a survey of Montgomery reduction in the context of residue number system arithmetic. We present the main variants of RNS Montgomery reduction, some efficient embedded hardware implementations, applications in asymmetric cryptography (RSA, ECC, pairing, lattices), to end with the use of RNS against side-channel analysis and fault attacks.

Method to control and correct telemtry well information in the basis of residue number system

Abstract: The paper considers the issue of increasing the reliability of the borehole telemetry information. The issue is suggested to be solved by applying the code of nonpositional residue number system instead of a traditionally used positional number notation to code the information. The residue number system is shown to have the best error-correcting capacities and is able both to detect the errors and correct them. Keywords: oil wells; telemetry information, coding, residue number system, error-correcting capacities, error detection, error correction

Interval Estimation of Relative Values in Residue Number System

Abstract: Residue number system (RNS), due to its carry-free nature, is popular in many applications of high-speed computer arithmetic, especially in digital signal processing and cryptography. However, the main limiting factor of RNS is a high complexity of such operations as magnitude comparison, sign determination and overflow detection. These operations have, for many years, been a major obstacle to more widespread use of parallel residue arithmetic. This paper presents a new efficient method to perform these operations, which is based on computation and analysis of the interval estimation for the relative value of an RNS number. The estimation, which is called the interval floating-point characteristic (IFC), is represented by two directed rounded bounds that are fixed-precision numbers. Generally, the time complexities of serial and parallel computations of IFC are linear and logarithmic functions of the size of the moduli set, respectively. The new method requires only small-integer and fixed-precision float...

Optimization of the FIR Filter Structure in Finite Residue Field Algebra

Abstract: This paper introduces a method for optimizing non-recursive filtering algorithms. A mathematical model of a non-recursive digital filter is proposed and a performance estimation is given. A method for optimizing the structural implementation of the modular digital filter is described. The essence of the optimization is that by using the property of the residue ring and the properties of the symmetric impulse response of the filter, it is possible to obtain a filter having almost a half the length of the impulse response compared to the traditional modular filter. A difference equation is given by calculating the output sample of modules p1 … pn in the modified modular digital filter. The performance of the modular filters was compared with the performance of positional non-recursive filters implemented on a digital signal processor. An example of the estimation of the hardware costs is shown to be required for implementing a modular digital filter with a modified structure. This paper substantiates the expediency of applying the natural redundancy of finite field algebra codes on the example of the possibility to reduce hardware costs by a factor of two. It is demonstrated that the accuracy of data processing in the modular digital filter is higher than the accuracy achieved with the implementation of filters on digital processors. The accuracy advantage of the proposed approach is shown experimentally by the construction of the frequency response of the non-recursive low-pass filters.

A Method for Operational Diagnosis of Data Represented in a Residue Number System

Abstract: Two methods for diagnosing data represented in a residue number system (RNS) are considered. It is shown that the main drawback of these methods is a considerable time of diagnosing RNS-based data. The proposed method makes it possible to reduce the time of diagnosing errors in RNS-based data, which increases the efficiency of diagnosis. The use of the method of operational diagnosis of data increases the overall efficiency, which indicates the expediency of its application in computing systems of nonpositional code structures in RNSs.

Practical Evaluation of Protected Residue Number System Scalar Multiplication

Abstract: The Residue Number System (RNS) arithmetic is gaining grounds in public key cryptography, because it offers fast, efficient and secure implementations over large prime fields or rings of integers. In this paper, we propose a generic, thorough and analytic evaluation approach for protected scalar multiplication implementations with RNS and traditional Side Channel Attack (SCA) countermeasures in an effort to assess the SCA resistance of RNS. This paper constitutes the first robust evaluation of RNS software for Elliptic Curve Cryptography against electromagnetic (EM) side-channel attacks. Four different countermeasures, namely scalar and point randomization, random base permutations and random moduli operation sequence, are implemented and evaluated using the Test Vector Leakage Assessment (TVLA) and template attacks. More specifically, variations of RNS-based Montgomery Powering Ladder scalar multiplication algorithms are evaluated on an ARM Cortex A8 processor using an EM probe for acquisition of the traces. We show experimentally and theoretically that new bounds should be put forward when TVLA evaluations on public key algorithms are performed. On the security of RNS, our data and location dependent template attacks show that even protected implementations are vulnerable to these attacks. A combination of RNS-based countermeasures is the best way to protect against side-channel leakage.

Alternative Redundant Residue Number System Construction with Redundant Residue Representations

Abstract: Residue number system (RNS) is a number representation system that represents a large integer with several smaller integers. Due to its ability to perform addition and multiplication in parallel, RNS is widely used in signal processing, communication, and cryptography. To extend the ability of RNS, redundant residue number system (RRNS), which has abilities to detect and correct errors, is proposed to be used in fault tolerant applications. Currently, there are two major ways to construct RRNS from RNS. This paper proposes an alternative way to do the construction by using redundant residue representations. Our proposed RRNS can perform certain operations more efficiently, for example, backward conversion and error detection, and can also perform a complex RNS operation, namely, comparing the values between two RRNS representations. However, it would have more costs to perform addition and multiplication on our RRNS. We also compare our work to the two previous works, and discuss their advantages and drawbacks. Further investigations are required to improve the performance of the proposed RRNS.

Residue number system arithmetic based on integrated nanophotonics.

Abstract: The residue number system (RNS) enables dimensionality reduction of an arithmetic problem by representing a large number as a set of smaller integers, where the number is decomposed by prime number factorization. These reduced problem sets can then be processed independently and in parallel, thus improving computational efficiency and speed. Here, we show an optical RNS hardware representation based on integrated nanophotonics. The digit-wise shifting in RNS arithmetic is expressed as spatial routing of an optical signal in 2×2 hybrid photonic-plasmonic switches. Here, the residue is represented by spatially shifting the input waveguides relative to the routers’ outputs, where the moduli are represented by the number of waveguides. By cascading the photonic 2×2 switches, we design a photonic RNS adder and a multiplier forming an all-to-all sparse directional network. The advantage of this photonic arithmetic processor is the short (10’s ps) computational execution time given by the optical propagation delay through the integrated nanophotonic router. Furthermore, we show how photonic processing in-the-network leverages the natural parallelism of optics such as wavelength-division-multiplexing in this RNS processor. A key application for such a photonic RNS engine is the functional analysis of convolutional neural networks.

Simultaneous Conversions with the Residue Number System Using Linear Algebra

Abstract: We present an algorithm for simultaneous conversions between a given set of integers and their Residue Number System representations based on linear algebra. We provide a highly optimized implementation of the algorithm that exploits the computational features of modern processors. The main application of our algorithm is matrix multiplication over integers. Our speed-up of the conversions to and from the Residue Number System significantly improves the overall running time of matrix multiplication.

Historical Patterns of Emerging Residue Number System Technologies During the Evolution of Computer Engineering and Digital Signal Processing

Abstract: The mathematical theory of Residue Number System (RNS) arithmetic existed in the mathematical literature for thousands of years, having first been published by Sun Tzu in 100 A.D. In the mid 1900's RNS number theory began to evolve into many engineering applications as the evolution of digital computers began. In recent times RNS arithmetic has again emerged extensively in cryptography, cyber security, machine learning, fault tolerant signal processing, biomedical signal processing, etc. This paper reviews the history of how over many decades RNS arithmetic has emerged into rapidly developing digital signal processing applications to provide efficient DSP solutions.

General modular adder designs for residue number system applications

Abstract: Modular adders are very crucial components in the performance of residue number system-based applications. Most of the work published so far has been restricted to modulo (2 n ± 1) adders or modulo-specific adders. Less work has been dedicated to modulo-generic adders. This work presents new designs for modulo (2 n ± K) adders, where K is any integer in the range of 3 ≤ K <; 2 n-1 . The proposed structure merges two binary adder structures and maximises sharing of components, wherever possible. This merger permits shorter cell-interconnections, which results in space wastage reduction. Additionally, tristate-based multiplexers (MUXs) are used in lieu of the more demanding gate-based MUXs. As examined over a very practical range of n, 7 ≤ n ≤ 15, and based on a 65 nm VLSI realisation, the circuit layouts of the proposed adders outperform considerably the most recent and competitive functionally identical published works. On average, the proposed designs have shown reductions in area, time, power, and energy of 23.7, 13.8, 22.9, and 33.6%, respectively.

Method of operating neural networks, corresponding network, apparatus and computer program product

Abstract: A method of operating neural networks such as convolutional neural networks including e.g. an input layer, an output layer and at least one intermediate layer between the input layer and the output layer, with the network layers including operating units (10) performing arithmetic operations on input data ( a (k-1) , w (k) ) to provide output data ( a (k) ). The method includes: - selecting a set of operating units in the network layers, - performing arithmetic operations in operating units (10) in the selected set of operating units by performing Residue Number System or RNS operations on RNS-converted (12) input data ( a (k-1) , w (k) ) by obtaining RNS output data ( a (k) ) in the Residue Number System, - backward converting (14) from the Residue Number System the RNS output data ( a (k) ) resulting from the RNS operations.

An optimized two-level discrete wavelet implementation using residue number system

Abstract: Using discrete wavelet transform (DWT) in high-speed signal processing applications imposes a high degree of caution to hardware resource availability, latency and power consumption. In this paper, we investigated the design and implementation aspects of a multiplier-free two-level DWT by using residue number system (RNS). The proposed two-level takes the advantage of performing the multiplication operations using only the memory without involving special multiplier units, which preserves valuable resources for other critical tasks within the FPGA. The design was implemented and synthesized in ZYNQ ZC706 development kit, taking advantage of embedded block RAMs (BRAMs). The results of the overall experimentations showed that there is a considerable improve in the proposed two-level DWT design with regard to latency and peak signal-to-noise ratio (PSNR) precision value in the final output.

Adjustment of adaptive digital filter coefficients in modular codes

Abstract: The main advantage of adaptive digital filters is the minimum error of their output response. It is reached by recalculation of values of coefficients of the filter. The conducted researches have shown that the known algorithms of adjustment of coefficients of the adaptive digital filter are inexpedient to be used at their implementation in the RNS codes. The new consecutive algorithm of recalculation of coefficients which application allows to carry out adjustment of coefficients of modular digital filters much quicker, than the existing algorithms is presented in article. At the same time for carrying out recalculation of each coefficient of the modular digital filter it is necessary to execute one operation of subtraction, one operation of multiplication and one transaction of addition of the module, i.e. time of recalculation is proportional to a filter order. Thus, it is obvious that use of the developed algorithm allows to reduce time expenditure in comparison with earlier known algorithms of adaptation.

A pseudo-random sequence generation scheme based on RNS and permutation polynomials

Abstract: Long period pseudo-random sequence plays an important role in modern information processing systems. Base on residue number system (RNS) and permutation polynomials over finite fields, a pseudorandom sequence generation scheme is proposed in this paper. It extends several short period random sequences to a long period pseudo-random sequence by using RNS. The short period random sequences are generated parallel by the iterations of permutation polynomials over finite fields. Due to the small dynamic range of each iterative calculation, the bit width in hardware implementation is reduced. As a result, we can use full look-up table (LUT) architecture to achieve high-speed sequence output. The methods to find proper permutation polynomials to generate long period sequences and the optimization algorithm of Chinese remainder theorem (CRT) mapping are also proposed in this paper. The period of generated pseudorandom sequence can exceed 2100 easily based on common used field programmable gate array (FPGA) chips. Meanwhile, this scheme has extensive freedom in choosing permutation polynomials. For example, 10905 permutation polynomials meet the long period requirement over the finite field F q with q ≢ 1(mod 3) and q ⩽ 503. The hardware implementation architecture is simple and multiplier free. Using Xilinx XC7020 FPGA chip, we implement a sequence generator with the period over 250, which only costs 20 18kb-BRAMs (block RAM) and a small amount of logics. And the speed can reach 449.236 Mbps. The National Institute of Standards and Technology (NIST) test results show that the sequence has good random properties.

Data Flow Oriented Hardware Design of RNS-based Polynomial Multiplication for SHE Acceleration

Abstract: This paper presents a hardware implementation of a Residue Polynomial Multiplier (RPM), designed to accelerate the full Residue Number System (RNS) variant of the Fan-Vercauteren scheme proposed by Bajard et al. [BEHZ16]. Our design speeds up polynomial multiplication via a Negative Wrapped Convolution (NWC) which locally computes the required RNS channel dependent twiddle factors. Compared to related works, this design is more versatile regarding the addressable parameter sets for the BFV scheme. This is mainly brought by our proposed twiddle factor generator that makes the design BRAM utilization independent of the RNS basis size, with a negligible communication bandwidth usage for non-payload data. Furthermore, the generalization of a DFT hardware generator is explored in order to generate RNS friendly NTT architectures. This approach helps us to validate our RPM design over parameter sets from the work of Halevi et al. [HPS18]. For the depth-20 setting, we achieve an estimated speed up for the residue polynomial multiplications greater than 76 during ciphertexts multiplication, and greater than 16 during relinearization. It thus results in a single-threaded Mult&Relin ciphertext operation in 109.4 ms (×3.19 faster than [HPS18]) with RPM counting for less than 15% of the new computation time. Our RPM design scales up with reasonable use of hardware resources and realistic bandwidth requirements. It can also be exploited for other RNS based implementations of RLWE cryptosystems.

High Performance Parallel Computing in Residue Number System

Abstract: Residue Number System (RNS) allows performing computation more efficiently. Natural parallelism of representation and processing of numbers makes this number system suitable for applying to high performance computing. We address the main features of application of RNS to high-performance parallel computing. We consider and analyze different stages of data processing in RNS. Based on this analysis, we describe the process of decomposition of algorithms using RNS

Security analysis of homomorphic encryption scheme for cloud computing: Known-plaintext attack

Abstract: We consider cryptosystems for homomorphic encryption schemes based on the Residue Number System (RNS) and Secret Sharing Schemes. One of their disadvantages is that they are directly related to data redundancy, and hence, increasing the size of the storage. To minimize it, homophonic encryption can be combined with the arithmetic coding known as Chinese remainder theorem. We describe a new method of cryptanalysis based on a property of RNS and theory of numbers. We prove that an attacker needs only η · [log 2 log 2 (k · p n )l arbitrary generated input files that form the “known-plaintext”, where p i is moduli RNS, to calculate the secret key required to decrypt the entire data.

Area-Efficient FPGA Implementation of Minimalistic Convolutional Neural Network Using Residue Number System

Abstract: Convolutional Neural Networks (CNN) is the promising tool for solving task of image recognition in computer vision systems. However, the most known implementation of CNNs require a significant amount of memory for storing weights in training and work. To reduce the resource costs of CNN implementation we propose the architecture that separated on hardware and software parts for performance optimization. Also we propose to use Residue Number System (RNS) arithmetic in the hardware part which implements the convolutional layer of CNN. Software simulation using Matlab 2017b shows that CNN with a minimum number of layers can be quickly and successfully trained. Hardware simulation using FPGA Kintex7 xc7k70tfbg484-2 demonstrates that using RNS in convolutional layer of CNN allows to reduce hardware costs by 32% compared with the traditional approach based on the binary number system.

RNS-to-Binary Converters for New Three-Moduli Sets {2k - 3, 2k - 2, 2k - 1} and {2k + 1, 2k + 2, 2k + 3}

Abstract: In this paper, mixed radix conversion (MRC)-based residue number system (RNS)-to-binary converters for two new three-moduli sets {2k−3, 2k−2, 2k−1} and {2k+1, 2k+2, 2k+3} which are derived from the...

65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography

Abstract: Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic-curve cryptography (ECC) and Rivest-Shamir-Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue number system (RNS). Moreover, a 40-channel RNS moduli-set is proposed for this architecture to benefit from the short-channel width of the RNS moduli-set. The throughput of the architecture is enhanced by pipelining and pre-computations. The proposed architecture is fabricated as an ASIC using 65-nm CMOS technology. The measurement results are obtained for energy dissipation at different voltage levels from 0.43 to 1.25 V. The maximum throughput of the proposed design is 1037 Mbps while operating at a frequency of 162 MHz with an energy dissipation of 48 nJ. The proposed architecture enables the construction of low-voltage and energy-efficient ECCs.

Analysis and Design of Residue Number System Based Building Blocks

Abstract: This paper deals with designing of RNS (Residue Number System) based building blocks for applications in digital signal processing. RNS provides parallel, carry free operations and since it deals with small numbers hence it is faster than other conventional methods. RNS based processing is performed in three stages namely Forward Conversion (FC), Modular Operations, and Reverse Conversion (RC). This paper is aimed at designing and analysis of efficient blocks in terms of area, delay and power for special moduli-set {2n−1, 2n, 2n+1} using std_cell at 32/28 nm technology.Modification is done in earlier proposed architecture of Forward Converter for making it work for all valid combination of input data. In all basic blocks, binary adder is main component. Verilog HDL is used to design different blocks. Synopsys design compiler is used for area, power and delay calculation at 32/28 nm technology. It is observed that CSA (Carry Select Adder) based reverse converter is approximately 20% faster as compared to that based on RCA (Ripple Carry Adder). Also we have compared LUT based design of two different types of reverse converter namely CRT (Chinese Reminder Theorem) and MRC (Mixed Radix Converter).

Power Side Channel Resistance of RNS Secure Logic

Abstract: Over the last decade, significant research effort has gone into secret sharing schemes to secure cryptographic implementations to thwart power side-channel attacks. Higher-order side-channel attacks can correlate the behavior of multiple shares of a bit that leads to learningthe bit state. This violates the power side-channel privacy of cryptographic logic families such as t-privatelogic. The only recourse is to increase the number of secret shares t, which results in excessive hardware (quadratic in t) needs in area, energy and time for providing the desired level of security. In this paper, we present a new secure logic family based on secret sharing concepts using a residue number system. This technique maps the input from binary space into multiple un-correlated shares in the residue domain. These shares are processed independently in independent hardware lanes. The results are decoded back to binary space using the Chinese Remainder theorem. This technique increases the computational complexity for a side channel adversary through proper selection of random mask and residual moduli-which increase both side-channel privacy and cryptographic privacy. Further, we implemented the secure RNS logic and computed the SCA metrics. Finally, we evaluated the power SCA resistance using ML-classifiers. The results show that our RNS secure logic provides better resistance against power side-channel attacks both in terms of power distribution uniformity and success rates of power side channel attack root kits.

FPGA Implementation of Modular Multiplier in Residue Number System

Abstract: This work presents a description of a highperformance hardware implementation of a Montgomery modular multiplier using a residue number system (RNS). An RNS can be considered as self-defense against simple power analysis (SPA) and differential power analysis (DPA) attacks, and can be used for public-key cryptography, such as the Rivest, Shamir and Adleman (RSA) cryptosystem and elliptic curve cryptosystems (ECC). Various kinds of security are required for Big Data analysis. The proposed RNS-based modular multiplier is suitable for public-key cryptography that can be used for Big Data security. It is implemented on field-programmable gate-array (FPGA) technology and optimized by trying different variants of the Montgomery Algorithm on it. The proposed RNS-based modular multiplication takes only 22 ns on the Xilinx Virtex-II FPGA. In addition, it needs relatively few resources on the FPGA, needing only 68 slices.

An Exploration of FPGA based Multilayer Perceptron using Residue Number System for Space Applications

Abstract: In recent times, most satellite applications consist of complex and computationally intensive data processing systems. The challenge is to meet the demands of onboard processing while keeping the power consumption at a minimum. In this paper, we explore the scope of an FPGA based neural network using Residue Number System for space-based applications. We propose an implementation that uses RNS arithmetic to exploit the parallelism present in neural networks for faster computations thus meeting onboard processing demands of satellites without the use of high powered CPUs or GPUs.