Showing papers on "Sense amplifier published in 1998"

Power control system for synchronous memory device

Abstract: A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.

Programmable logic array integrated circuit incorporating a first-in first-out memory

Abstract: A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.

Non-volatile data storage unit and method of controlling same

Abstract: A non-volatile data storage unit having a data input and a volatile memory device for storing data. The volatile memory device is preferably a latch circuit made up of a pair of cross-coupled inverter circuits which store the data in complementary form. A non-volatile memory device, such as a pair of flash memory cells, is included which also store data in complementary form. Control circuitry is provided for controlling the operation of the data storage unit, including circuitry for transferring data from the data input to the volatile memory device and circuitry for programming the non-volatile memory device with data from the volatile memory device. The storage unit also preferably includes circuitry for transferring data stored in the non-volatile memory device to the volatile memory device, with such transfer typically taking place after an interruption of power to the storage unit.

Nonvolatile semiconductor memory device with soft-programming to adjust erased state of memory cells

Abstract: A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data "0" can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

Memory module system having multiple memory modules

Abstract: There are provided a memory controller, a plurality of memory modules, and an external data bus common to the plurality of memory modules. The plurality of memory modules each include a plurality of memory chips, a plurality of internal data buses connected between a corresponding memory chip and an input/output terminal, a logic chip, and a plurality of switch transistors each connected between a corresponding internal data bus and a corresponding input/output terminal to turn on/off in response to a control signal from the logic chip. The plurality of switch transistors in a memory module selected by the memory controller are turned on, and the plurality of switch transistors in the memory modules other than the selected memory module are turned off. Thus, the capacity of the memory modules may be increased while maintaining high-speed data transfer.

Method and apparatus for implementing multiple memory buses on a memory module

Abstract: A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.

Using FET switches for large memory arrays

Abstract: The present invention discloses a method and apparatus for interfacing a memory array to a memory controller using a field-effect transistor (FET) switch. The memory controller has a bus which comprises a plurality of signal lines. The memory array is coupled to the memory controller. The memory array is divided into N groups of memory devices; each group has K memory devices. K memory devices in each of the N groups share memory signal lines. The FET switch couples the bus to one of the N groups of the shared memory signal lines at different times in response to a switch control indication.

Ferroelectric memory using ferroelectric reference cells

Abstract: A random access memory circuit is described which uses single ferroelectric memory cells to store data. The ferroelectric memory cells can be selectively read using reference cells to generate a reference voltage which is compared to a voltage representative of data stored on the memory cell using a multiplexed sense amplifier. In using two ferroelectric reference cells in which one contains a logical 0 polarization, and the other contains a logical 1 polarization, a single-ended reference voltage can be generated on a reference bit line. A ferroelectric memory cell can then be read by comparing the voltage on its corresponding bit line to the reference bit line using the sense amplifier. The content of the memory cell being read and the content of the reference cells can be rewritten on the same clock cycles to save on access time.

Method and apparatus for testing an integrated memory device

Abstract: A method of memory array testing that detects defects which are sensitive to environmental conditions. A repair signature is generated reflecting the repair state of the memory. A memory device is rejected if there is a change in the repair signature of the memory array over the operating range of the device. In one embodiment, an integrated circuit includes a memory array, spare memory elements for repairing defective locations of the memory array, a built-in self-test (BIST) circuit for detecting faults in the memory array, a built-in self-repair (BISR) circuit for causing the failed memory location of the memory array to be replaced with a spare memory element, and a signature generator where the signature is based on a compression of addresses corresponding to failed memory locations, wherein the signature is used to determine that a repair result of the memory array is invariant over different environmental conditions.

Memory device and system including a low power interface

Abstract: A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.

Reducing power consumption in computer memory

Abstract: A computer system comprising an input/output device, a processor, a memory device, and a bridge logic device for interfacing the memory device to the processor and input/output device incorporates a refresh logic device for generating a memory refresh signal during suspend mode. Because the rate at which memory must be refreshed generally depends on the temperature of the memory device, the refresh logic varies the frequency of the refresh signal according to the temperature of the memory device, resulting in substantial power savings. In a preferred embodiment, the refresh logic uses a normal-rate refresh signal at the beginning of suspend mode and incrementally steps down the refresh rate as the memory temperature decreases. In other embodiments, the refresh logic incorporates a signal generator which produces a refresh signal at a frequency that varies according the output voltage from a temperature sensor or the temperature-sensitive resistance of a thermistor. In yet another embodiment, a variable-rate refresh logic is incorporated into the memory device, resulting in a self-refreshing memory module.

High performance cost optimized memory with delayed memory writes

Abstract: A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.

Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof

Abstract: A semiconductor memory device which is applicable not only to a cache system but to the field of graphic processing is provided. The semiconductor memory device includes a DRAM portion, an SRAM portion and a bidirectional data transfer circuit 106 which carries out data transfer between a DRAM array included in the DRAM portion and an SRAM array included in the SRAM portion as well as data input/output with the outside of the device. Driving of the DRAM array and data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by a DRAM control circuit. Driving of the SRAM array, data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input/output operation are controlled by the SRAM control circuit. The address to the DRAM array is applied to a DRAM array buffer 108, while an address for selecting a memory cell in the SRAM array is applied to the SRAM address buffer.

Semiconductor device and electronic equipment having a non-volatile memory with a security function

Abstract: A semiconductor device which can be re-used even if the read protection is set for a non-volatile memory included therein, and electronic equipment including such a semiconductor device. The data written in a memory cell array is protected from being read out from the outside for security. Only when erase of all data in the memory cell array is detected, the read protection is released. Thus, a microcomputer can be refused. The detection with respect to whether or not all data has been erased can be accomplished through execution of a flash erase operation or by reading out all address data. A read protection control circuit includes an EEPROM for storing information that the read protection is enabled. A plurality of such EEPROM's are used. If the read protection for the memory cell array is enabled, the erase/write to the EEPROM's are inhibited. The memory cell array is controlled separately from the EEPROM's. In the normal operation mode, the read-out of data by CPU is permitted. Such a configuration may be applied to a semiconductor device including a gate array block.

Method for programming a non-volatile memory device with program disturb control

Abstract: There is provided a non-volatile memory device programming method for improving soft programming. In the programming method, a first voltage for program inhibition is applied to a bit line, and a second voltage is applied to the gate of a first select transistor, unselected word lines, and a selected word line. Then, after blocking a current path, a third voltage is applied to the word line of a first unselected memory cell and the word line of a second unselected memory cell sharing the drain and the source of a memory cell on the selected word line in order to decouple the first and second unselected memory cells from the other unselected memory cells. A fourth voltage is applied to the unselected word lines except for the first and second unselected memory cells, thereby coupling the sources or drains of the first and second unselected memory cells and disconnecting the channel of the selected memory cell from those of the other unselected memory cells. Then, a program voltage is applied to the selected word line.

Programmable logic array device with random access memory configurable as product terms

Abstract: A look-up-table-based programmable logic device is provided with memory circuitry which can be operated either as random access memory ("RAM") or to perform product term ("p-term") logic. Each individual row of the memory is separately addressable for writing data to the memory or, in RAM mode, for reading data from the memory. Alternatively, multiple rows of the memory are addressable in parallel to read p-terms from the memory. The memory circuitry of the invention is particularly useful as an addition to look-up-table-type programmable logic devices because the p-term capability of the memory circuitry provides an efficient way to perform wide fan-in logic functions which would otherwise require trees of multiple look-up tables.

Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain

Abstract: A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.

Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array having plural electrically erasable memory cells including a gate, a source, a drain, and an electric charge accumulation layer each disposed in a matrix form. A data writing section writes data into memory cells in this memory cell array. A data reading section reads out data in memory cells of the memory cell array. A data erasing section erases data in memory cells of the memory cell array. A control section controls, when applying a first signal to the gate in a specified memory inhibited of writing and applying a second signal to a node capacitively coupled to at least one of source and drain, in writing data into the memory cells, so that the second signal may fall later than the first signal.

Method and apparatus for enhancing the performance of semiconductor memory devices

Abstract: A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.

A method and apparatus for hardware block locking in a nonvolatile memory

Abstract: The memory device (200) includes a nonvolatile memory array (215) including a first block of memory cells (230). The first volatile protection bit coupled to the first block is programmable to prevent a memory access operation directed to the first block from being performed.

Dram core refresh with reduced spike current

Abstract: A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.

A ferroelectric dynamic random access memory

Abstract: A memory including an array of memory cells (20), each of which includes a ferroelectric field effect transistor (FET) as its memory element; and sense and refresh circuitry (32) connected to the array of memory cells to read stored data within each cell by sensing source-to-drain conductivity of the ferroelectric transistor and to refresh the stored data.

Memory module with flexible serial presence detect configuration

Abstract: The invention comprises a in line memory module which includes connections on its surface so that either a standard Electrically Erasable Programmable Read Only Memory (EEPROM), or a "daisy chain" EEPROM can be utilized with the memory module.

High-density chain ferroelectric random access memory (chain FRAM)

Abstract: A new chain ferroelectric random access memory-a chain FRAM-has been proposed. A memory cell consists of parallel connection of one transistor and one ferroelectric capacitor, and one memory cell block consists of plural memory cells connected in series and a block selecting transistor. This configuration realizes the smallest 4 F/sup 2/ size memory cell using the planar transistor so far reported, and random access. The chip size of the proposed chain FRAM can be reduced to 63% of that of the conventional FRAM when 16 cells are connected in series. The fast nondriven half-V/sub dd/ cell-plate scheme, as well as the driven cell-plate scheme, are applicable to the chain FRAM without polarization switching during the standby cycle thanks to short-circuiting ferroelectric capacitors. It results in fast access time of 45 ns and cycle time of 70 ns without refresh operation.

Memory controller architecture

Abstract: An apparatus for providing a number of ports with burst access to a DRAM array includes a memory array, a controller for controlling the memory array, a write device for writing to the memory array, a read device for reading from the memory array, a FIFO output buffer for temporarily storing data read from the memory array and/or a FIFO input buffer for temporarily storing data prior to writing to the memory array.

A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM

Abstract: An ultrahigh-speed 4.5-Mb CMOS SRAM with 1.8-ns clock-access time, 1.8-ns cycle time, and 9.84-/spl mu/m/sup 2/ memory cells has been developed using 0.25-/spl mu/m CMOS technology. Three key circuit techniques for achieving this high speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array. The proposed decoder can reduce the delay time between the address input and the word-line signal of the 4.5-Mb SRAM to 68% of that of an SRAM with conventional circuits. The sense amplifier with nMOS source followers can reduce not only the delay time of the sense amplifier but also the power dissipation. In the SRAM, the sense-amplifier activation pulse must be input into the sense amplifier after the signal from the memory cell is input into the sense amplifier. A large timing margin required between these signals results in a large access time in the conventional SRAM. The sense-amplifier activation pulse generator that uses a duplicate memory-cell array can reduce the required timing margin to less than half of the conventional margin. These three techniques are especially useful for realizing ultrahigh-speed SRAM's, which will be used as on-chip or off-chip cache memories in processor systems.

Multiple transistor dynamic random access memory array architecture with simultaneous refresh of multiple memory cells during a read operation

Abstract: A four transistor dynamic memory cell architecture and refresh technique which allows for cell refresh to occur during a read operation. The access and memory transistors of the individual memory cells are fabricated with a relative width-to-length ratio such that it is sufficient to merely activate the associated word line to perform the refresh operation. This is accomplished without activating the read sense amplifier resulting in lower power consumption and the retention of most recently read data. Multiple word lines may be activated concurrently utilizing the technique disclosed to further reduce the refresh rate overhead in a memory array and increase the overall memory array bandwidth.

Pipelined dual port integrated circuit memory

Abstract: A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells, where each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) compares addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

Power consumption reduction in medical devices by employing different supply voltages

Abstract: Power consumption in medical devices is reduced through the application of different supply voltages to analog and digital circuits, respectively. The medical device generally includes analog circuits (e.g., an atrial sense amplifier, a ventricular sense amplifier, a T-wave amplifier, bandpass filters, detection circuits, sensor amplification circuits, physiological signal amplification circuits, output circuits, a battery monitor circuit, and a power on reset circuit) and digital circuits (e.g., a processor, a controller, and a memory) with the supply voltage applied to the analog circuits being greater than that applied to the digital circuits. A source applies a first fixed supply voltage to the digital circuits of the medical device and a voltage generation circuit (e.g., a charge pump circuit) having the first fixed supply voltage applied thereto is used for generating a second fixed supply voltage to be applied to analog circuits of the medical device.

Dynamic write process for high bandwidth multi-bit-per-cell and analog/multi-level non-volatile memories

Abstract: A write process and circuit for a non-volatile memory such as a multi-bit-per-cell Flash memory has multiple local memory arrays and a global bias circuit that charges row lines in the arrays for programming operations. A programming operation in an array includes a charging period during which the global bias circuit charges a selected row line to a voltage corresponding to a value to be written in a memory cell and a sequence of program cycles and verify cycles during which the selected row line is isolated to preserve the charge from the bias circuit. A global control circuit can use a capacitive coupling to the charged row line to raise and lower the row line voltage. In one embodiment, the row line voltage rises to a programming voltage to change the threshold voltage of the selected cell during program cycles and falls to a verify voltage during verify cycles to sense whether the selected cell has a target threshold voltage. Alternatively, the row line voltage remains constant as charged by the bias circuit if a maximum current for biasing a column line connected to a sense amplifier causes the programming voltage to be equal to the trip point of the sense amplifier when the memory cell has the target threshold voltage.