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Showing papers on "Serialization published in 2010"


Journal ArticleDOI
TL;DR: This document presents a model of nanopublications along with a Named Graph/RDF serialization of the model and discusses the importance of aggregating nanopublication and the role that the Concept Wiki plays in facilitating it.
Abstract: As the amount of scholarly communication increases, it is increasingly difficult for specific core scientific statements to be found, connected and curated. Additionally, the redundancy of these statements in multiple fora makes it difficult to determine attribution, quality and provenance. To tackle these challenges, the Concept Web Alliance has promoted the notion of nanopublications (core scientific statements with associated context). In this document, we present a model of nanopublications along with a Named Graph/RDF serialization of the model. Importantly, the serialization is defined completely using already existing community-developed technologies. Finally, we discuss the importance of aggregating nanopublications and the role that the Concept Wiki plays in facilitating it.

317 citations


Journal ArticleDOI
13 Mar 2010
TL;DR: This work develops a compiler and runtime system that runs arbitrary multithreaded C/C++ POSIX Threads programs deterministically but resorts to serialization rarely, for handling interthread communication and synchronization.
Abstract: The behavior of a multithreaded program does not depend only on its inputs. Scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in the execution of multithreaded programs. This severely complicates many tasks, including debugging, testing, and automatic replication. In this work, we avoid these complications by eliminating their root cause: we develop a compiler and runtime system that runs arbitrary multithreaded C/C++ POSIX Threads programs deterministically. A trivial non-performant approach to providing determinism is simply deterministically serializing execution. Instead, we present a compiler and runtime infrastructure that ensures determinism but resorts to serialization rarely, for handling interthread communication and synchronization. We develop two basic approaches, both of which are largely dynamic with performance improved by some static compiler optimizations. First, an ownership-based approach detects interthread communication via an evolving table that tracks ownership of memory regions by threads. Second, a buffering approach uses versioned memory and employs a deterministic commit protocol to make changes visible to other threads. While buffering has larger single-threaded overhead than ownership, it tends to scale better (serializing less often). A hybrid system sometimes performs and scales better than either approach individually. Our implementation is based on the LLVM compiler infrastructure. It needs neither programmer annotations nor special hardware. Our empirical evaluation uses the PARSEC and SPLASH2 benchmarks and shows that our approach scales comparably to nondeterministic execution.

233 citations


Patent
21 Jun 2010
TL;DR: In this article, a smartphone and encoder are used for commissioning RFID transponders with unique object class instance numbers without requiring a realtime connection to a serialization database.
Abstract: In one embodiment the present invention comprises a smartphone and encoders for commissioning RFID transponders. The present invention further includes novel systems, devices, and methods for commissioning RFID transponders with unique object class instance numbers without requiring a realtime connection to a serialization database.

89 citations


Patent
12 Jul 2010
TL;DR: In this paper, a serialization service module is provided for configuring an asset management system to provide a secure means of generating, assigning to chips (or other electronic objects or devices), and tracking unique serial numbers.
Abstract: A serialization service module is provided for configuring an asset management system to provide a secure means of generating, assigning to chips (or other electronic objects or devices), and tracking unique serial numbers. To provide this service, a controller is used to define a product model, then to define one or more serialization schemas to be bound to each product model. Each serialization schema contains a range of serial numbers for a particular product. The serial number schemas are sent over a secure, encrypted connection to appliances at the manufacturer's location. Agents can then request serial number values by product name. The serial numbers are generated by the appliance, metered, and provided to the agents. The serial numbers are then injected sequentially into each die in a chip manufacturing process using the agent.

82 citations


Patent
17 Aug 2010
TL;DR: The watermark can be formed by ink-jet printing, or otherwise, and can be used for various purposes, including authenticating the document as an original, linking to associated on-line resources and distinguishing seemingly-identical versions of the same document (document serialization) as discussed by the authors.
Abstract: Stationery, or other printable media, is encoded with a digital watermark. The watermark is not conspicuous to a human observer of the media, yet conveys plural bits of auxiliary information when optically scanned and digitally processed. The watermark can be formed by ink-jet printing, or otherwise. The encoded information can be used for various purposes, including authenticating the document as an original, linking to associated on-line resources, and distinguishing seemingly-identical versions of the same document (document serialization).

51 citations


Proceedings ArticleDOI
05 Jul 2010
TL;DR: The Tantivy middleware layer reduces the volume of data transmitted without semantic interpretation of service requests or responses and thus improves the service response time and the use of aspect-oriented programming techniques provides modularity and transparency in the implementation.
Abstract: Web Services communicate through XML-encoded messages and suffer from substantial overhead due to verbose encoding of transferred messages and extensive (de)serialization at the end-points. We demonstrate that response caching is an effective approach to reduce Internet latency and server load. Our Tantivy middleware layer reduces the volume of data transmitted without semantic interpretation of service requests or responses and thus improves the service response time. Tantivy achieves this reduction through the combined use of caching of recent responses and data compression techniques to decrease the data representation size. These benefits do not compromise the strict consistency semantics. Tantivy also decreases the overhead of message parsing via storage of application-level data objects rather than XML-representations. Furthermore, we demonstrate how the use of aspect-oriented programming techniques provides modularity and transparency in the implementation. Experimental evaluations based on the WSTest benchmark suite demonstrate that our Tantivy system gives significant performance improvements compared to non-caching techniques.

37 citations


Proceedings ArticleDOI
15 Jul 2010
TL;DR: AGGRO as discussed by the authors is an innovative Optimistic Atomic Broadcast-based (OAB) active replication protocol that aims at maximizing the overlap between communication and processing through a novel AGGRessively Optimistic concurrency control scheme.
Abstract: Software Transactional Memories (STMs) are emerging as a potentially disruptive programming model. In this paper we are address the issue of how to enhance dependability of STM systems via replication. In particular we present AGGRO, an innovative Optimistic Atomic Broadcast-based (OAB) active replication protocol that aims at maximizing the overlap between communication and processing through a novel AGGRessively Optimistic concurrency control scheme. The key idea underlying AGGRO is to propagate dependencies across uncommitted transactions in a controlled manner, namely according to a serialization order compliant with the optimistic message delivery order provided by the OAB service. Another relevant distinguishing feature of AGGRO is of not requiring a-priori knowledge about read/write sets of transactions, but rather to detect and handle conflicts dynamically, i.e. as soon (and only if) they materialize. Based on a detailed simulation study we show the striking performance gains achievable by AGGRO (up to 6x increase of the maximum sustainable throughput, and 75% response time reduction) compared to literature approaches for active replication of transactional systems.

36 citations


Proceedings ArticleDOI
06 Jun 2010
TL;DR: This paper provides infrastructure that allows multiple threads on a multi-core machine to concurrently perform read and write operations on shared data structures, automatically mitigating hotspots and other performance hazards.
Abstract: To take full advantage of the parallelism offered by a multi-core machine, one must write parallel code. Writing parallel code is difficult. Even when one writes correct code, there are numerous performance pitfalls. For example, an unrecognized data hotspot could mean that all threads effectively serialize their access to the hotspot, and throughput is dramatically reduced. Previous work has demonstrated that database operations suffer from such hotspots when naively implemented to run in parallel on a multi-core processor. In this paper, we aim to provide a generic framework for performing certain kinds of concurrent database operations in parallel. The formalism is similar to user-defined aggregates and Google's MapReduce in that users specify certain functions for parts of the computation that need to be performed over large volumes of data. We provide infrastructure that allows multiple threads on a multi-core machine to concurrently perform read and write operations on shared data structures, automatically mitigating hotspots and other performance hazards. Our goal is not to squeeze the last drop of performance out of a particular platform. Rather, we aim to provide a framework within which a programmer can, without detailed knowledge of concurrent and parallel programming, develop code that efficiently utilizes a multi-core machine.

30 citations


Proceedings ArticleDOI
17 Oct 2010
TL;DR: The design and implementation of Co-Located Runtime Sharing (CoLoRS) is presented, a system that enables cross-language, cross-runtime type-safe, transparent shared memory and RPC over CoLoRS significantly improves both communication throughput and latency by avoiding data structure serialization.
Abstract: As software becomes increasingly complex and difficult to analyze, it is more and more common for developers to use high-level, type-safe, object-oriented (OO) programming languages and to architect systems that comprise multiple components. Different components are often implemented in different programming languages. In state-of-the-art multicomponent, multi-language systems, cross-component communication relies on remote procedure calls (RPC) and message passing. As components are increasingly co-located on the same physical machine to ensure high utilization of multi-core systems, there is a growing potential for using shared memory for cross-language cross-runtime communication.We present the design and implementation of Co-Located Runtime Sharing (CoLoRS), a system that enables cross-language, cross-runtime type-safe, transparent shared memory. CoLoRS provides object sharing for co-located OO runtimes for both static and dynamic languages. CoLoRS defines a language-neutral object/classmodel,which is a static-dynamic hybrid and enables class evolution while maintaining the space/time efficiency of a static model. CoLoRS uses type mapping and class versioning to transparently map shared types to private types. CoLoRS also contributes a synchronization mechanism and a parallel, concurrent, on-the-fly GC algorithm, both designed to facilitate cross-language cross-runtime object sharing.We implement CoLoRS in open-source, production-quality runtimes for Python and Java. Our empirical evaluation shows that CoLoRS extensions impose low overhead. We also investigate RPC over CoLoRS and find that using shared memory to implement co-located RPC significantly improves both communication throughput and latency by avoiding data structure serialization.

22 citations


Patent
Lisa C. Heller1
08 Nov 2010
TL;DR: In this paper, a system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources, including a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock.
Abstract: A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock.

19 citations


Patent
08 Dec 2010
TL;DR: In this paper, a system and method optimizes hardware description code generated from a graphical program or model automatically, including a streaming optimizer, and a delay balancing engine, is presented.
Abstract: A system and method optimizes hardware description code generated from a graphical program or model automatically. The system may include a streaming optimizer, and a delay balancing engine. The streaming optimizer transforms one or more vector data paths in the source model to scalar data paths or to a smaller-sized vector data paths. The streaming optimizer may also configure portions of the modified model to execute at a faster rate. The delay balancing engine may examine the modified model to determine whether any delays or latencies have been introduced. If so, the delay balancing engine may insert one or more blocks into the modified model to correct for any data path misalignment caused by the introduction of the delays or latencies. A validation model, a report, or hardware description code that utilizes fewer hardware resources may be generated from the modified model.

01 Jan 2010
TL;DR: This work proposes optical tokens as a way to manage coordination while coping with repeater inefficiencies, and simplifies protocols by serializing potential races before they issue to the interconnect, called Atomic Coherence.
Abstract: Many have advocated silicon-based nanophotonics for future many-core data communication. It is my goal to show its applicability to other many-core needs, namely many-core coordination. The same optical properties that benefit data communication may benefit many-core coordination: low cross-chip latencies, high bandwidth, and low power consumption. However, to take full advantage of these benefits, it will be necessary to accommodate the technology's limitations. One limiter is repeater inefficiency. Converting an optical signal to and from the electrical domain is relatively slow and also power-inefficient. Thus, it is in the interest of performance to keep the signal in optical form from source to destination. I propose optical tokens as a way to manage coordination while coping with repeater inefficiencies. In most cases, our optical tokens can be passed from any interested party to any other interested party with no repeats, thus allowing for flexible communication at the speed-of-light propagation. When a token is viewed as usage rights for a resource, it becomes a fast traveling mutex. I show two applications of optical tokens. The first application employs optical tokens in the arbiters of an optical data interconnect. The data interconnect is fast and requires fast arbitration for high utilization. Also, like the optical tokens, it avoids repeating data transmissions. These complimentary repeater-less designs allow a token to maintain pace with its associated bandwidth allocation and achieve very high utilization. I further extend the proposal to support flow control and fairness. The second application employs optical tokens to address cache coherence protocol complexity. Cache coherence protocol complexity arises from the presence of concurrency races, which though rare, must be detected and resolved. My proposal, called Atomic Coherence, simplifies protocols by serializing potential races before they issue to the interconnect. Without races, sophisticated protocols are substantially easier to design, debug, and validate. Race serialization comes at some cost to performance, but is kept to a minimum with low-latency optical tokens.

Book ChapterDOI
20 Mar 2010
TL;DR: This paper proposes an inversion framework that is grammar-based inversion, where a program is associated with an unambiguous grammar describing the range of the program, while the complexity is related to how efficient an inverse can be obtained.
Abstract: Program inversion has many applications such as in the implementation of serialization/deserialization and in providing support for redo/undo, and has been studied by many researchers. However, little attention has been paid to two problems: how to characterize programs that are easy or hard to invert and whether, for each class of programs, efficient inverses can be obtained. In this paper, we propose an inversion framework that we call grammar-based inversion, where a program is associated with an unambiguous grammar describing the range of the program. The complexity of the grammar indicates how hard it is to invert the program, while the complexity is related to how efficient an inverse can be obtained.

Journal ArticleDOI
TL;DR: This paper proposes a low‐power bus serialization method that encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized.
Abstract: One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.

Journal ArticleDOI
TL;DR: The HepML format and a corresponding C++ library developed for keeping complete description of parton level events in a unified and flexible form are described and an extension of the format for keeping additional information available in generators is proposed.

Patent
24 Apr 2010
TL;DR: In this paper, a binary data transfer system is described to transfer data from data source to data destination, where the system partitions placement and type data from binary data to be transferred as independent data streams and retains binary format of data source including type information, padding information and endian information for the network transfer.
Abstract: A binary data transfer system is described to transfer data from data source ( 31 ) to data destination ( 32 ). The system partitions placement and type data from binary data to be transferred as independent data streams and retains binary format of data source ( 31 ) including type information, padding information and endian information for the network transfer. This eliminates data parsing overheads at a data source ( 31 ) and reduces data parsing overheads required at a data destination ( 32 ). In this system, data destination ( 32 ) decodes transferred binary data using software code ( 47 ) transferred from data source ( 31 ). This transferred software code ( 47 ) optionally decodes base sixty four encoding and uses the type information, padding information and endian information to extract data from binary data stream at data destination ( 32 ). This system is applicable to any binary data transfer system between any data source and destination like a web browser client that accesses a server on the web. Hence combining native data format of a data source ( 31 ) along with transfer of software code to decode and encode such data at data destination ( 32 ), eliminates processing overheads at server and reduces processing overheads at client.

Patent
26 Mar 2010
TL;DR: In this paper, the authors present a replication solution for managing access to resources shared among multiple processes within a computer system, where multiple program instances of an application are almost simultaneously executed on multiple processors for fault tolerance.
Abstract: Managing access to resources shared among multiple processes within a computer system Multiple program instances of an application are almost simultaneously executed on multiple processors for fault tolerance The replication solution supports the recording and subsequent replay of reservation events granting the shared resources exclusive access rights to the processes, when one program code instruction may request access to a set of shared resources in a non-deterministic order

Proceedings ArticleDOI
09 Jan 2010
TL;DR: A new strategy for compiler-generated locking is presented that uses data structure knowledge to facilitate more precise alias and lock generation analyses and reduce unnecessary serialization, and indicates that compiler knowledge of data structures improves the effectiveness of compiler analysis.
Abstract: To achieve high-performance on multicore systems, sharedmemory parallel languages must efficiently implement atomic operations. The commonly used and studied paradigms for atomicity are fine-grained locking, which is both difficult to program and error-prone; optimistic software transactions, which require substantial overhead to detect and recover from atomicity violations; and compiler-generation of locks from programmer-specified atomic sections, which leads to serialization whenever imprecise pointer analysis suggests the mere possibility of a conflicting operation. This paper presents a new strategy for compiler-generated locking that uses data structure knowledge to facilitate more precise alias and lock generation analyses and reduce unnecessary serialization. Implementing and evaluating these ideas in the Java language shows that the new strategy achieves eight-thread speedups of 0.83 to 5.9 for the five STAMP benchmarks studied, outperforming software transactions on all but one benchmark, and nearly matching programmer-specified fine-grained locks on all but one benchmark. The results also indicate that compiler knowledge of data structures improves the effectiveness of compiler analysis, boosting eight-thread performance by up to 300%. Further, the new analysis allows for software support of strong atomicity with less than 1% overhead for two benchmarks and less than 20% for three others.The strategy also nearly matches the performance of programmer-specified fine-grained locks for the SPECjbb2000 benchmark, which has traditionally not been amenable to static analyses.

Patent
David J. Seager1, Martin J. Smithson1
12 Jan 2010
TL;DR: In this paper, an ordered sequence of two or more facet providers is associated and each is configured to select successive subsets of data in a registry via a database upon a user request to create and configure a faceted selection.
Abstract: An ordered sequence of two or more facet provider objects are associated and each is configured to select successive subsets of data in a registry via a database upon a user request to create and configure a faceted selection. Upon a user selection of a save feature, each associated facet provider object is serialized in the ordered sequence, and each serialization is collected into an ordered list of serializations and saved. The serialization of each facet provider object is performed by one of the respective facet provider object and a facet provider object of a same type as the respective facet provider object. A selection statement is constructed from the associated facet provider objects in the ordered sequence. A difference between the constructed selection statement and an actual selection statement is calculated and the selection statement difference is appended to the saved ordered list of serializations.

Proceedings ArticleDOI
06 Sep 2010
TL;DR: This paper considers a realistic model in which transactions' read/write sets are not known a-priori, and transactions' data access patterns may vary depending on the observed snapshot, and formalizes a set of correctness and optimality properties.
Abstract: In this paper we investigate the problem of speculative processing in a replicated transactional system layered on top of an optimistic atomic broadcast service. We consider a realistic model in which transactions' read/write sets are not known a-priori, and transactions' data access patterns may vary depending on the observed snapshot. We formalize a set of correctness and optimality properties aimed at ensuring that transactions are not activated on inconsistent snapshots, as well as the minimality and completeness of the set of explored serialization orders. Finally, an optimal speculative transaction replication protocol is presented.

Proceedings ArticleDOI
16 Jun 2010
TL;DR: This paper presents VMRPC, a light-weight RPC framework specifically designed for VMs that leverages heap and stack sharing to circumvent unnecessary data copying and serialization/deserilization, and achieve high performance.
Abstract: Despite advances in high performance inter-domain communication for virtual machines (VM), data intensive applications developed for VMs based on traditional remote procedure call (RPC) mechanism still suffer from performance degradation due to the inherent inefficiency of data serialization/deserilization operation. This paper presents VMRPC, a light-weight RPC framework specifically designed for VMs that leverages heap and stack sharing to circumvent unnecessary data copying and serialization/deserilization, and achieve high performance. Our evaluation shows that the performance of VMRPC is an order of magnitude better than traditional RPC systems and existing alternative inter-domain communication mechanisms. We adopt VMRPC in a real system, and the experiment results exhibit that the performance of VMRPC is even competitive to native environment.

Proceedings ArticleDOI
13 Jun 2010
TL;DR: This work formalizes a set of correctness and optimality properties ensuring the minimality and completeness of the set of explored serialization orders within the replicated transactional system.
Abstract: We define the problem of speculative processing in a replicated transactional system layered on top of an optimistic atomic broadcast service. A realistic model is considered in which transactions' read and write sets are not a priori known and transactions' data access patterns may vary depending on the observed snapshot. We formalize a set of correctness and optimality properties ensuring the minimality and completeness of the set of explored serialization orders within the replicated transactional system.

Patent
12 May 2010
TL;DR: In this article, a method for serialization and deserialization is proposed, where the number of channels is taken as variable, a frame format encoding serial data is set, a local reception end determines the frame head of the received serial data according to the set frame format and converts the serial data into N-bit parallel data; the parallel data is analyzed according to set frame formats so as to obtain a link state and the N-bits parallel data are output.
Abstract: The invention discloses a method for serialization and deserialization, comprising the following steps: the number N of channels is taken as variable, a frame format encoding serial data is set; a local reception end determines the frame head of the received serial data according to the set frame format and converts the serial data into N-bit parallel data; the parallel data is analyzed according to the set frame format so as to obtain a link state and the N-bit parallel data is output; a local transmission end encodes the local parallel data according to the set frame format, and the parallel data corresponding to the frame format is output according to the link state resulted from the analysis of the local reception end; and the parallel data is converted into the serial data and frequency-doubling high-speed clock is utilized to output the serial data. The invention further discloses a device for serialization and deserialization; by adopting the method and the device, chips with the single-chip SERDES function can be used for the mutual conversion between parallel signals and serial signals of the different number of channels, and meanwhile, consumptive cost of users is reduced.

Patent
26 May 2010
TL;DR: In this paper, a language analysis of an extensible markup language security application, relating to a computer data processing technology field, is presented, which includes: according to the content needing for signature and with encryption of the known safety strategy as well as the signature way, the corresponding position information of all path expression is ensured; according to pathexpression, the data structure of finite state automata is correspondingly built with a character in the path expression used as of the state jumping condition of the automata; a message string of the safety strategy is applied by inputting orderly
Abstract: The invention relates to a language analysis of an extensible markup language security application, relating to a computer data processing technology field; The method includes: according to the content needing for signature and with encryption of the known safety strategy as well as the signature way, the corresponding position information of all path expression is ensured; according to the pathexpression, the data structure of finite state automata is correspondingly built with a character in the path expression used as of the state jumping condition of the automata; a message string of thesafety strategy is applied by inputting orderly the finite state automata for matching and receiving XML message to safe process the needed position message; the XML message of the original serialization string format as well as the offset sequence of the position message are regarded as a analysis result, and inputted to a safety processing module of the XML safety application for safety processing. The invention can improve the entire performance of the XML safety application from the time and space consumption.

Patent
17 Mar 2010
TL;DR: In this paper, a method for time-sequence data processing, a device and a system therefor, is presented, which comprises: acquiring time information, an attributive serialization passage and an application processing type of the data to be processed; corresponding the serialisation passage to the application processing types; determining a storage unit corresponding to the data according to the time information and the serialization passages; and processing the data by the instruction of the applicationprocessing type by the storage unit.
Abstract: The invention discloses a method for time-sequence data processing, a device and a system therefor. The method comprises: acquiring time information, an attributive serialization passage and an application processing type of the data to be processed; corresponding the serialization passage to the application processing type; determining a storage unit corresponding to the data to be processed according to the time information and the serialization passage; and processing the data to be processed by the instruction of the application processing type by the storage unit. The method, the device and the system can optimize the storage and the management for the data.

Patent
17 Mar 2010
TL;DR: In this article, a system for forwarding messages of an ESB consisting of an access engine and a ESB kernel is described, where the access engine provides access support of respective technical specification for a caller party and a callee party, and forwards a call request of the caller party or an execution result of the callee parties.
Abstract: The invention relates to a system for forwarding messages of an ESB The system comprises an access engine and an ESB kernel, wherein the access engine provides access support of respective technicalspecification for a caller party and a callee party, and forwards a call request of the caller party or an execution result of the callee party; and the ESB kernel determines positions and types of afirst access engine corresponding to the caller party and a second access engine corresponding to the callee party, and selects direct forwarding, forwarding after natural serialization or forwardingor after unified message conversion of the call request transmitted by the caller party through the first access engine according to a determination result The invention also relates to an ESB message forwarding method and a server which correspond to the system The method and the system thereof perform message conversion of different strategies aiming at different conditions on comparison of the access engine types on the ESB, execute direct forwarding, natural serialization or unified message conversion of the messages according to different priorities, and achieve the aims of reducing message conversion times and improving the performance through optimization

Proceedings ArticleDOI
25 Oct 2010
TL;DR: It is proposed that Transactional memory (TM) is a good match to software packet processing: it both can allow the system to optimistically exploit parallelism between the processing of packets whenever it is safe to do so, and is easy-to-use for a programmer.
Abstract: Software packet processing is becoming more important to enable differentiated and rapidly-evolving network services With increasing numbers of programmable processor and accelerator cores per network node, it is a challenge to support sharing and synchronization across them in a way that is scalable and easy-to-program In this paper, we focus on parallel/threaded applications that have irregular control-flow and frequently-updated shared state that must be synchronized across threads However, conventional lock-based synchronization is both difficult to use and also often results in frequent conservative serialization of critical sections Alternatively, we propose that Transactional memory (TM) is a good match to software packet processing: it both (i) can allow the system to optimistically exploit parallelism between the processing of packets whenever it is safe to do so, and (ii) is easy-to-use for a programmer With the NetFPGA [1] platform and four network packet processing applications that are threaded and share memory, we evaluate hardware support for TM (HTM) using the reconfigurable FPGA fabric Relative to NetThreads [2], our two-processor four-way-multithreaded system with conventional lock-based synchronization, we find that adding HTM achieves 6%, 54% and 57% increases in packet throughput for three of four packet processing applications studied, due to reduced conservative serialization

Patent
23 Jun 2010
TL;DR: In this article, a method and equipment for manufacturing an electronic newspaper document, which belongs to the field of digital content publication, is described, which is applied to reading on various portable digital devices with different display environments.
Abstract: The embodiment of the invention discloses a method and equipment for manufacturing an electronic newspaper document, which belong to the field of digital content publication. The manufactured electronic newspaper document is applied to reading on various portable digital devices with different display environments. The method provided by the embodiment of the invention comprises the following steps: organizing an XML edition catalog document and an XML layout document by using an XML according to the layout customizing demand; extracting digital content information from the XML edition catalog document and the XML layout document; constructing an electronic newspaper object containing content data and a presentation method for the extracted digital content information; and generating an electronic newspaper target document for the constructed electronic newspaper object through an object serialization write-in mechanism. The electronic newspaper object manufactured by the embodiment of the invention can be independent from the target reading equipment, and is suitable for reading on the various portable digital devices.

Patent
06 Dec 2010
TL;DR: In this paper, a method of serialization in a data processing system includes serializing a mutable object utilizing a full serialization process, caching primitive data and metadata regarding the mutable objects in binary format in cache and then checking whether primitive fields of the object are modified.
Abstract: A method of serialization in a data processing system includes serializing a mutable object utilizing a full serialization process, caching primitive data and metadata regarding the mutable object in binary format in cache and then checking whether primitive fields of the mutable object are modified. Thereafter, the mutable object is again serialized utilizing an abbreviated serialization process by reference to the cached primitive data and metadata if the primitive fields of the object are not modified. In the event that primitive fields of the object are modified, the full serialization process is utilized. Thereafter, the serialized mutable object is communicated to a distributed code element.

Patent
28 Jun 2010
TL;DR: In this article, a distributed computation construction infrastructure identifies an execution context bound to a user context at a device, the execution context corresponding to one or more processes executing at the device.
Abstract: An approach is provided for construction and aggregation of distributed computations. A distributed computation construction infrastructure identifies an execution context bound to a user context at a device, the execution context corresponding to one or more processes executing at the device. The distributed computation construction infrastructure further causes, at least in part, decomposition of the execution context into one or more closure primitives and respective process states, wherein the one or more closure primitives represent computation closures of the one or more processes. The distributed computation construction infrastructure also causes, at least in part, serialization of the one or more closure primitives, the process states, or a combination thereof. The distributed computation construction infrastructure further causes, at least in part, aggregation of the one or more primitives and the respective process states to reconstruct at least a portion of the execution context based, at least in part, on consistency determination.