Showing papers on "Silicon oxide published in 1985"

Manufacture of semiconductor device

Abstract: PURPOSE:To suppress the generation of distortion when an ion implantation is performed and, at the same time, to reduce the crystal defects induced by the ion implantation by a method wherein, when a high density impurity region is going to be formed, an ion implantation with a small quantity of dosage, which is obtained by dividing the required dosage, is performed a plurality of times, and a heat treatment is performed immediately after each ion implantation. CONSTITUTION:A silicon oxide film 3 is formed on an N-type epitaxial layer 2 by performing a thermal oxidization processing. Then, an aperture is perforated on a part of the silicon oxide film 3, which is a base forming region in other words. Then, B is ion-implanted with the energy of 50keV and the dosage of 3.5X10 cm through the above-mentioned aperture, and a P-type ion-implanted layer 4 is formed in said N-type epitaxial layer 2 as an N-type semiconductor base. At this time, the dosage used in this case is set one half of the dosage which is intrinsically required. Directly after the above-mentioned procedure, a heat treatment is performed in an N2 atmosphere, and a P-type diffusion layer 5 is formed. Then, B is ion-implanted again through the aperture of the silicon oxide film 3, and a P-type ion-implanted layer 6 is formed. The energy used at this time is 50keV and the dosage is 3.5X10 cm , which are same as those used previously.

Remote plasma enhanced CVD deposition of silicon nitride and oxide for gate insulators in (In, Ga)As FET devices

Abstract: We have deposited silicon nitride (Si3N4) and silicon oxide (SiO2) thin films using remote plasma enhanced chemical vapor deposition (RPECVD). We have characterized the chemical composition of the films by infrared absorption (IR), x‐ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), and Rutherford backscattering (RBS), and have studied the electrical properties in metal insulator semiconductor (MIS) device configurations. We have configured the deposition system and adjusted gas flow rates in order to minimize: (a) O contamination in the Si3N4 films; and (b) OH groups in the SiO2 films. This paper describes the deposition apparatus and the process, and presents a phenomenological model for the plasma phase and surface reactions involved. We have combined both types of insulators in a trilayer dielectric that has been used as a gate insulator for (In,Ga)As insulated gate field effect transistors (IGFET’s). We have found that the electrical properties of these devices are superior to ...

Semiconductor memory device

Abstract: PURPOSE:To obtain an amorphous nonvolatile memory, which has excellent holding characteristics and reproducibility and a large area and large capacitance and cost thereof is low, by using an amorphous silicon carbide film in place of an amorphous silicon nitride film. CONSTITUTION:An insulating substrate 11, a lower electrode 12, an N type 13, which is hydrogenated previously by amorphous silicon and to which phosphorus is doped to a high degree, and an N type 14 to which phosphorus is doped similarly to a low degree are formed in the order. An silicon oxide film 15 in which amorphous silicon in oxidized through plasma anodizing, etc., a film 16, which consists of a hydrogenated amorphous silicon carbide film and contains carbon by 35atom% or more, and an upper electrode 17 are shaped in the order. Accordingly, a device having performance, which has not exist as nonvolatile memories, such as, a holding time of ten years or more, a writing time of 0.1musec or less, even fast erasing speed, a large area and large capacitance and low cost is obtained.

Dielectric isolation of silicon by anodic bonding

Abstract: Dielectrically isolated silicon was produced by anodically bonding together a pair of silicon wafers whose surfaces were covered with an electrically nonconductive micron layer of thermally grown oxide. Although anodic bonding normally requires a conductive oxide, anodic bonding works with nonconductive silicon oxide if the total layer of silicon oxide is less than ten microns thick. The time needed for the anodic bonding process decreases monotonically with temperature because the increase in the deformability of silicon oxide overcomes the decrease in the maximum permissible anodic bonding voltage with temperature. However, factors such as silicon degradation and electrode reactions at very high temperatures indicate that a compromise temperature range of 850–950 °C is best for the anodic bonding of silicon oxide. Bonding voltages of 30–50 V for times of about an hour produced the best bonding yields at these temperatures. Anodically bonded silicon wafers were examined with infrared and ultrasonic transmission microscopy for bond quality. Small scattered nonbonded zones comprising on the average 5% of the total wafer area were found in all wafers. These nonbonded zones were the result of dust particles, entrapped gas, and dimensional mismatches between multiple bonding fronts.

Non-linear device for driving liquid crystal display

Abstract: A non-linear device used for driving a liquid crystal display is disclosed. This non-linear device comprises a first amorphous silicon layer, an insulator film deposited on the first silicon layer and a second amorphous silicon layer deposited on said insulator film. The insulator film may be made of silicon oxide or silicon nitride. The non-linear device thus has an SIS structure.

Method of manufacturing a semiconductor device

Abstract: A method for manufacturing a semiconductor device having a high breakdown voltage and a high reliability, comprises (a) forming on a semiconductor substrate an insulating layer having a diffusion window; (b) forming an impurity-doped poly-silicon layer on the insulating layer and on that portion of the semiconductor substrate which is exposed through the diffusion window; (c) forming an undoped poly-silicon layer on the impurity-doped poly-silicon layer; (d) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer and undoped poly-silicon layer, thus diffusing the impurity from the impurity-doped poly-silicon layer into the semiconductor substrate through the diffusion window and converting the undoped poly-silicon layer to a silicon oxide layer; (e) forming on the silicon oxide layer an oxidation-resisting mask layer in a desired pattern; and (f) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer, silicon oxide layer and mask layer, thus converting those portions of the impurity-doped poly-silicon layer which lie beneath those portions of the silicon oxide layer which are exposed through the mask layer to impurity-doped silicon oxide layers, whereby the remaining portions of the impurity-doped poly-silicon layer provide an interconnection electrode layer having a desired pattern.

Silicon oxide thin film etching process

Abstract: A plasma dry etch process for etching semiconductor insulating materials, such as thermally grown or CVD deposited silicon oxide, with selectivity to silicon and refractory metals and their silicides, using a fluorinated inorganic center together with a hydrogen-liberating source under glow discharge conditions. The process does not employ saturated or unsaturated fluorocarbons as etchants, thereby eliminating the polymerization problem.

Ion bombardment induced changes in silicon dioxide surface composition studied by x‐ray photoelectron spectroscopy

Abstract: A model for the quantitative analysis of silicon oxide using x‐ray photoelectron spectroscopy (XPS) peak intensities is developed. This model is shown to have a precision of <5% in predicting the O/Si ratio within the XPS sampled volume. He+, Ne+, Ar+, and Xe+ bombardment of SiO2 are studied using this model. Results indicate that oxygen is preferentially depleted as a result of sputtering. Although elemental Si was not spectrally detected due to measurement noise and overlayer contamination, an equivalent upper limit to the elemental Si thickness of ∼2 A is determined for Ne+, Ar+, and Xe+; He+ results in about 4 A of elemental Si.

Iron-aluminum-phosphorus-silicon-oxide molecular sieves

Abstract: A novel class of iron-aluminum-phosphorus-silicon-oxide molecular sieves is disclosed which contain as framework constituents FeO 2 - , and/or FeO 2 -2 , AlO 2 - , PO 2 + and SiO 2 tetrahedral oxide units. These compositions are prepared hydrothermally, preferably using organic templating agents and are suitably employed as adsorbents and catalysts.

Transmission electron microscopy studies on the lateral growth of nickel silicides

Abstract: Transmission electron microscopy (TEM) has been utilized to study the nickel‐silicide growth in self‐supported lateral‐diffusion, thin‐film couples by overlapping deposited layers of Ni and Si between two silicon oxide deposited films. Energy‐dispersive x‐ray spectroscopy, microdiffraction, and selected area diffraction were used to identify the Ni‐silicide phases and their crystal structures. Long‐grain growth of Ni2Si, as a result of phase‐boundary migration induced by diffusion, was observed during in situ annealing between 500 and 750 °C in TEM. No preferred orientation or particular crystallographic relationship was found among the long grains.Transmission electron microscopy (TEM) has been utilized to study the nickel‐silicide growth in self‐supported lateral‐diffusion, thin‐film couples by overlapping deposited layers of Ni and Si between two silicon oxide deposited films. Energy‐dispersive x‐ray spectroscopy, microdiffraction, and selected area diffraction were used to identify the Ni‐silicide phases and their crystal structures. Long‐grain growth of Ni2Si, as a result of phase‐boundary migration induced by diffusion, was observed during in situ annealing between 500 and 750 °C in TEM. No preferred orientation or particular crystallographic relationship was found among the long grains.

Method of manufacturing an insulated gate field effect transistor

Abstract: A method of manufacturing an insulated gate field effect transistor has first and second impurity doping processes for forming source and drain regions. In the first doping process, an impurity is lightly doped in the source and drain forming regions in self-alignment with a silicon gate pattern and a field insulating film. Next, a heat treatment is conducted so that the side surface portions of the silicon gate pattern are converted into silicon oxide films having a predetermined thickness. Thereafter, the second doping process is conducted in which an impurity is heavily doped in each part of the source and drain forming region in self-alignment with the silicon oxide films and the field insulating film. Each of source and drain region manufactured by the method has a first part of low impurity concentration adjacent to a channel region and a second part of high impurity concentration positioned between the first part and the field insulating film. The deviation of the thickness of the silicon oxide film is very small, and the length of the first part depends on that thickness. On the other hand, the length of the first part of source, drain region influences the performance of the transistor, and therefore, the method can manufacture the transistor of a stable quality.

The Composition and Properties of PECVD Silicon Oxide Films

Abstract: Plasma‐enhanced chemical vapor‐deposited (PECVD) silicon oxide films were prepared by the reaction of and. The deposition rate as a function of flow rate, RF power, and total pressure was obtained. The film composition and properties for samples deposited with different flow rates were measured. Si‐rich films were obtained for the deposition with flow rate ratio of < 3.5. The refractive index increased and film thickness decreased after samples were annealed. Etch rate in a solution containing ten parts of ammonium fluoride and one part hydrofluoric acid (10:1 BHF) and refractive index decreased by increasing the Si:O ratio in samples. The bonds were found for all Si‐rich films. Both Si‒OH and H‒OH bonds were observed for all samples. The phases Si, , and were found for Si‐rich films. At a constant field, the film conductivity increased with increasing Si:O ratio. Evidence of electron traps was observed for PECVD and Si‐rich Si‐O films.

Lamp having interference film

Abstract: A lamp includes a glass bulb sealing a filament therein. A light interference film is formed on a surface of the bulb. The film has at least five layers and is formed by alternately stacking a low-refractive index layer comprising silicon oxide and a high-refractive index layer having a refractive index higher than said low-refractive index layer. The low-refractive index layer contains, at least one additive selected from the group consisting of phosphorus and boron.

Low-pressure oxidation of silicon stimulated by low-energy electron bombardment

Abstract: The mechanisms of silicon oxide growth stimulated by electronic bombardment have been studied. Silicon single crystals, after cleaning by ion bombardment in UHV, were submitted to a low-energy (<100eV) electron irradiation (∼ 1 mA cm−2), under low oxygen pressure (10−4 Torr) in the temperature range 25–700°C. Oxide thicknesses less than 10 nm were thereby achieved. There is a strong increase of the initial growth rate when the electron energy decreases to 10eV. The oxidation kinetics can be fitted by a direct logarithmic law: X = X 0 log [(t/τ) + 1] where X is the thickness of oxide grown during time t and U = X 0/τ is the initial growth rate. Using the results of 18O tracing experiments, the growth mechanism is explained by a step-by-step motion of charged oxygen species under a constant electric field.

Transparent plastic can

Abstract: A transparent plastic can which comprises a transparent body formed of a laminated plastic structure, the inner surface of which is coated with a thin layer of silicon oxide.

A shape-selective platinum-loaded mordenite catalyst for the hydrocracking of paraffins by the chemical vapour deposition of silicon alkoxide

Abstract: A platinum-loaded H-mordenite (PtHM) catalyst has been modified by the chemical vapour deposition of silicon alkoxide in order to improve its shape-selectivity for the hydrocracking of paraffins. The paraffins reacted on the silica-coated PtHM according to their molecular size, and reactant shape-selectivity was achieved by choosing the extent of modification. Silica was only deposited on the external surface of the zeolite to form mono-, di- or tri-layers of SiO2, with the internal acid and metal sites unpoisoned, thus effectively narrowing the pore exit size only. Platinum metal on the external surface was not completely covered by the silicon oxide.

An investigation on surface conditions for Si molecular beam epitaxial (MBE) growth

Abstract: Contamination‐free Si substrate surfaces are vitally important to the subsequent molecular beam epitaxy (MBE) growth. A number of studies on the major contaminants, i.e., C and O, on Si surfaces have been done, and new cleaning procedures for reducing these contaminants have been proposed. However, to date the detailed behavior of C and O on Si surfaces and their effects on the subsequent Si MBE growths are not well established. In the present work, the behavior of the contaminants on heated Si surfaces were investigated using Auger electron spectroscopy (AES) and secondary ion mass spectrometry (SIMS). Also, the chemical bonding of C on Si surfaces was studied by analyzing the AES line shapes of carbon and comparing them with those known carbon chemical states. For the chemical cleaning procedures used in this study, a silicon oxide protection layer is grown onto the cleaned Si surface prior to sample loading. The property of this silicon oxide layer is studied using ellipsometry measurements. To verify ...

Semiconductor device and manufacture thereof

Abstract: PURPOSE:To reduce a collector capacitance and make a transistor operable at a high speed, by forming, the parts corresponding to at least the part to come into an active region of a semiconductor device, into non-insulating regions, and forming the other parts into insulating regions, on the non-insulating region of a substrate, and by sticking on the surface thereof a different substrate from the foregoing substrate to form the complete semiconductor device. CONSTITUTION:On a P -type single crystal silicon substrate 11, a silicon oxide film 12, an N -type polycrystalline silicon film 13, and a silicon oxide film 14 are formed in succession. On the predetermined part thereof, a window 14a is formed, and an N -type polycrystalline silicon film 15 is so formed as to be buried therein. Then, while the foregoing is referred to as a substrate 16, the N -type polycrystalline silicon film 15 is left only in the window 14a. On the other hand, an N -type single crystal silicon substrate 17 is prepared, and is stuck on the substrate 16. Caused by annealing when sticking, an N -type collector diffusion layer 18 is formed in the part of the single crystal silicon substrate 17, which exists just over the N -type polycrystalline silicon film 15. Thereby, a buried collector is formed with the N -type polycrystalline silicon films 13, 15 and N -type collector diffusion layer 18. Then, an N -type epitaxial layer 19 is grown on the surface of the substrate 17.

Silica intercalated crystalline zirconium phosphate-type materials

Abstract: The present invention relates to intercalated crystalline zirconium phosphate-types compositions wherein the interlayers of said composition have been intercalated with three-dimensional silicon oxide pillars whereby the pillars comprise at least two silicon atom layers parallel to the clay interlayers.

Manufacture of semiconductor device

Abstract: PURPOSE:To increase gate withstanding voltage and improve frequency characteristics by isolating a gate electrode and a contact layer having high electron concentration only by the width of the side wall of a temporary gate and forming the gate electrode and the contact layer in a self-alignment manner, shaping the gate electrode having a T-shaped sectional form and removing an silicon nitride film. CONSTITUTION:An active layer 2 is crystal-grown on a substrate 1, and an silicon oxide film (a first insulating film)is formed, and patterned to a gate electrode form shaped through a post-process. When an silicon oxide film 4 (a second insulating film) is formed onto a temporary gate 3 and etched, a side wall 4a consisting of an silicon nitride film remains only on both side surfaces of the temporary gate 3. When a contact layer 5 is shaped, single crystals selectively grow on the contact layers on both sides of the side all. When an silicon nitride film 6 (a third insulating film) and a photo-resist 7 are applied and etched, only the nitride films on the temporary gate 3 and the side wall 4a are removed and the temporary gate 3 and the side wall 4a and the silicon nitride as the silicon nitride film 6 and the side wall 4a are left as they are. A gate electrode 8 is formed from an upper section.

Manufacture of semiconductor device

Abstract: PURPOSE:To eliminate the dispersion of current amplification due to the difference in dimensional shape by a method wherein the junction shape of the part wherein the first time oxide film comes into contact with the second conductive impurity is a flat one having almost no curvature due to the encroachment of the first time oxide film by the second time oxidation. CONSTITUTION:An N-type buried layer 107 is formed on a P-type silicon substrate 101 and then an N-type epitaxial layer 102 is formed on the N-type buried layer 107. Firstly a P-type regions 103 to electrically isolate transistors are formed and after forming a thin oxide film on the surface of a substrate 101, an oxidation resistant film e.g. a silicon nitride film 106 is formed at least on a base region 105 and then the first time thermal oxidation process is performed to form a silicon oxide film 104. Secondly the base region 105 is formed by implanting P-type impurity using the oxide film 104 as a mask by ion implantation process. Finally the silicon oxide film 104 is formed further thicker by the second time thermal oxidation process. Through the second time thermal oxidation process, the junction shape 112 of the part wherein the base region 105 comes into contact with the oxide film after the first time thermal oxidation is changed into almost the same shape as that shown by 112a due to the second time thermal oxidation.

Armored cable having mineral insulation

Abstract: An armored cable having mineral insulation, comprising a metal central conductor and a cylindrical hollow metal sheath between which a powdered refractory insulating material is interposed, characterized in that the mineral insulating material is a mixture of 10 to 30% by weight of magnesium oxide (MgO) and 70 and 90% by weight of silicon oxide (SiO 2 ).

Assessment of the relative contribution of atomic mixing and selective sputtering to beam induced broadening in SIMS depth profiling

Abstract: A thin native silicon oxide layer, covered with hydrogen- and carbon-containing impurities, was sandwiched between a crystalline silicon substrate and an evaporated 35 nm layer of amorphous silicon. SIMS depth profiles of H − , C − , O − and Si − were measured under 4 to 12 keV Cs + impact. The impurity profiles exhibit exponential slopes at the leading and the trailing edges. The characteristic widths describing the exponential tails increase with increasing probe energy. At the leading edges the characteristic widths for H, C and O are identical whereas at the trailing edges the decay lengths are strongly element-specific. The results are interpreted in terms of the relative importance of atomic mixing and selective sputtering. The oscillatory behaviour of the Si − and H − yields, observed in the vicinity of the interface, is also discussed.

Microwave spectroscopic measurement of the electron density in a planar discharge: Relation to reactive‐ion etching of silicon oxide

Abstract: It is demonstrated that microwave cutoff can be used to measure absolute electron densities for CHF3, Ar, and O2 plasmas in a batch‐mode planar reactor excited at 13.56 MHz. The densities obtained are between 1015 and 1016 m−3 for all gases and a large set of conditions (pressure, rf power, electrode spacing). A comparison with selective etching of SiO2 over Si in the same reactor shows a qualitative agreement between the substrate ion flux calculated from the electron density and the etch rate of silicon oxide; the apparent sputter yield ranges from 0.4 to 1.4 molecules per ion.

Fabrication of dielectrically isolated devices utilizing buried oxygen implant and subsequent heat treatment at temperatures above 1300° C.

Abstract: Dielectrically isolated devices are produced by a series of steps including the implantation of a silicon substrate to produce a precursor to the silicon oxide region and subsequently heat treating this region. In contrast to previous techniques, the extent of such heating is substantially increased to remove a non-oxidic intermediary region typically remaining.

Formation of thin film

Abstract: PURPOSE:To increase the deposition rate of a film and to improve productivity in the stage of forming the thin film by a sputtering method by specifying the surface shape of a target material CONSTITUTION:An Si substrate as a substrate 17 to be treated is installed on a lower electrode 13 and the inside of a vacuum vessel 11 is evacuated to a prescribed degree of vacuum in the stage of forming, for example, a silicon oxide film by a sputtering device For example, gaseous Ar is introduced into the vessel from an introducing port 18 and the inside of the vessel 11 is maintained under a prescribed gaseous pressure A high-frequency power source 15 is then turned on to impress the prescribed high-frequency voltage between upper and lower electrodes 12 and 13 to generate an electric discharge so that the target material 16 is sputtered by Ar ions and the silicon oxide film is deposited on the substrate 17 The surface shape of the material 16 is thereby made into a recessed shape Then the released atoms are directed toward the substrate 17 to be formed with the film thereon and the deposition rate is increased

Arsenic segregation to silicon/silicon oxide interfaces

Abstract: Arsenic segregation at polycrystalline silicon/silicon and polycrystalline silicon/silicon oxide interfaces was examined directly by transmission electron microscopy(TEM) and scanning transmission electron microscopy(STEM). Segregation occurring precisely at these interfaces was identified. A simple model was proposed based on arsenic segregation to structural units containing dangling bonds and consequent bond saturation. The removal of these dangling bonds will then play an important role in the electrical properties of these interfaces. Furthermore substitutional arsenic segregation at a degenerate level at these interfaces was also proposed. The subsequent dopantionization and localized charges at the interfaces was discussed.