Showing papers on "State (computer science) published in 1996"

Principles and methods of testing finite state machines-a survey

Abstract: With advanced computer technology, systems are getting larger to fulfill more complicated tasks: however, they are also becoming less reliable. Consequently, testing is an indispensable part of system design and implementation; yet it has proved to be a formidable task for complex systems. This motivates the study of testing finite stare machines to ensure the correct functioning of systems and to discover aspects of their behavior. A finite state machine contains a finite number of states and produces outputs on state transitions after receiving inputs. Finite state machines are widely used to model systems in diverse areas, including sequential circuits, certain types of programs, and, more recently, communication protocols. In a testing problem we have a machine about which we lack some information; we would like to deduce this information by providing a sequence of inputs to the machine and observing the outputs produced. Because of its practical importance and theoretical interest, the problem of testing finite state machines has been studied in different areas and at various times. The earliest published literature on this topic dates back to the 1950's. Activities in the 1960's mid early 1970's were motivated mainly by automata theory and sequential circuit testing. The area seemed to have mostly died down until a few years ago when the testing problem was resurrected and is now being studied anew due to its applications to conformance testing of communication protocols. While some old problems which had been open for decades were resolved recently, new concepts and more intriguing problems from new applications emerge. We review the fundamental problems in testing finite state machines and techniques for solving these problems, tracing progress in the area from its inception to the present and the stare of the art. In addition, we discuss extensions of finite state machines and some other topics related to testing.

System and method for maintaining continuous and progressive game play in a computer network

Abstract: A system for maintaining continuous and progressive game play in a computer network. The system includes at least one server and at least one game-playing client, in communication with each other through a computer network. Each server includes a memory storing game data which includes initial game data specifying an initial game state and which includes accumulated game data specifying updates to the initial game state. Either the server or the client includes memory storing knowledge base rules and storing an executable computer game program for applying the knowledge base rules to the game data. The executable computer game program generates responses to the client and updates the accumulated game data. The system optionally comprises a second game-playing client and a second server including memory which stores game data connected to the network. The game data in the second server may be derived from and identical to the game data in the first server, thereby establishing a second instance of the first server game state.

Hand held computerized data collection terminal with rechargeable battery pack sensor and battery power conservation

Abstract: An improved hand-held data terminal is provided. A sensing circuit senses the presence of rechargeable batteries. A rechargeable battery pack can be used in the hand-held data terminal. The battery pack can include a short circuit element. The short circuit element comes into contact with the hand-held data terminal when the rechargeable battery pack is assembled with the hand-held data terminal. The short circuit element, when in contact with the hand-held data terminal, serves to indicate the presence of the rechargeable battery pack and to thereby enable the recharging capabilities of the hand-held data terminal. A battery pack which does not contain the short circuit element cannot be recharged by the hand-held data terminal since the recharging circuit of the data terminal would remain in a disabled state. Further, the battery pack can be shaped asymmetrically so that it can only be assembled with the hand-held data terminal in an operational orientation.

The Cambridge illustrated history of China

Abstract: Foreword Kwang-Ching Liu Preface Acknowledgements 1. The origins of Chinese civilization: Neolithic period to the western Zhou dynasty (animal and human imagery in bronze vessels) 2. Philosophical foundations: the eastern Zhou period 3. The creation of the bureaucratic empire: the Qin and Han dynasties 4. Buddhism, aristocracy, and alien rulers: the age of division (early Buddhist art) 5. A cosmopolitan empire: the Tang dynasty 6. Shifting south: the Song dynasty (landscape painting) 7. Alien rule: the Liao, Jin, and Yuan dynasties (drama and the performing arts) 8. The limits of autocracy: the Ming dynasty (the kilns at Jingdezhen) 9. Manchus and imperialism: the Qing dynasty (working for a living) 10. Taking action: the early twentieth century (modern Chinese painting) 11. Radical reunification: the People's Republic Epilogue Chronology Picture acknowledgements Notes Further reading Index.

Principles of Digital Design

Abstract: (NOTE: Each chapter ends with a summary, problems and further readings.) 1. Introduction. Design representation. Levels of abstraction. Design process. CAD tools. Typical design process. Road map. 2. Data Types and Representations. Positional number systems. Octal and hexadecimal numbers. Number system conversions. Addition and subtraction of binary numbers. Representation of negative numbers. Two's-complement addition and subtraction. Binary ultiplication. Binary division. Floating-point number representation. Binary codes for decimal numbers. Character codes. Codes for error detection and correction. Hamming codes. 3. Boolean Algebra and Logic Design. Algebraic properties. Axiomatic definition of boolean algebra. Basic theorems of boolean algebra. Boolean functions. Canonical forms. Standard forms. Digital logic gates. Extension to multiple inputs and multiple operators. Gate implementations. VLSI technology. 4. Simplification of Boolean Functions. The map representation. The map method of simplification. Don't-care conditions. The tabulation method. Technology mapping for gate arrays. Technology mapping for custom libraries. Hazard-free design. 5. Combinatorial Components. Carry-ripple adders. Carry-look-ahead adders. Adders/subtractors. Logic unit. Arithmetic-Logic Unit. Decoders. Selectors. Buses. Priority encoders. Magnitude comparators. Shifters and rotators. Read-Only memories. Programmable logic arrays. 6. Sequential Logic. SR-latch. Gated SR-latch. Gated D-latch. Flip-flops. Flip-flop types. Analysis of sequential logic. Finite-state-machine model. Synthesis of sequential logic. FSM model capture. State minimization. State encoding. Choice of memory elements. Optimization and timing. 7. Storage Components. Registers. Shift registers. Counters. BCD counter. Asynchronous counter. Register files. Random-access memories (RAMs). Push-down stacks. Firs- in-first-out queue. Simple datapaths. General datapaths. Control unit design. 8. Register-Transfer Design. Design model. FSMD definition. Algorithmic-state-machine charts. Synthesis from ASM charts. Register sharing (variable merging). Functional unit sharing (operator sharing). Bus sharing (connection merging). Register merging. Chaining and multicycling. Functional unit pipelining. ASM pipelining. Control- pipelining. Scheduling. 9. Processor Design. Instruction sets. Addressing modes. Processor design. Instruction set design. Processor design. Reduced instruction set. RISC Design. Data forwarding. Branch prediction.

Preserving state information in a continuing conversation between a client and server networked via a stateless protocol

Abstract: A method and system for preserving state in computers communicating over networks, such as the World Wide Web (WWW) using stateless protocols, e.g., HTTP. State is preserved in a conversation between a client requesting services from a served by performing the service and identifying all continuations (hyperlinks) in an output from the service; recursively embedding the state information in all identified continuations in the output sent to the client. The state information may be embedded and communicated by the server to the client. Alternatively, dynamically downloadable program code may be used to embed the state information at the client. Additional features enable the filtering and/or addition of hyperlinks and data output from the services according to predetermined criteria. State information may be embedded by modifying an identified continuation which is a request for an HTML file, to invoke a CGI converter program with the identified continuation and the state information passed as arguments. State information may also be embedded by modifying an identified continuation which is an invocation to a CGI program with the identified continuation and the state information passed as arguments, and the embedding step is performed by the CGI program. Alternatively, an identified continuation which is an invocation of a CGI program may be modified to invoke a CGI converter program with the identified continuation, an argument counter which indicates a number of arguments associated with the CGI program, and the state information passed as arguments. Here, the embedding is performed by the converter program.

Combining hardware and software to provide an improved microprocessor

Abstract: A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising means to translate a set of target instructions into instructions of a host instruction set, means to optimize the instructions of the host instruction set translated from the target application program speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target application program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance with the speculation, means to detect failure of the condition during the execution of the set of host instructions, means for updating state of the host computer from state of the target computer when a set of host instructions fails to execute in accordance with the speculation, and means to translate a new set of host instructions without the speculation when a set of host instructions fails to execute in accordance with the speculation.

Method and system for controlling power consumption in a computer system

Abstract: A portable, software-controlled system for managing power consumption in a computer system. The power management system is integrated with the operating system of the computer system and is extensible to any add-on devices that are installed into the computer system. Upon the detection of a power down condition indicating that the computer system should be powered down, the power management system may verify that the computer system can be powered down without causing any of the devices that are connected to the computer to lose application data. If all of the devices agree that the computer system can be powered down, then each device has its state saved into memory and is powered down. Next, the state of each processor is saved into memory and power to the processors is disabled. In order to suspend the computer system, power to the memory is maintained, allowing each device state and processor state to be restored upon reboot. The computer system may be hibernated by writing all of the active memory (including each device state and processor state) to a secondary storage area and then powering off the entire computer system, including memory.

Receiver-driven layered multicast

Abstract: State of the art, real-time, rate-adaptive, multimedia applications adjust their transmission rate to match the available network capacity. Unfortunately, this source-based rate-adaptation performs...

System and method for recovering PC configurations

Abstract: A computer utility automatically monitors changes in configuration files stored on the computer hard disk. The recovery tool indicates to the user when changes are detected in the configuration files and provides the option to restore the configuration files to their state before they were changed if the computer system operates improperly. In addition, the recovery tool monitors selected application files for changes in the files or missing files, and prompts the user when a change is detected. The recovery tool also provides for monitoring of the CMOS memory which stores computer system operating functions and parameters. If possible corruption of the CMOS memory is detected, the recovery tool restores the contents of the CMOS to their proper state. Finally, the computer utility provides the option of making a bootable floppy diskette containing the computer system configuration. The floppy diskette also stores files from the utility necessary to provide for restoration of the configuration, if necessary, from the floppy diskette.

Authoring tool comprising nested state machines for use in a computer system

Abstract: According to the invention, an authoring tool comprises at least one nestable graphic state and transition machine, hereinafter referred to as a "state machine", each state machine comprising one or more states and zero or more transitions, each transition interconnecting a first state, known as the "from -- state", with a second state, known as the "to -- state". The first and second states can be the same state or different states. For each state in the plurality of states there can be any number of transitions, including zero, emanating therefrom and directed thereto. Each state machine has a state designated as its "current state" which changes in response to users actions or other events. Each state machine also has an initial state which is the state that is designated as the current state when the multimedia title is launched. The authoring tool allows an author to view a state machine simultaneously in several different formats, providing a full view and a map view. State machines can be nested, i.e. a state machine can be contained by another state machine. Preferably, separate user and author views are provided so that an author can manipulate a multimedia product and simultaneously observe the effect such manipulation has on the multimedia product from the user's point of view. Preferably, a plurality of modes are provided, each mode being geared toward particular functionality within the invention and a mechanism is provided so that a user of the invention can selectively switch between modes.

Efficient context saving and restoring in a multi-tasking computing system environment

Abstract: In a multi-tasking computing system environment, one program is halted and context switched out so that a processor may context switch in a subsequent program for execution. Processor state information exists which reflects the state of the program being context switched out. Storage of this processor state information permits successful resumption of the context switched out program. When the context switched out program is subsequently context switched in, the stored processor information is loaded in preparation for successfully resuming the program at the point in which execution was previously halted. Although, large areas of memory can be allocated to processor state information storage, only a portion of this may need to be preserved across a context switch for successfully saving and resuming the context switched out program. Unnecessarily saving and loading all available processor state information can be noticeably inefficient particularly where relatively large amounts of processor state information exists. In one embodiment, a processor requests a co-processor to context switch out the currently executing program. At a predetermined appropriate point in the executing program, the co-processor responds by halting program execution and saving only the minimal amount of processor state information necessary for successful restoration of the program. The appropriate point is chosen by the application programmer at a location in the executing program that requires preserving a minimal portion of the processor information across a context switch. By saving only a minimal amount of processor information, processor time savings are accumulated across context save and restoration operations.

Non-volatile memory system having internal data verification test mode

Abstract: A memory system including means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. The memory system is placed into a test mode of operation in which an internal program or erase verify operation is executed under the control of the system's internal state machine. Once in the mode, the memory system steps through each memory cell, address by address, and reads the contents of the cell using the appropriate reference voltage for a programming or erase operation. A status register bit is set indicating successful completion of the verification operation for a block of memory cells. A register bit is also set if a cell fails the verification operation. This provides a more accurate determination of the state of a memory cell than can be achieved by performing an external read operation using read operation or data verification reference voltage levels.

Apparatus and method for preventing theft of computer devices

Abstract: Apparatus and method for discouraging computer theft The apparatus and method requires that a password or other unique information be supplied to the computer before the computer BIOS routines can be completely executed A BIOS memory storing the BIOS routines includes a security routine which will determine whether or not the required password entered by the user, or a known quantity read from an externally connected memory device is present The security function stored within the BIOS memory also includes an administration function which permits the computer to be either placed in a locked state, thereby requiring password or the known quantity read from an externally connected memory device to be present each time the computer is booted up The administration function also permits an unlock state which permits the computer boot up process to complete without entering any password or externally supplied quantity The external memory location is consulted during each boot up sequence, to determine whether the computer has been placed in the locked or in the unlocked state If the security depends upon the supply of the known quantity from an externally connected memory device, the computer will be inoperable to anyone not in possession of the external memory device In the event that the external memory location bearing the locked or unlocked code is removed, the security function assumes the computer to be in the locked state, thus frustrating avoidance of the locked state by tampering with the external memory

Method and apparatus for regression testing of application logic

Abstract: A method and system for regression testing of application logic within a software system. Software architecture can be separated into a presentation layer (e.g., user interface), an application layer (e.g., business logic), and a data/storage layer. Within the novel testing system, communication interfaces between the presentation layer and the application layer are identified such that user initiated commands ("events") passed from the presentation layer to the application layer are recorded into a test playback event file. During test playback event recordation, differences in the state of the application layer of a reference program are collected into a reference state log file. To test a program, the recorded events of the test playback event file are played back and applied directly to its application layer. After each event, the differences in the state of the program are collected into a test state log file. The reference and test state log files are compared and differences are stored in an error or summary difference file. By recording events that enter the application layer, in lieu of the user entered commands that enter the presentation layer, the novel testing system is insensitive to changes in the presentation layer and allows more direct testing and error detection of the application layer. By recording differences in the state of the application layer on an event by event basis, in lieu of recording differences in information presented to the user, the novel system allows more effective error detection and error isolation of the application layer.

Method and system for performing clean-up of a solid state disk during host command execution

Abstract: A system and method for converting invalid user data within a solid state disk into free memory during time allotted to execute a host command from a standard interface. Clean-up states are part of a clean-up state machine which controls the conversion of the invalid user data into free memory. Whenever a command interrupt is received from the standard interface, a watchdog timer is set to the maximum time allotted to execute the command. The command is executed first, and then a number of clean-up states to be executed in the remaining time is calculated. A counter is set equal to that number. Thereafter, a clean-up state is executed and the counter is decremented. Execution of clean-up states and decrementing of the counter continues until either the counter indicates all states have been executed or the timer indicates that all allotted time has expired. In one embodiment, the solid state disk is included in a computer system having a central processing unit, and the solid state disk includes a flash memory array and a memory array controller.

The State of SPIN

Abstract: The number of installations of the Spin model checking tool is steadily increasing. There are well over two thousand installations today, divided roughly evenly over academic and industrial sites. The tool itself also continues to evolve; it has more than doubled in size, and hopefully at least equally so in functionality, since it was first distributed in early 1991. The tool runs on most standard workstations, and starting with version 2.8 also on standard PCs.

Preventative maintenance and diagonstic system

Abstract: A maintenance system for a machine (12) controlled by a programmable logic controller (14) having a memory (20) which stores input data received from the machine (12) and output data communicated to the machine (12). The maintenance system includes a computer (33) interfaced to the memory to be non-intrusive with respect to the programmable logic controller (14). The computer (33) is operative to monitor a state of the machine (12) over a plurality of manufacturing cycles, the state including at least a portion of the input data and the output data. The computer (33) is further operative to detect a fault condition for a component of the machine (12) based upon a state of a current manufacturing cycle and a state of a previous manufacturing cycle. A display device (32) is in communication with the computer (33) to alert an operator of the fault condition and to graphically display a location of the component within the machine (12) to facilitate a corrective measure by the operator.

Computer network status monitoring system

Abstract: A status monitoring system for a computer network including obtaining, concurrently displaying, and dynamically updating, the operational state of a plurality of nodes in a computer network. The operational state for each node is displayed concurrently in an expandable hierarchical display having a dynamically updatable operational state icon corresponding to each node in the network. The operational state icon is characteristic of a traffic light and can be used in combination with superimposed status indicators.

Automated state model generation algorithm for power circuits and systems

Abstract: A new approach of automatically generating state-space models of power circuits and systems is presented. In this approach, the composite system state equations are established algorithmically given the standard node incidence matrix and elementary branch data (e.g. resistances, inductances, back emfs). The resulting state equations can be solved using a variety of numerical techniques or commercially available computer simulation programs. An example system consisting of a three-phase generator and rectifier load is used to illustrate this approach. Experimental verification is also provided.

Method and apparatus for computer system power management

Abstract: A method and apparatus for managing power states of at least one hardware resource, including registering at least one hardware resource power state corresponding to a software process, determining whether a current hardware resource power state fulfills the registered hardware resource power state corresponding to the software process, and modifying the current hardware resource power state that is determined not to fulfill the registered hardware resource power state prior to executing the software process.

Computer implemented machine learning and control system

Abstract: In a computer implemented learning and/or process control system, a computer model is constituted by the most currently fit entity in a population of computer program entities. The computer model defines fitness as a function of inputs and outputs. A computing unit accesses the model with a set of inputs, and determines a set of outputs for which the fitness is highest. This associates a sensory-motor (input-output) state with a fitness in a manner that might be termed "feeling". The learning and/or control system preferably utilizes a compiling Genetic Programming system (CGPS) in which one or more machine code entities such as functions are created which represent solutions to a problem and are directly executable by a computer. The programs are created and altered by a program in a higher level language such as "C" which is not directly executable, but requires translation into executable machine code through compilation, interpretation, translation, etc. The entities are initially created as an integer array that can be altered by the program as data, and are executed by the program by recasting a pointer to the array as a function type. The entities are evaluated by executing them with training data as inputs, and calculating fitnesses based on a predetermined criterion. The entities are then altered based on their fitnesses using a genetic machine learning algorithm by recasting the pointer to the array as a data (e.g. integer) type. This process is iteratively repeated until an end criterion is reached.

System and method for controlling copying and playing of digital programs

Abstract: A system and method for preventing effective copying of digital recordings. A copy-state code accompanies each recording, one state of which represents that no copies at all are to be made of the recording. Compatible players are designed to prevent play of any writable disk which includes a "no-copy" code. It is the inconsistency between the code and the medium containing it that causes play of the medium to be inhibited.

Memory cell capable of storing more than two logic states by using different via resistances

Abstract: A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

Methods of programming multi-state integrated circuit memory devices

Abstract: Methods of programming multi-state memory devices include the steps of programming a nonvolatile multi-state memory cell (e.g., EEPROM) from a reference state (e.g., erased state) towards a first program state, by applying a first program voltage (Vpgm) thereto. The first program voltage is preferably applied for a first predetermined time interval so that sufficient Fowler-Nordheim tunneling of electrons can occur into the cell's floating gate to cause a shift in the cell's threshold voltage from the reference state (e.g., Vth=-2 V) to a first program state (e.g., -1 V≦Vth≦-0.5). To verify the step of programming the memory cell into the first program state, a operation is performed by a sense amplifier to sense a first state of the memory cell, upon application of a first reference voltage thereto. Once verification of the first program state has been achieved, another programming step may be performed to program the memory cell from the first program state to a second program state, by applying a second program voltage thereto and then sensing a second state of the memory cell upon application of a second reference voltage thereto (e.g., Vpref2 >Vpref1). For example, the second program voltage (Vpgm) is preferably applied for a second predetermined time interval so that sufficient additional Fowler-Nordheim tunneling of electrons can occur into the cell's floating gate to cause a shift in the cell's threshold voltage from the first program state (e.g., Vth=-1 V) to the second program state (e.g., 0 V≦Vth≦0.5 V).

Improved reachability analysis of large finite state machines

Abstract: BDD-based symbolic traversals are the state-of-the-art technique for reachability analysis of Finite State Machines. They are currently limited to medium-small circuits for two reasons: peak BDD size during image computation and BDD explosion for representing state sets. Starting from these limits, this paper presents an optimized traversal technique particularly oriented to the exact exploration of the state space of large machines. This is possible thanks to: 1) temporary simplification of a Finite State Machine by removing some of its state elements, 2) a "divide-and-conquer" approach based on state set decomposition. An effective use of secondary memory allows us to store relevant portions of BDDs and to regularize access to memory, resulting in less page faults. Experimental results show that this approach is particularly effective on the larger ISCAS'89 and ISCAS'89-addendum'93 circuits.

Apparatus and method for reducing power consumption in a computer system

Abstract: A method and apparatus for reducing the power consumption of a processor in a computer system where a programming structure running on the processor determines when the processor is in an inactive state to cause clocking signals and the power supply to be disabled to the processor. The processor is again coupled to the power supply and the clock signals in response to a periodic interrupt signal, a non-periodic interrupt or a bus request from a peripheral device. Thereafter, the programming structure signals the control logic again when the processor reenters the inactive state, such that the control logic disables the clock signals and decouples the power supply to the processor when the processor returns to the inactive state. The method is extended to offer the ability to shut down the processor from programming structures running on alternate masters or subsystem controllers within the same system.

Speculative execution of test patterns in a random test generator

Abstract: Presented is a computer-based test system and method for generating and improving the effectiveness of test cases for a model or an implementation of a computer architecture. The system includes an architectural model configured to model the requirements of the computer architecture and a behavior model configured to model the implementation of the computer architecture, wherein the behavioral model is designed to conform with the computer architecture. Further included is a simulator configured to simulate the operation of the behavioral model in response to a test pattern and to provide a behavioral model state. A random test generator is configured to test aspects of the architectural model and to generate and provide test patterns to the simulator according to the behavioral model state provided by the simulator. The random test generator provides the ability to store a pre-simulation behavioral model state and reset the simulator to the pre-simulation behavioral model state at a later time. The system may further include a history of previous events from which the rate at which an event occurs may be controlled.

System and method for on-chip debug support and performance monitoring in a microprocessor

Abstract: User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements. By changing data in the storage elements, the programmer may change the information against which the state of the nodes is compared and also the method by which the comparison is made. The output devices include counters. Counter outputs may be used as state machine inputs, so one event may be defined as a function of a different event having occurred a certain number of times. The output devices also include circuitry for generating internal and external triggers. User-configurable multiplexer circuitry may be used to route user-selectable signals from within the microprocessor to the chip's output pads, and to select various internal signals to be used as state machine inputs.

Method and apparatus for selective replay of computer programs

Abstract: A user can selectively replay portions of a computer program execution, so that the entire program need not be run again to support further test and debug. A run-time instrumented version of the program is created by inserting special instructions into the original program. The run-time instrumented version is executed to create trace files of memory accesses and system calls, as well as identification of interrupts. During execution of the run-time instrumented version, a state of each accessed memory location is monitored and updated to determine which memory accesses should be traced and when. This monitoring and updating is performed in a manner which minimizes interference with the execution. A user then may select a desired portion of the original computer program for replay and, in response, appropriate data is stored in corresponding memory locations so that the desired portion of the program may be replayed accurately.