Showing papers on "Switching time published in 1982"

Velocity-Modulation Transistor (VMT) : A New Field-Effect Transistor Concept

Abstract: Field-effect transistors of a completely new category are proposed and analysed, in which the conductivity modulation ΔG by the gate voltage Vg is brought forth mainly through the Vg-dependence of electron mobility. Since the sheet concentration of electrons in such FETs need not be modulated, the switching speed of the device is expected to be free from the transit time limitation, reaching the range of subpicosecond. As a specific example, an FET with a dual-channel configuration is discussed.

Ultra-fast field emitter array vacuum integrated circuit switching device

Abstract: A field-emitter switching device wherein a positive pulse is applied to a te (which is held at a bias potential V1 just below turn-on). A collector is held at a potential higher than the gate in order to collect emitted electrons from a field emitter source. As the voltage is applied to the gate, electrons are emitted immediately from the source and travel to the most positive potential at the collector. Because of the field emitter geometry, such electron transport is extremely fast. The ultra-fast switching speed is attained because the electrons reach near-maximum velocity within a few field tip diameters of the source.

New technology towards GaAs LSI/VLSI for computer applications

Abstract: For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed: self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HEMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).

Thermooptic deflection and switching in glass

Abstract: New types of active optical device in glass such as deflectors and modulators/switches using the thermooptic effect originating from the temperature dependence of the refractive index are proposed and demonstrated. Thermally induced index changes for light deflection and switching are provided by applying an appropriate voltage to a small film heater deposited on the glass surface. Thermooptic waveguide switches fabricated by the ion-exchange technique successfully exhibited a switching speed of the order of 1 msec with 0.5-W driving electric power.

Switching dynamics in a thin film recording head

Abstract: The switching dynamics in a thin-film head for both the writing and reading modes are studied To minimize magnetostatic energy, the film head is split up into multidomains subsequent to saturation writing in the hard (or track) direction The domain structure is composed of elongated domains in the easy direction and closure domains at the edges The results of our calculation show that domain wall motion contributes increasingly to the effective head permeability as the track width is decreased In the readback process, it was found that the switching time for wall motion τ w (∼170 ns) in the edge domains is some two orders of magnitude larger that τ r for rotation (∼1 ns) in the main domains Since these motions are coupled due to the requirement of continuity of the perpendicular component of \overrightarrow{M_{s}} at a 90° wall, the switching dynamics is dominated by wall motion A finite distribution of wall motion threshold field H o can give rise to different time delays in the head response, leading to distortions in the readback signal, including the presence of wiggles at the trailing edge

Optical bistable-switching operation in semiconductor lasers with inhomogeneous excitation

Abstract: Bistable operation is examined in the paper for DH semiconductor lasers employing inhomogeneous excitation. Steady-state rate equations are analysed in terms of typical parameters for contemporary stripe-geometry lasers, and it is shown that the I/L curves demonstrate bistability. Characteristics for optical bistable-switching operations effected by trigger current pulses are also numerically analysed through the use of nonlinear rate equations. Bistable operation has been achieved experimentally with InGaAsP/InP DH lasers through a newly designed periodic excitation stripe geometry. Bistability was observed within a current range less than 10° of the threshold current. The range was seen to strongly depend on the stripe geometry anddevice temperature, which are controllable. Switching between the two stable states was accomplished by application of an electrical pulse. Switching time was about 1 ns.

New Technology Towards GaAs LSI/VLSI for Computer Applications

Abstract: For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HFMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).

Digital-to analog converter having supplementary currents to enhance low current switching speed

Abstract: A bit cell is presented which can provide a small weighted current without loss of switching speed. The bit cell contains a switch which is responsive to an applied control signal to direct the weighted current to an output or to divert it away from the output. Supplementary currents are supplied to the switch to provide sufficient current to the switch to charge and discharge parasitic capacitances of the switch within the switching time of the control voltage. The supplementary currents maximize switching speed at a given power dissipation and produce a constant offset current at the switch output. A D/A converter is presented which utilizes a plurality of such bit cells to maximize the speed of D/A conversion. The offset currents are eliminated from the converter output so that the output current is proportional to the digital input.

Fractional-division frequency synthesizer for digital angle-modulation

Abstract: A FRACTIONAL-DIVISION FREQUENCY SYNTHESIZER FOR DIGITAL ANGLE-MODULATION Abstract of the Disclosure In order to deliver an angle-modulated output signal as a function of digital information, the frequency synthesizer delivers an output frequency FS = (N + k)FR, where N is the integral part of a number N+k and FR is a reference frequency. Provision is made for a variable oscillator, an oscillator control loop comprising in series a variable-rank divider prepositioned on the division rank N, a phase comparator for receiving the reference frequency and a summing device. The synthesizer further comprises a phase accumulator for performing at the frequency FRmodulo-M summation of a number G = k.M applied to its input. The sum and carry outputs of the accumulator are coupled respectively to the summing device in order to deliver a signal for compensating the signal delivered by the phase comparator and to the divider for delivering a control signal at N+1 of the division rank. An adder having one out-put coupled to the input of the phase accumulator receives a constant number g on one input and a number dg which is representative of the digital information on another input.

Normally-off type high speed SI-Thyristor

Abstract: The design, fabrication, and characterization of a normally-off type static induction thyristor (SIThy) with a surface gate structure were made with an intention to use it in high speed switching at high currents. The device chip had a size of 7 × 10 mm2and included 9,000 channels, where each channel stripe had a width of 1.5 \micro m and a length of 250 \micro m. The double LOCOS technique was used in the fabrication process of the device. By mounting the chips in specially designed packages, a very low forward voltage drop of 1.2 V at 100 A and a high switching speed of 300 ∼ 600 nsec in turn-on and turn-off times were obtained. A bipolar mode static induction transistor (BSIT) was also made by using the same photomasks and the same fabrication process as SIThy. It also exhibited a low forward voltage drop of 0.7 V at 100 A and a high switching speed of 100 ∼ 200 nsec in turn-on and turn-off times.

Frequency generator using composite digitally controlled oscillators

Abstract: A frequency generator for generating a large number of closely and evenly spaced frequencies over a large bandwidth including a first digitally controlled oscillator and a second digitally controlled oscillator, and a combiner for mixing the frequencies from said first and second digitally controlled oscillators, wherein the sampling rate of the digitally controlled oscillators differs by a small predetermined amount. Switching speed is extremely rapid.

GaAs to ECL level converter

Abstract: An improved high speed gallium arsenide (GaAs) to emitter coupled logic (ECL) voltage level converter is provided which consumes less power and also provides an improved speed-power product performance characteristic. The converter includes a three branch output circuit which emulates the operation of an ECL output driver. The emulator circuit causes faster switching by compensating for parasitic resistances and capacitance and is also provided with a gate discharge network which reduces switching time of the ECL output emulator.

Radio link remote control signaling system, and method

Abstract: To permit simultaneous transmission of command codes, in binary command words, with traffic or other announcements, being broadcast over an FM transmitter which has a 57 kHz subcarrier AM modulated by an announcement recognition (AR) signal, for example 125 Hz, use is made of the long response time of AR switching elements to provide, before the AR switching element (13) can respond, decoding of a command word at a clock rate which is fast with respect to the response time of the long switching time constant switching element (13). This fast response is, preferably, accomplished by a counter (18) which has only the number of count positions corresponding to the bits in the command word, then provides an overflow to block a memory (15) in which the bits are being stored; a second counter (20)--or a continuing portion of the counter--counting at the clock rate for a period of time longer than the response time of the switching element (13) to then cause unblocking of the memory, for subsequent reception of command words, which may occur during transmission of the AR signal, by merely short interruptions thereof, insufficiently long to prevent drop-out of the switching element (13) of the AR system. A decoder (30) is connected to decode the expected command words, but reject AR signals, the characteristics of both of which are known.

MOS FET switch - has triple wound input transformer with blocking oscillator

Abstract: The FET- switch has the options of the load being connected in the source- or drain - or both drain- and source circuits. It has a triple wound input transformer connected to source and gate with a blocking oscillator connected to its primary and secondary. An RC- circuit controls the switching time for inductive loads. The tertiary winding (5) of a triple wound transformer is connected to the MOS-FET power transistor (1) with a rectifier (6) in series and resistor (7) and capacitor (16) in parallel to control the switching time. The primary (10) and secondary (9) with transistor (8) form the blocking oscillator. Full wave rectifiers (18) provide an a.c. supply option.

A comparison of the performance of gold and platinum killed power diodes

Abstract: Measurements of leakage current, switching time and forward voltage drop are presented for gold and platinum killed devices. It is shown that under certain conditions improved switching performance may be obtained from platinum killed devices due to the lifetime profile produced at elevated temperatures by the shallow recombination centre. This interpretation of the experimental data is supported by results from a numerical model of diode switching. Other samples used in this study show that lifetime profiles resulting from a spatially non-uniform distribution of a deep impurity such as gold can have an equally strong effect upon the detailed switching characteristics.

Invited) The Potential for Bipolar VLSIs

Abstract: The possibility of using bipolar devices for high density VLSIs is discussed. Fundamental limitations involving the integration level, speed, power and packaging condition are stated. It is pointed out that the main difference between MOS and bipolar devices is the difference in switching energy. Bipolar devices' high transconductance at low operating voltages, resulting from strong non-linearity, is the key in surpassing MOS devices. The potential for I2L circuits in high speed, dense VLSIs is discussed. It is shown by computer simulation that a switching speed of 150 ps seems to be possible for submicron scaled I2Ls. Also an 80 k-gate VLSI with tpd=1.5 ns will be feasible with bipolar devices. An VLSI with such a construction can compete favorably with MOS VLSIs in density and performance.

Numerical Evaluation of Inductance Influences of Superconducting Lumped Circuit Interconnections on Ultrafast Switching Signal Propagation Characteristics

Abstract: The lumped inductance influence of superconducting circuit interconnection on ultrafast switching (~ 10 ps) signal propagation characteristics, such as propagation delay, degraded switching time, reflections, amplitude distortions, and crosstalk, were for the first time quantitatively evaluated by using the LNAP computer simulation, including the influences of matching capacitors and terminated resistor value.

Switching time between overt and covert speech: Generative attention

Abstract: Four experiments investigated a new phenomenon: the existence of a very large switching time effect that occurs from rapidly alternating between overt and covert (mouthed) speech. This is referred to as an intensity switching effect, and the time taken for each switch is, in itself, long enough for a spoken or mouthed character (letter or digit) to be produced. In Experiments 1 and 2, the intensity switching effect was shown to be different from the switching that occurs between categories of materials (letters and digits) because it is both much larger and much more resistant to practice effects. The intensity switching effect was also shown to be distinct from a memory load effect, since it holds even for perceptually available lists. In Experiments 3 and 4, the issue of a peripheral vs. a central origin of intensity switching was addressed. Evidence was found for a central origin. In addition, two models -of response intensity representation were contrasted: a symbolic or digital model, with intensity altered by parameter substitution, and an analog model, with intensity represented by a moving pointer on an intensity continuum. The results supported the symbolic model. It is concluded that the intensity switching effect is a measure of control processes at work in altering the intensity parameters of the vocal response system.

Circuit for a power FET transistor

Abstract: In the circuit according to the invention for a power field-effect transistor (1) switching an inductive load (L) and controlled via a drive resistor (4), the gate-drain path of the power field-effect transistor (1) is connected in parallel with a capacitor (2), the time constant of the RC section formed of drive resistor (4) and capacitor (2) determining the rate of voltage rise permissible for the circuit arrangement. This achieves a defined switching time extension by intervening in the control loop and the switching rate is almost exclusively determined by the time constant of drive resistor (4) and capacitor (2) and is largely independent, for example, of the load (L) to be switched and of usual manufacturing tolerances of the power field-effect transistor (1).

Control device for ac motor

Abstract: PURPOSE:To stabilize a load drive without reducing the capacity of a motor by switching a power source to the motor in response to the variation in the frequency. CONSTITUTION:A variable frequency power converter 14 is provided between a commercial power source and an AC motor 12, which are connected via a switch 16, and a bypass circuit 20 having a switch 18 is provided for the converter 14. The switches 14, 18 are switched by a switch controller 22 to connect the motor 12 to the commercial power source 10 in the rated frequency range of the motor, and to connect the motor 12 to the converter 14 in the range of the frequency lower than the prescribed value. Thus, the phase difference between the voltage of the motor and the voltage at the power source can be eliminated at the switching time.

Optical waveguide 2 × 2 matrix switch using dielectric chip motion

Abstract: Input and output light angles in a total internal reflection optical waveguide switch, in which a guided light beam is switched by dielectric chip contact with a low-index channel built in a waveguide film, are studied to construct a matrix switch. Output angle depends on channel width, chip contact width, chip position, and input angle. In a single switch experiment, the output angle is larger than the total reflection critical angle for the channel due to narrow chip contact width. By utilizing this property, a nonblocking 2 × 2 matrix switch, driven by PZT bimorphs, is fabricated. Insertion losses of 2.9-6.0 dB, cross talk values of 10.8– 28.1 dB, and switching time of 6 msec are obtained for the TE0 mode at 0.633-μm wavelength.

Analysis and Design of High-Power Rectifiers

Abstract: In this paper all aspects of the design and analysis of high-power rectifiers are pre­sented. In the first section, the results of a study are given which identify the limit­ing physical mechanisms affecting forward drop in power rectifiers. In the second sec­tion, the effect of packaging variations on surge and steady-state device ratings is investigated. In the third section, the effect that gold, platinum, and electron irradia­tion have on the switching speed, forward drop and “snappiness” of power rectifiers is analyzed using a method to directly measure the free-carrier concentration while the device is switching. Device analysis, wherever presented, is made using an exact numerical model in one dimension which allows for temperature- and time-dependent cal­culations on devices imbedded in inductive switching circuits.

Output switching device

Abstract: PURPOSE:To achieve switching from one signal source to the other without interrupting a wave, to shorten the switching time and to solve problems such as the generation of heat, by varying the extent of phase shifting by 90 deg. through a variable phase shifter and a quarter-wavelength line. CONSTITUTION:A variable phase shifter 41 capable of varying the extent of phase shifting by 90 deg. is connected between terminals (2) and (1) of hybrid circuits 21 and 22, and a variable phase shifter 42 is connected between terminals (4) and (3) of the hybrid circuits 21 and 22 through a fixed line 43 which has longer line length than the one-quarter wavelength of an in-use frequency. Then the switching between broadcasting equipments 26 and 28 which supply electric power to an antenna 27 is performed while the extents of phase shifting of the phase shifters 41 and 42 are set to 90 and 0 deg. respectively and the electric length theta1 between the terminal (2) of the hybrid circuit 21 and the terminal (1) of the hybrid circuit 22 is equalized to the electric length theta2 between the terminal (4) of the hybrid circuit 21 and the terminal (3) of the hybrid circuit 22, or while the extents of phase shifting of the phase shifters 41 and 42 are set to 0 and 90 deg. and a 180 deg. phase difference is given between said electric length theta1 and electric length theta2.

Drive circuit for electrochromatic display cell - has switching circuit to reverse current during write and erase operations without cell damage

Abstract: The drive circuit for an electrochromatic display cell is designed to avoid cell damage and to minimise the switching time of the cell. The display cell (1) has a back electrode and a number of individual segment electrodes. The circuit consists of two stages, one for writing and one for erasing. The circuit has a pair of contacts (16) that are switched to distinguish between write and erase operations. A clock (15) applies pulses to the clock inputs of flip flops (11,25) that are feedback coupled to NAND gates (7,17) connected over switches (3,21) to comparator (2,22) stages. The circuit operates to reverse current direction when changing from a write to an erase operation.

Quasiparticle-Injected Superconducting Weak Link Device

Abstract: This paper concerns a new three terminal superconducting weak link device, having a third electrode attached to the weak link part for injecting quasiparticles. The structure, the fabrication procedure and the result of the measurement of its static I-V characteristics are presented. As a result, a current gain larger than that of any other Josephson switching devices is obtained. It is found that the larger current gain depends strongly upon the input resistance between the third electrode and the weak link part. The switching speed of the device is also theoretically discussed.

Pulse switching controlling method for pulse width modulation type inverter

Abstract: PURPOSE:To enable the smooth torque control of an induction motor by reducing the variation in the fundamental wave voltage and the displacement in the phase at the switching time when a PWM inverter is switched between 3-pulse and 1-pulse modes. CONSTITUTION:A source oscillation frequency f0 is counted by a counter 10, is stored in ROMs 11-13, is compared with a DC voltage VC by D/A converters 14-16, and modulation pulse is formed under the exclusive OR conditions 20-22 with the respective phase fundamental wave pulses. The resetting circuit 23 of the counter 10 is switched at the time of switching between 3-pulse and 1-pulse modes, thereby reducing the variation in the effective value of the fundamental wave voltage, and the displacement of the phase can be reduced by the signal from a lead 1-pulse clock generator. Accordingly, the current jump at the switching time can be reduced, thereby reducing the conversion capacity of the inverter and controlling the smooth torque of a motor.

Rectifier for driving motor

Abstract: PURPOSE:To enable to shorten the wasteful switching time irrespective of load characteristics by increasing the gain of a current controller when a converter is switched in a speed controlling circuit having both positive and negative direction converters. CONSTITUTION:A current controlling loop having a sequential current controller 9 and a voltage controlling loop having a voltage controller 13 are provided within the speed controlling loop of the speed controlling circuit of a DC motor 2 having a positive side converter 3 and a negative side converter 4 connected in antiparallel to one another, and the gate pulse generator 17 of the converter and a normal and reverse switching logic circuit 18 are controlled by the output of the controller 13. A zero current detector 25 is provided in the current controlling loop, the zero time point of a main circuit current is detected when the positive and negative converters are switched, while the gain of the current controller 9 is increased in accordance with the detection signal, and the wasteful switching time can be shortened.

A new, high speed, unique switch

Abstract: An effort was made to devise a new semiconductor switch which has the switching speed of the emitter-open switching, but only requires a standard base drive configuration (see figure 1 for my definition of standard base drive). The result of the research is a new semiconductor switch which achieves higher switching speed than emitter-open switching, lower forward voltage drop (particularly for very high current applications, involving hundreds of amperes), considerably lower cost, and uses more readily available parts. It is free from reverse biased secondary breakdown, a predominant mode of failure of many semiconductor switches.