Showing papers on "System bus published in 1983"

Modular computer system

Abstract: A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas. The transfer of the supervisor function from processor to processor is performed by registering the supervisor's identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors. Access to the common system bus by the processing elements is controlled by the associated interface units by means of a combination serial/parallel arbitration scheme which increases arbitration speed without requiring a full complement of request/grant leads.

High speed parallel bus and data transfer method

Abstract: A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.

Access control method for multiprocessor systems

Abstract: In ma multiprocessor system, a data transferring port (7), into which data can be written only when no data is stored and from which data can be read only when it is stored, is provided and the port (7) itself is caused to perform an exclusion control, whereby that processor (2, 3) of a plurality of processors (2, 3) which has once acquired a bus (5) mastership is prevented from making another bus use request until the bus use requests of the other processors (2, 3) run out.

Self configuring computer network with automatic bus exchange of module identification numbers and processor assigned module numbers

Abstract: In a computer network having a system bus, a system processor connected to the system bus, and a plurality of local processors each connected to a respective local bus each having a plurality of interface cards attached thereto, each interface card includes an identification ROM. Each interface card responds to an initial reset signal enabling that interface card to respond to the same initial address. Each local processor outputs that initial address. The closest interface card of each local bus responds by transmitting information from its identification ROM to the requesting local processor, which then assigns an address to the closest interface card, which then automatically sets circuitry that enables the next closest interface card to respond to the initial address. The procedure is repeated to assign unique addresses to all of the interface cards.

Process control system with improved fault isolation

Abstract: A process control system includes redundant digital controllers and a plurality of input/output (I/O) modules for interfacing with remote field sensors and actuators. Bi-directional communication between controllers and I/O modules is achieved by a parallel wired, process I/O bus. Failures within the system, including the bus structure itself, that continually keep the bus active (i.e., in a low state) are isolated by a combination of software diagnostic routines for performing bus checkout and a unique quick disconnect feature that readily isolates the fault condition first between the I/O module nest area and the controllers, then, if necessary, to individual I/O modules. During fault isolation procedures, individual I/O modules may be disconnected from the bus while the values of field signals are simultaneously maintained to provide minimum process upset.

Information display system

Abstract: An information display system comprising a computer device having at least one input member for receiving video information and a processor member connected to said input member for processing and/or controlling digital video information contained in and/or obtained from the video information received from the input member and/or digital video information produced by the computer device itself in order to produce display data and control-signals, a communication channel comprising a data bus connected to the processor member of the computer device and a control bus for the transmission of the display data and the control-signals respectively, a memory device connected to the data bus for storing display data received from the data bus, a memory control-device connected to the control bus for controlling the storage of display data in and reading stored display data from the memory device in response to control-signals received from the control bus, a digital/analogue converting device connected to the memory device for producing analogue display signals during reading of the memory device and at least one display panel consisting of a plurality of electronic display units arranged side by side in a manner such that the respective display surfaces together constitute the display surface of the display panel.

Circuits for accessing a variable width data bus with a variable width data field

Abstract: A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width Nc and a data field of Nf, the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field Nf extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. The structure includes a modulo Nc combinational ring shifter for aligning the data field with the data bus. An overflow signal generator is provided using a subtraction circuit wherein the data field width is subtracted from the data bus width between alignment bit n and the end bit Nc. A negative subtraction result indicates overflow and the magnitude of the result specifies the bit positions from bit 1 of the data bus for the wrapped around bits. A select signal generator including two decoders is provided to indicate the valid data bit positions of the data bus.

Transceiver having collision detection capability for contention-formatted FDM local area networks

Abstract: A transceiver provides data collision detection and avoidance in a contention-formatted, FDM communications network using FSK modulation. Locally-generated baseband data is compared to recovered baseband data received from the system bus. A failure to compare indicates that there has been a data collision. The wide disparities in amplitude between locally-generated FDM signals and signals received from the bus are accommodated by a signal splitter which provides greater attenuation of the local signal than the generally weaker bus signal, and by the use of logarithmic amplifiers which generate relatively constant output levels for a wide range of input signal amplitudes. Collision avoidance is provided by monitoring the bus signal demodulators for data activity, and by inhibiting the local transmitter when such activity is detected, subject to an override during transmission by the local station.

Eye-tracker communication system

Abstract: A system for computer vision comprises a source of digitized video signals and a frame encoder circuit connected to the source of digitized video signals. The frame encoder encodes threshold crossing events at at least two threshold levels and stores encoded data for a two-dimensional area within the frame in a cache memory. The threshold levels are programmable. A computer is in communication with the encoder circuit at least via its data bus and address bus for programming the threshold levels and controlling the encoder and accessing the data in said cache memory. The computer has an associated main memory with a stored task for reading the cache memory and interactively controlling the frame encoder circuit and interpreting the data gathered thereby. Data is encoded by event type and pixel address wherein the event type is indicative of threshold crossed and direction of crossing. The task stored in main memory has an algorithm for continuously changing the threshold levels and analyzing the data in successive frames until the desired threshold levels are achieved.

Distributed data transfer control for parallel processor architectures

Abstract: An apparatus for distributing the control of data transfers within single instruction stream multiple data stream processors. Each of the parallel processors or arithmetic units is coupled to a dedicated local memory. A main memory provides storage of system data. Each dedicated local memory and the main memory are coupled to a bus interface unit. Each bus interface unit is coupled to a common data bus for the transfer of data between the main memory and the dedicated local memories. Each bus interface unit provides the control functions required to transfer data between the common data bus and the main or local memory to which it is coupled. One bus interface unit is designated the resource controller. The resource controller performs all of the functions of a bus interface unit and also provides the system level functions of supplying clock signals and performing bus arbitration. Each bus interface unit is capable of managing transfers to and from its associated memory thereby distributing control of the multiple data streams eliminating the potential problems associated with requiring a single controller to manage these parallel data transfers.

Memory controller with synchronous or asynchronous interface

Abstract: A common memory interfacing circuit and method for coupling a memory to either a synchronous bus or an asynchronous bus. Synchronizing means are provided for synchronizing memory request signals with a local clock when the interfacing circuit is coupled to an asynchronous bus. The interface circuit responds to signals from the memory when internal memory operation has been completed and generates an acknowledge signal to send to the requesting bus. To simplify the common interface circuit, a synchronous protocol for information exchange between system components is made similar to an asynchronous protocol.

Multiplex bus system for controlling the transmission of data between a master control unit and a plurality of remotely located receiver-transmitter units

Abstract: A multiplex bus system comprises a master control unit (MCU) connected to at least one receiver-transmit unit (RTU) by a data bus. The MCU transmits to the RTU a message comprising a synchronization pulse of known duration and successive time spaced timing signals separated by time duration T marking the boundaries of data bits to be transmitted from the RTU to the MCU. The RTU includes a clock pulse source which utilizes the synchronization pulse to determine the frequency of the clock pulse source in P pulses per duration T. The value P is used in conjunction with the timing signals to create properly timed data determining signals in the data bits.

Data processor having multiple-buffer adapter between a system channel and an input/output bus

Abstract: A data processor has a block-multiplexed system channel coupled to a processing engine and a byte-multiplexed bus coupled to multiple I/O devices. A multi-buffer adapter transfers data by cycle-steal (direct memory access) operations between the channel and the bus. The adapter has multiple buffers switchable to the channel in a burst mode by a channel interface and to the bus in a byte mode by a device-level interface.

Bus master capable of relinquishing bus on request and retrying bus cycle

Abstract: A bus master is provided with the capability to accept a data transfer task from a CPU, which includes the performance of a predetermined sequence of data transfer operations between memory and a selected peripheral controlled by a respective controller. During any one of the operations, the bus master may be requested to relinquish the bus so that a higher priority transfer may occur or a deadlock condition resolved. In response to such request, the bus master immediately terminates the current bus cycle, but remembers the state thereof at the time of relinquishment. After the high priority transfer is completed, the bus master may be allowed to rearbitrate for use of the bus. Upon again obtaining control of the bus, the bus master restarts the bus cycle which was prematurely terminated and continues the sequence of operations as if no relinquishment had occurred.

Multiprocessor supervisory control for an elevator system

Abstract: An elevator system, and method of monitoring same, which includes a plurality of elevator cars under the group supervisory control of at least first and second processors, which all share a common memory over a system bus. The first processor periodically monitors its own status, and it sets a predetermined location of the shared memory each time it finds its status to be normal. The second processor periodically checks the predetermined location, and upon finding it set, it resets it. The second processor also monitors its own status. The second processor triggers a retriggerable hardware timer each time it determines that the first processor and itself are both operating normally, with the trigger rate preventing the timer from reaching the end of a predetermined timing period. When the second processor finds the status of either processor to be abnormal, it terminates its triggering of the timer. The timer then provides a signal at the end of its timing period, which reinitializes both processors.

Deadlock detection and resolution scheme

Abstract: @ in a communication system which includes a plurality of stations (23,24) interconnected for communications by a first bus (21), a second station (22) includes a device, such as a processor (25), and a resource, such as a memory (32) or a peripheral unit, interconnected for communication by a second bus (36) An interface mechanism (34) connecting the first bus with the second bus allows the device to access the first bus over the second bus, and allows a first station to access the resource via the first and second buses Deadlock detection circuitry (47) detects cotemporaneous attempts by the device to access the first bus and attempts by the first station to access the resource Deadlock resolution circuitry (26) responds to deadlock detection by disconnecting the device from the second bus to allowthe first station to access the resource, and by reconnecting the device to the second bus when the first station ceases to access the resource If the device is operating under program control, the deadlock detection and resolution are transparent to the program (Fig 1)

Fault-tolerant power supply system

Abstract: A power supply system for use in a fault-tolerant computer having a main bus interconnecting several main bus elements, with at least one of the elements being capable of transmitting commands and receiving status information. The system includes a status bus which is coupled to the main bus. A control unit is associated with each bus element, such control unit including a voltage regulator connected to a primary source of power for providing regulated voltage to the associated bus element in response to commands received over the status bus from the main bus. The primary power source preferably includes redundant power supplies which provide voltage which is distributed over a pair of redundant voltage buses. Apparatus for sensing when a main bus element has seized the main bus may be included so that the bus element can be commanded by way of the status bus to release the main bus.

Image processing system

Abstract: An image processing system is disclosed which includes: a control computer (10) which has a CPU (14) and a main memory (16) therein; and an image memory section (12) which is connected to the CPU (14) through an interface (26) and which has an image memory (20) for digitally storing image data, a memory controller (44) and an image processor (50). A memory area (16a) as part of the main memory (16) is independently allocated to store as a register area data transferred through a privately leased data bus (28) which bypasses the interface (26) between the control computer (10) and the image memory section (12). When random access operation of the image data with respect to the image memory (20) is performed, the data transfer between the CPU (14) and the image memory section (12) can be performed through the memory area (register area) (16a) and the special data bus (28) without going through the interface (26).

Serial/parallel input/output bus for microprocessor system

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines For a given set of addresses parallel data transfers occur and for a different set of addresses serial data transfers occur A single instruction may transfer one bit, multiple bits in series, or bytes or words in parallel; the serial or parallel mode is specified by the address, so software may be written without regard for the type of interface This serial/parallel I/O port shares the address/data bus with memory and may be used with any memory-mapped peripheral

Multiprocessor computing system featuring shared global control

Abstract: A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space: a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus. Each station's station bus is selectively interfaced to the system bus, and a station accesses an addressable element of another station by placing its dedicated subspace address on the station bus, interfacing its station bus with the system bus, and causing the other station to interface its station bus with the system bus. A station accesses an element of another station passively, without utilizing the intelligence, if any, of the other station to make the access.

Semiconductor memory device

Abstract: PURPOSE:To realize various types of protective functions of the memory by a small quantity of units, to set the conditions to prevent the rewriting by providing the memory element for protective information, the temporary memory register of protective information and the address decision circuit, etc. CONSTITUTION:When a chip selecting signal 43 and an address 41 are given, the contents of a memory element 151 for the data and a memory element 152 for protective information are read by respective sense amplifiers 341 and 342. The output of the amplifier 342 is set to a register 37 to store temporarily the protective information, and when the output 47 is '1', the data are read onto a data bus 42. When the output 47 of the protective information is '0', a driver 351 is controlled, the output is prohibited and the data are not sent to the bus 42. By adding the address decision circuit, the writing preventing data latch circuit, and the deleting preventing data latch circuit, the conditions to prevent the rewriting can be set. Namely, various types of the protective functions of the memory can be realized by a small quantity of the units and the conditions to prevent the rewriting can be set.

Multiprocessor computer system utilizing a tapped delay line instruction bus

Abstract: The disclosure is directed to a multiprocessor data processing system. The data processing system of the invention generally comprises a plurality of microprocessor units and an instruction memory device electrically storing a common set of instructions in a pre-ordered sequence, each of said instructions being stored in representative, digital, electrical signal form. A tapped delay line instruction bus system is provided to electrically interconnect the instruction memory with each of the microprocessor units. The tapped delay line instruction bus system includes a plurality of individual tap buses and electrical controls operable to apply the digital electrical signals for each of the instructions stored in the instruction memory device to each of the individual tap buses, one tap bus at a time, in a timed, time-skewed sequence. Each of the plurality of microprocessor units is electrically connected to one of the individual tap buses of the tapped delay line instruction bus system whereby each of the microprocessor units receives the representative electrical signals for each of the instructions stored in the instruction memory device pursuant to a pre-ordered, timed sequence.

A communication structure for a multiprocessor computer with distributed global memory

Abstract: An experimental multiprocessor computer was designed and built in order to explore the feasibility of certain internal communication mechanisms The system consisted of seven processing elements, each containing a part of the global memory connected to a local bus For each processor the global memory is seen as one single, linearly addressable structure The processing elements were all connected to a common, global bus, consisting of three separate busses in order to increase the capacity A bus selection unit was designed, capable of making a unique bus selection for each request, within a fraction of a memory cycle The experiments have shown that communication structures based on distributed global memory and global bus systems can be used efficiently for medium scale systems

A synchronisation mechanism for a multiprocessing system

Abstract: A synchronisation mechanism is disclosed for controlling devices or sub-systems connected to a common bus in a multiprocessing system so that the devices are kept in step one with the other when performing sequences of operations. More specifically, the mechanism ensures that no device can start its (i + 1)th operation until all devices have completed their ith operation. This is achieved by providing each device with three synchronising logic blocks (LB1, LB2, LB3) each of which functions to generate control signals (p, q, r respectively) on associated control lines at the end of selected operations in the sequence of operations. The control lines monitoring the performance of corresponding operations in all the devices are each applied via logic circuits (L or L2 or L3 as appropriate) to one of three selected bus lines (P, 0, R respectively). The logic circuits operate to produce a bus control signal on the selected bus line only when all of the corresponding operations have been completed by all the devices. As soon as a bus control signal is generated on one of the bus lines all devices start performing the next operation in the respective sequences.

A data processing apparatus and method for use in speech recognition

Abstract: A speech recognizer is disclosed which includes a number of processors (110,130, 140,150,160) each having a shared memory (406) associated therewith. Each processor performs local processing tasks on data stored in the associated shared memory. The data stored is distributed by direct memory access during and without interfering with local processing of the remaining data stored in the shared memories. A plurality of circuits are connected to a shared data bus (412) for effecting the data transfer across the shared data bus. A remote controller (447) controls transfer of data across a remote bus (450). A shared controller (440) includes synchronization circuitry (1100) for synchronizing shared data bus requests with the timing of the local processor, and priority circuitry (1000) to insure that the local processor always has access to the shared memory (406) through the shared data bus (412) without waiting. When used in continuous speech recognition, a front end processor (110) is employed for converting digital spectral speech data to frames of parametric data more suitable for further speech processing; at last two template processors (130, 140, 150) are employed to store the recognizable vocabulary as templates and for comparing the frames of parametric data individually with the stored templates; and a master processor (160) is employed to transfer new frames of parametric data to the template processors and to redistribute templates among the template processors for more efficient processing in response to analysis of the results of template comparisons.

Remote control apparatus

Abstract: OF THE DISCLOSURE Remote control apparatus for controlling a number of equipment in which each unit includes a microprocessor which produces a first remote control signal on its data bus line and an interface circuit including a first latch circuit which receives the first remote control signal from the data bus line of the microprocessor and a second latch circuit which receives a second remote control signal on its input terminal and transfers the second remote control signal to the data bus line of the microprocessor, a common input/output terminal receives the first and second remote control signals and a switching means is connected between the common input/output terminal and a reference point such as ground and the switching means is controlled by the first remote control signal to pass it to the common input/output terminal. .. .. .. . . .. ... .. .. ..

A programmable NMOS DRAM controller for microcomputer systems with dual-port memory and error checking and correction

Abstract: An NMOS DRAM controller for use in microcomputer systems based on the iAPX-86 and iAPX-286 microprocessor families or on the Multibus system bus is described. The controller provides complete support for dual-port memories and memories with error checking and correction. The controller has programmable attributes for configuring it to the particular requirements of the system. The controller uses parallel arbitration to minimize arbitration delay. A memory cycle will start on the same clock edge that samples a command if the cycle has been previously enabled. Novel logic and circuit design techniques have been used to achieve 16 MHz operation, 20 ns input setup time, and 35 ns output delay time.

I/o channel bus.

Abstract: A data bus system utilizing logical transfer channels provides high data rates (even over long distances) and good error detection. The basic function of a transfer channel is to enable temporary assignment of some portion of the bus resource to a specific device and then to allow simple, quick addressing of that device by reference to that channel. There are a relatively small number of transfer channels (say four) that may be attached or detached by the channel processor (IOCP) to meet the data flow requirements. For a transfer to occur between the IOCP (15) and a device (30a, 30b), the IOCP (15) first effects an "attach" operation to assign the device (30a, 30b) a transfer channel for the duration of the transfer. Thereafter, the IOCP (15) allocates the bus cycles among the currently attached transfer channels according to any desired priority scheme, subject to the constraint that the device on a transfer channel be ready to send or receive data before that transfer channel may be granted cycles.

Asynchronous multiport parallel access memory system for use in a single board computer system

Abstract: A data processing system includes an asynchronous parallel multiport volatile main memory system accessible directly by any one of M number of central processing units or by I/O controllers connected in common to any one of N number of system buses Priority resolver circuits award access to main memory on a predetermined priority basis Each port includes address, data in, data out, timing and control circuits which operatively couple to the priority resolver circuits The circuits of each port and the central processing unit or system bus I/O controllers associated therewith operate independently of each other in an asynchronous manner to access and store data and to report errors

Method for extending a parallel data bus

Abstract: A bus extender which accepts data from a parallel data bus and extends the bus by means of a serial link to another parallel bus. The bus extender comprises a local and remote station or terminal, each having a transmit and receive section. A transmit terminal receives a data frame from the parallel bus and decomposes the frame into data and management sub-frames. The local and remote terminals exchange management sub-frames, thereby starting the transmission process. A data sub-frame is then transmitted from the local to the remote station and a management sub-frame is returned from the remote station indicating receipt of the data sub-frame. Other sub-frames may be exchanged for specialized purposes, such as polling and error signalling. Specialized messages may be identified by tagging sub-frames with message codes. At the remote station, the original management and data bits are reassembled into a single data frame with placement of the bits in the same order as originally appeared at the local station. The new frame is then transferred on the data bus with all bits in parallel. The bus extender appears transparent to the two parallel bus sections.