Showing papers on "System bus published in 2001"

Apparatus for data copyright management system

Abstract: A data copyright management apparatus for handling data copyrights, and data of digital cash and video conference system is provided The data copyright management apparatus comprises a CPU, ROM, EEPROM, and RAM The ROM, EEPROM, and RAM are connected to the CPU bus, and a system bus of a device which utilizes the data can be connected to the CPU bus A data copyright management system program, cryptographic algorithm, and user information are stored in the ROM, and a first public-key, a first private-key, a second public-key, a second private-key, a first secret-key, a second secret-key, and copyright information are stored in the EEPROM The data copyright management apparatus may be configured in the form of a monolithic or hybrid IC, a thin IC card, PC card, insertion board, and further, may be incorporated in a computer, television set, set-top box, digital video tape recorder, digital video disk recorder, digital audio tape apparatus, or personal digital assistants, and the like

Method and apparatus for incorporating a multiplier into an FPGA

Abstract: One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.

Memory bus termination with memory unit having termination control

Abstract: Methods and apparatus for a memory system using line termination circuits in each memory unit (e.g., integrated circuit memory device) are disclosed. The memory unit contains termination control logic that sets the state of a controllable termination circuit to control reflections on the data bus. The termination control logic determines the proper state for the termination circuit from the state of its memory unit, and in some cases, from the approximate state of the data bus as gleaned from commands decoded from the command/address bus. A termination configuration register on the unit can be used to define the appropriate termination state for each unit state and/or data bus state.

Reducing bus delay in submicron technology using coding

Abstract: In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed wire model or a lumped capacitive coupling between wires. In this paper we extend the Elmore delay to account for a distributed model with distributed coupling component and an arbitrary number of lines driven by independent sources. The effect of data patterns is taken into account allowing us to estimate the delay on a sample by sample basis instead of making a worst case assumption. Using this detailed wire delay model, we propose a technique to speed up the communication through a data bus using coding. The idea is to encode the data being transmitted through the bus with the goal of eliminating certain types of transitions that require a large delay. We show that by using proper encoding techniques, the bus can be sped up by a factor of 2.

I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

Abstract: A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

System and method for automated monitoring and assessment of fabrication facility

Abstract: A method for monitoring and assessing operation of a semiconductor fabrication facility comprises the steps of connecting a monitoring and assessment system to a system bus which is connected directly or indirectly to a manufacturing execution system and a plurality of semiconductor fabrication tools. Through a user interface, the state models can be configured for the semiconductor fabrication tools where each state model is based upon a set of defined triggers for each tool. During monitoring various messages are transmitted on the system bus between the semiconductor fabrication tools and the manufacturing execution system and the monitoring and assessment system, and appropriate triggers are generated based upon the messages where the triggers are selected from a set of defined triggers. During operation, the state models are updated for each tool affected by one of the triggers and transitions within the state models are recorded in a tracking database.

Data communication apparatus for computer intelligent network interface card which transfers data between a network and a storage device according designated uniform datagram protocol socket

Abstract: An interface device is connected to a host by an I/O bus and provides hardware and processing mechanisms for accelerating data transfers between a network and a storage unit, while controlling the data transfers by the host. The interface device includes hardware circuitry for processing network packet headers, and can use a dedicated fast-path for data transfer between the network and the storage unit, the fast-path set up by the host. The host CPU and protocol stack avoids protocol processing for data transfer over the fast-path, freeing host bus bandwidth, and the data need not cross the I/O bus, freeing I/O bus bandwidth. Realtime audio and video communication can also be provided when the interface device is coupled by an audio/video interface to appropriate communication devices, such as microphone, a speaker, a camera and/or a display.

The IEC/IEEE train communication network

Abstract: Railway operators and manufacturers have standardized a data communication network that interconnects programmable equipment between and within rail vehicles. This data bus architecture offers a basis for standardization of future railways applications.

A comparison of five different multiprocessor SoC bus architectures

Abstract: The performance of a system, especially multiprocessor system, heavily depends upon the efficiency of its bus architecture. In System-on-a-Chip (SoC), the bus architecture can be devised with advantages such as shorter propagation delay (resulting in a faster bus clock), larger bus width, and multiple buses. This paper presents five different SoC bus architectures for a multiprocessor system: Global Bus I Architecture (GBIA), Global Bus II Architecture (GBIIA), Bi-FIFO Bus Architecture (BFBA), Crossbar Switch Bus Architecture (CSBA), and CoreConnect Bus architecture (CCBA). The performance of these architectures is evaluated using applications from wireless communications-an Orthogonal Frequency Division Multiplexing (OFDM) transmitter-and from video processing-an MPEG2 decoder. To increase performance, these bus architectures employ a pipelined scheme, resulting in improved throughput. While all five bus architectures perform well, we find that BFBA and CSBA perform the best for the OFDM transmitter and the MPEG2 decoder, respectively.

A Comparison of Five Different Mu It i processor SoC Bus Architectures

Abstract: The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. In System-on-a-Chip (SoC), the bus architecture can be devised with advantages such as shorter propagation delay (resulting in a faster bus clock), larger bus width, and multiple buses. This paper presents five different SoC bus architectures for a multiprocessor system: Global Bus I Architecture (GBIA), Global Bus I1 Architecture (GBIIA), Bi-FIFO Bus Architecture (BFBA), Crossbar Switch Bus Architecture (CSBA), and Coreconnect Bus architecture (CCBA). The pedormance of these architectures is evaluated using applications from wireless communications - an Orthogonal Frequency Division Multiplexing (OFDM) transmitter - and from video processing - an MPEG2 decoder. To increase performance, these bus architectures employ a pipelined scheme, resulting in improved throughput. While all five bus architectures perform well, we find that BFBA and CSBA perform the best for the OFDM transmitter and the MPEGZ decoder, respectively.

Fringe field switching mode liquid crystal display

Abstract: Disclosed is a fringe field switching mode liquid crystal display. The fringe field switching mode liquid crystal display of the present invention comprises a transparent insulating substrate; a plurality of gate bus line arranged in selected direction on the transparent insulating substrate, the gate bus line is arranged so that each element of the pair separated at a first distance is arranged a plurality of pairs at a second distance wider than a first distance; a plurality of common bus lines arranged on the centers of each gate bus line separated at the second distance, being in parallel with the gate bus line; a plurality of data bus lines arranged crossing with the gate bus line and common bus line to define a unit pixel; a thin film transistor disposed at the intersection of the gate bus line and data bus line; a counter electrode disposed in a unit pixel area and made of a transparent conductor, being in contact with the common bus line; and a pixel electrode overlapping with the counter electrode in the unit pixel and made of a transparent conductor, being in contact with the thin film transistor.

Method for the acceleration and simplification of file system logging techniques using storage device snapshots

Abstract: This invention presents a method and system to emulate logging or journaling file systems by means of a snapshot mechanism. Use of the snapshot mechanism reduces the number of system bus calls during log or journal updates and recalls in case of file recovery. The snapshot mechanism is implemented in hardware to provide for speedy and reliable data transfers. Overall system performance thereby is improved with an average reduced number of calls to the system memory bus. The present invention offers a cost effective way of retrofitting existing file systems with a journaling or logging capability.

Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection

Abstract: A method and associated apparatus is provided for improving the performance of a high speed memory bus using switches. Bus reflections caused by electrical stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a segmented bus wherein bus segments are connected through switches. The switches disconnect unused bus segments during operations so that communicating devices are connected in an substantially point-to-point communication path.

Universal serial bus peripheral bridge with sequencer

Abstract: A Universal Serial Bus to parallel bus bridge includes a Universal Serial Bus port that receives a serial bit stream of data and commands in a Universal Serial Bus protocol from a USB host computer. A parallel bus port on the bridge includes parallel port registers and state machines coupled to a peripheral device. A USB controller core is coupled between the Universal Serial Bus port and the parallel bus port and converts data and commands between the Universal Serial Bus protocol and the parallel bus protocol. A sequencer is coupled between the USB controller core and the parallel bus port. A sequence of sequencer commands is loaded into memory in the USB bridge and used by the sequencer to perform a sequence of parallel port operations. The sequencer performs the commands autonomously without intervention from the USB host computer. Because the host computer does not have to initiate a USB transaction for each individual parallel port operation, the sequence of operations is completed in a shorter amount of time.

In plane switching mode liquid crystal display device and method for manufacturing the same

Abstract: Disclosed is an in plane switching (IPS) mode LCD device and method for manufacturing the same. The IPS mode LCD device of the present invention includes a transparent insulating substrate, a gate bus line and a data bus line arranged in a cross fashion on the transparent insulating substrate to define a unit pixel area, a common electrode line disposed in parallel to the gate bus line while being spaced at most apart from the gate bus line in the unit pixel area, the common electrode line having a pair of shields respective disposed at both lateral edges of the unit pixel area, a thin film transistor disposed near an intersection of the gate bus line and the data bus line, a counter electrode arranged in the unit pixel area between the shield of the common electrode line and made of a transparent conductor, the counter electrode including a plurality of branches arranged in parallel to the data bus line, and a bar contacting the common electrode line and connecting respective one-side ends of the branches together, and a pixel electrode formed of a transparent conductor and including a pair of first electrode parts respectively overlapping with the shields of the common electrode line while extending in parallel to the data bus line, second electrode parts interposed each between adjacent ones of the branches included in the counter electrode, and a third electrode part contacting a part of the thin film transistor while connecting together respective one-side ends of the first and second electrode parts.

Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system

Abstract: A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle. The Transaction Controller monitors the Transaction Bus, maintains a set of duplicate cache-tags for all CPU/Cache modules, maps addresses to Target devices, performs centralized cache control for all CPU/Cache modules, filters unnecessary Cache transactions, and routes necessary transactions to Target devices over the Transaction Status Bus. The Transaction Status Bus includes both bus-based based and point-to-point control of the target devices. A modified rotating priority scheme is used to provide Starvation-free support for Locked buses and memory resources via backoff operations. Speculative memory operations are supported to further enhance performance.

Router line card protection using One-for-N redundancy

Abstract: Router line cards are partitioned, separating packet forwarding from external or internal interfaces and enabling multiple line cards to access any set of external or internal data paths. Any failed working line card can be switchably replaced by another line card. In particular, a serial bus structure on the interface side interconnects any interface port within a protection group with a protect line card for that group. Incremental capacity allows the protect line card to perform packet forward functions. Logical mapping of line card addressing and identification provides locally managed protection switching of a line card that is transparent to other router line cards and to all peer routers. One-for-N protection ratios, where N is some integer greater than two, can be achieved economically, yet provide sufficient capacity with acceptable protection switch time under 100 milliseconds. Alternatively, protect line cards can routinely carry low priority traffic that is interruptible, allowing the protect line card to handle higher priority traffic previously carried by a failed working line card. This approach renders unnecessary engineering a network for less than full capacity to allow rerouting in the event of individual line card failure. Consequently, all data paths can be fully utilized. If a particular interface module on one data bus needs removal for maintenance, a duplicate data bus is available intact, allowing hot replacement of any working or protect interface module, even while a line card protection switch is in effect.

High speed data bus

Abstract: The invention comprises data processing systems and components thereof Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices Memory integrated circuits and memory modules including at least one switch in the data bus are also provided

Memory device having a programmable register

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Emulator chip/board architecture and interface

Abstract: A communication interface for an in-circuit emulation system. The interface uses four pins between a virtual microcontroller (an FPGA emulating a microcontroller) and a real microcontroller under test. The bus is fast enough to allow the two devices to operate in synchronization. I/O reads, interrupt vector information and watchdog information is provided over the bus in a time fast enough to allow execution in lock step. Two data lines are provided, one is bi-directional and one is driven only by the microcontroller. A system clock is provided and the microcontroller supplies its clock signal to the FPGA since the microcontroller can operate at varying clock speeds. The bus is time-dependent so more information can be placed on this reduced-pin count bus. Therefore, instructions and data are distinguished based on the time the information is sent within the sequence. The bus can be used to carry trace information, program the flash memory on the microcontroller, perform test control functions, etc.

System and method for providing an improved common control bus for use in on-line insertion of line replaceable units in wireless and wireline access systems

Abstract: There is disclosed a system and method for providing an improved common control bus for use in the on-line insertion of line replaceable units (such as circuit board cards) into a backplane of a processor shelf, a modem shelf, or a similar type of equipment. The present invention increases the number of device locations that a common control bus can access. The present invention comprises a complex programmable logic device on a circuit board card that is coupled to a common control bus. The complex programmable logic device is capable of selectively coupling to the common control bus each one of a plurality of device locations on the circuit board card. The complex programmable logic device controls data access to and from each device that is coupled to the common control bus.

Power line communications network device for DC powered computer

Abstract: A multi-point computer networking system for transmitting data over power lines is built into an external AC adapter that powers a computer device or peripheral. The networking system includes a data bus interface unit for exchanging data with a computer, a power line data transceiver unit for placing data onto and taking data off of the power line, and a network controller implementing a network protocol for sending and receiving messages. The networking system is disposed within the housing of the AC adapter. Therefore, there is no extra box or cable needed for each DC powered computer device to serve both DC power and data networking functions.

Method and apparatus for emulating ethernet functionality over a serial bus

Abstract: The invention allows applications to transparently use a bus, such as the IEEE-1394 serial bus, as if it were an Ethernet (IEEE 802.3). In a conventional Ethernet, each node is assigned a unique 6-byte MAC address in order to receive frames addressed to it over the LAN. According to the invention, IEEE-1394 bus node identifiers are mapped to Ethernet MAC addresses using for example a digital signature algorithm. Ethernet frames are then “wrapped” into 1394 bus packets and addressed to the destination node using the hashed address. The receiver unwraps the 1394 packet and restores the Ethernet frame to its original form. An optimum packet size for transmission of Ethernet packets over the 1394 bus is selected with reference to speed topology maps in the 1394 bus nodes, and this optimum size is transmitted to bus nodes. This packet size is reported to TCP to specify the packet size, and all packets larger than that size are fragmented and reassembled at the receiving node. The protocol works transparently across networks that are linked via bridges.

Safety critical avionics for the 777 primary flight controls system

Abstract: The new technologies in flight control avionics systems selected for the Boeing 777 airplane program consists of the following: Fly-By-Wire (FBW), ARINC 629 Bus, Deferred Maintenance. The FBW must meet extremely high levels of functional integrity and availability. The heart of the FBW concept is the use of triple redundancy for all hardware resources: computing system, airplane electrical power, hydraulic power and communication path. The architecture of the 777 flight controls system follows the earliest Boeing 7J7 design. The Boeing designed global DATAC bus, also known as ARINC 629 data bus, is used to communicate among all computing systems. Each DATAC bus is isolated, both physically and electrically from the other two. The three DATAC buses are not synchronized. The control system performance under the autonomous and asynchronous DATAC bus operation has been studied. The primary flight computers (PFCs) form a triple-triple redundant system; three PFC channels and three computing lanes in each channel. Each channel is also isolated, both physically and electrically from the other two. The microprocessor hardware for three computing lanes in each channel are dissimilar to facilitate detection of generic design errors of the most complicated hardware devices; microprocessors. The Byzantine general problem has been considered in the design of the PFC redundancy management to cope with functional asymmetry and communication asymmetry. The deferred maintenance is to provide hot spare modules within an LRU such that the airplane dispatchability can be enhanced. This concept is applied to the three major avionics systems, PFC, Air Data Inertial Reference System (ADIRU) and Airplane Information Management System (AIMS).

Dynamic hardware and software performance optimizations for super-coherent SMP systems

Abstract: A method for increasing performance optimization in a multiprocessor data processing system. A number of predetermined thresholds are provided within a system controller logic and utilized to trigger specific bandwidth utilization responses. Both an address bus and data bus bandwidth utilization are monitored. Responsive to a fall of a percentage of data bus bandwidth utilization below a first predetermined threshold value, the system controller provides a particular response to a request for a cache line at a snooping processor having the cache line, where the response indicates to a requesting processor that the cache line will be provided. Conversely, if the percentage of data bus bandwidth utilization rises above a second predetermined threshold value, the system controller provides a next response to the request that indicates to any requesting processors that the requesting processor should utilize super-coherent data which is currently within its local cache. Similar operation on the address bus permits the system controller to triggering the issuing of Z 1 Read requests for modified data in a shared cache line by processors which still have super-coherent data. The method also comprises enabling a load instruction with a plurality of bits that (1) indicates whether a resulting load request may receive super-coherent data and (2) overrides a coherency state indicating utilization of super-coherent data when said plurality of bits indicates that said load request may not utilize said super-coherent data. Specialized store instructions with appended bits and related functionality are also provided.

Self-test RAM using external synchronous clock

Abstract: A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data, a control circuit receiving a signal from an external system clock and controlling data transfer operations between the memory device and an external data bus, and a test mode circuit receiving the external clock signal. When operated in speed test mode, the control circuit provides a signal to the test mode circuit enabling its function. A predetermined data pattern is first written to one or more cells, and then subsequently accessed during a read cycle. The enabled test mode circuit compares the contents of an internal data bus to the predetermined data pattern at a time referenced to the system clock signal. In the case of a failed comparison, the test mode circuit produces a signal that places the external data bus in a high impedance state. The disclosed memory device is therefore capable of itself providing some of the test functions previously provided by external testing equipment, and speed testing equipment in particular.

Self powered data communication optical fiber cable extender

Abstract: An extender for an electrical data bus including a power line and signal lines has first and second electrical connectors for connection to respective electrical connectors attached to respective electrical data buses. The electrical connectors include a data interface circuit for communication with the electrical bus, an optical transmitter and optical receiver electrically connected to the data interface circuit, and driver circuits for the optical transmitter and optical receivers. The driver circuits obtain power from the power line on the local electrical data bus. An optic fiber is connected between the optical transmitters and receivers at respective first and second electrical connectors to transfer data optically between the first and second electrical connectors and thereby extend the range of the data bus.

Generic serial bus architecture

Abstract: A serial bus is provided that supports multiple data transmission protocols. The serial bus allows a bus master to communicate with a variety of semiconductor devices that support a variety of serial interface standards. As a result, a single bus master may control and observe a JTAG-compatible semiconductor device, an SPI-compatible semiconductor device and an I 2 C compatible semiconductor device over the serial bus.

Hard disk drives employing high speed distribution bus

Abstract: A processor coupled by a high speed, wideband data bus to a plurality of slave data processing circuits. The data bus includes an N-bit set of master registers loaded by the processor and M number of slave modules, each slave module having an N-bit slave data register. The processor can sequentially load the master data registers and transfer the data to a selected slave module in a round-robin manner. A high speed transfer of data is thereby achieved.