Proceedings ArticleDOI
Reducing bus delay in submicron technology using coding
Paul P. Sotiriadis,Anantha P. Chandrakasan +1 more
- pp 109-114
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TLDR
The Elmore delay is extended to account for a distributed model with distributed coupling component and an arbitrary number of lines driven by independent sources and a technique to speed up the communication through a data bus using coding is proposed.Abstract:
In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed wire model or a lumped capacitive coupling between wires. In this paper we extend the Elmore delay to account for a distributed model with distributed coupling component and an arbitrary number of lines driven by independent sources. The effect of data patterns is taken into account allowing us to estimate the delay on a sample by sample basis instead of making a worst case assumption. Using this detailed wire delay model, we propose a technique to speed up the communication through a data bus using coding. The idea is to encode the data being transmitted through the bus with the goal of eliminating certain types of transitions that require a large delay. We show that by using proper encoding techniques, the bus can be sped up by a factor of 2.read more
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On-Chip Communication Architectures: System on Chip Interconnect
Sudeep Pasricha,Nikil Dutt +1 more
TL;DR: This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design, and will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on- chip communication architectures.
Journal ArticleDOI
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes
S.R. Sridhara,Naresh R. Shanbhag +1 more
TL;DR: Fundamental bounds on the number of wires required to provide joint crosstalk avoidance and error correction using memoryless codes are presented and a code construction that results in practical codec circuits with theNumber of wires being within 35% of the fundamental bounds is proposed.
Proceedings ArticleDOI
Area and energy-efficient crosstalk avoidance codes for on-chip buses
TL;DR: This paper presents an overview of the existing coding schemes and proposes a family of codes referred to as overlapping codes that reduce both overheads and energy dissipation and constructs two codes from this family that demonstrate their superiority over existing schemes in terms of area and energy Dissipation.
Journal ArticleDOI
Exploiting ECC redundancy to minimize crosstalk impact
TL;DR: It is shown that dual Rail codes perform better at reducing crosstalk-induced-bus delays than Hamming codes, and the possibility of exploiting the information redundancy previously necessary to limit CIBD is investigated.
Proceedings ArticleDOI
A crosstalk aware interconnect with variable cycle transmission
TL;DR: A crosstalk aware interconnect that uses a faster clock and dynamically controls the number of cycles required for transmission based on the estimated delay of the data pattern to be transmitted and is evaluated on the on-chip buses of a microprocessor and the SPEC2000 benchmarks.
References
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Garrett Birkhoff,Gian-Carlo Rota +1 more
TL;DR: In this paper, the authors propose an order of differential equations with constant coefficients for plane-autonomous systems and approximate solutions for linear Equations with Constant Coefficients with regular singular points.
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Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs
TL;DR: In this paper, a closed-form formula for a waveform of the RC interconnection line with practical boundary conditions is derived, and the optimum linewidth that minimizes RC delay and the trend of RC delay in the scaled-down VLSIs are discussed.
Journal ArticleDOI
An analytical delay model for RLC interconnects
Andrew B. Kahng,Swamy Muddu +1 more
TL;DR: An analytical delay model based on first and second moments to incorporate inductance effects into the delay estimate for interconnection lines under step input is developed and shown to be as easy to compute as Elmore delay.