Showing papers on "System on a chip published in 1992"

Performance of synchronous and asynchronous schemes for VLSI systems

Abstract: Continuous advances in VLSI technology have made it possible to implement a system on a chip. One consequence of this is that the system will use a homogeneous technology for interconnections, gates, and synchronizers. Another consequence is that the system size and operation speed increase, which leads to increased problems with timing and synchronization. System and delay models necessary for the study of time performances of synchronous and asynchronous systems are developed. Clock skew is recognized as a key factor for the performance of synchronous systems. A mode of clocking that reduces the clock skew substantially is proposed and examined. Time penalty introduced by synchronizers is recognized as a key factor for the performance of asynchronous systems. This parameter is expressed in terms of system parameters. Different techniques and recommendations concerning performance improvement of synchronous and asynchronous systems are discussed. >

A 2-chip 1.5 Gb/s bus-oriented serial link interface

Abstract: The authors report a monolithic transmitter and receiver chip pair which implements a full-duplex virtual ribbon cable interface. For short-distance applications, on-chip equalizer is provided to allow use of coaxial cables rather than a more costly fiber link. The chips require no external frequency-determining elements or user adjustments and operate over a range of 600 to 1500 MHz using an on-chip VCO (voltage-controlled oscillator). Only one in-package capacitor per chip is required. A state-machine controller (SMC) is also implemented on the RX chip to transparently handle a start-up handshake protocol. This is the highest-speed-link-interface chipset reported to date at this level of functionality and integration. >

The Alpha Demonstration Unit: A High-performance Multiprocessor for Software and Chip Development.

Abstract: Digital’s first RISC system built using the 64-bit Alpha AXP architecture is the prototype known as the Alpha demonstration unit or ADU. It consists of a backplane containing 14 slots, each of which can hold a CPU module, a 64MB storage module, or a module containing two 50MB/s I/O channels. A new cache coherence protocol provides each processor and I/O channel with a consistent view of shared memory. Thirty-five ADU systems were built within Digital to accelerate software development and early chip testing. There is nothing more difficult to take in hand, more perilous to conduct, or more uncertain in its success, than to take the lead in the introduction of a new order of things. – Niccolo Machiavelli, The Prince Introducing a new, 64-bit computer architecture posed a number of challenges for Digital. In addition to developing the architecture and the first integrated implementations, an enormous amount of software had to be moved from the VAX and MIPS (MIPS Computer Systems, Inc.) architectures to the Alpha AXP architecture. Some software was originally written in higher-level languages and could be recompiled with a few changes. Some could be converted using binary translation tools.[1] All software, however, was subject to testing and debugging. It became clear in the early stages of the program that building an Alpha demonstration unit (ADU) would be of great benefit to software developers. Having a functioning hardware system would motivate software developers and reduce the overall time to market considerably. Software development, even in the most disciplined organizations, proceeds much more rapidly when real hardware is available for programmers. In addition, hardware engineers could exercise early implementations of the processor on the ADU, since a part as complex as the DECchip 21064 CPU is difficult to test using conventional integrated circuit testers. For these reasons, a project was started in early 1989 to build a number of prototype systems as rapidly as possible. These systems did not require the high levels of reliability and availability typical of Digital products, nor did they need to have low cost, since only a few would be built. They did need to be ready at the same time as the first chips, and they had to be sufficiently robust that their presence would accelerate the overall program. Digital’s Systems Research Center (SRC) in Palo Alto, CA had had experience in building similar prototype systems. SRC had designed and built much of its computing equipment.[2] Being located in Silicon Valley, SRC could employ the services of a number of local medium-volume fabrication and assembly companies without impeding the mainstream Digital engineering and manufacturing groups, which were developing AXP product systems. The project team was deliberately kept small. Two designers were located at SRC, one was with the Semiconductor Engineering Group’s Advanced Development Group in Hudson, MA, and one was a member of Digital’s Cambridge Research Laboratory in Cambridge, MA. Although the project team was separated both geographically and organizationally, communication flowed smoothly because the individuals had collaborated on similar projects in the past. The team used a common set of design tools, and Digital’s global network made it possible to exchange design information between sites easily. As the project moved from the design phase to production of the systems, the group grew, but at no point did the entire team exceed ten people. Since multiprocessing capability is central to the Alpha AXP architecture, we decided that the ADU had to be a multiprocessor. We chose to implement a bus-based memory coherence protocol. A high-speed bus connects three types of modules: The CPU module contains one microprocessor chip, its external cache, and an interface to the bus. A storage module contains two 32-megabyte (MB) interleaved banks of dynamic random-access memory (DRAM). The I/O Digital Technical Journal Vol. 4 No. 4 Special Issue 1992 1 The Alpha Demonstration Unit: A High-performance Multiprocessor for Software and Chip Development module contains two 50MB per second (MB/s) I/O channels that are connected to one or two DECstation 5000 workstations, which provide disk and network I/O as well as a high-performance debugging environment. Most of the logic, with the exception of the CPU chip, is emitter-coupled logic (ECL), which we selected for its high speed and predictable electrical characteristics. Modules plug into a 14-slot card cage. The card cage and power supplies are housed in a 0.5-meter (m) by 1.1-m cabinet. A fully loaded cabinet dissipates approximately 4,000 watts and is cooled by forced air. Figures 1 and 2 are photographs of the system and the modules.

Pocket electronic data retrieval device allowing access to compressed data on a memory chip with unique interchangeable chip carrier

Abstract: A compact electronic data retrieval device allowing access to compressed data stored on interchangeable ROM chips The chips which can contain directories, manuals or other materials that may be available for convenient access The chips which are not easily copied may be economically distributing Interchangeability of the chips is enhanced by a novel chip replacement system The chip replacement system enabling a precise and easy way for the user of an electronic device to change a computer chip which is utilized in the electronic device The chip is mounted onto a removable door in a manner to ensure proper placement of the chip and that proper forces are utilized to fit it within a chip socket This system is particularly applicable to electronic appliances where a computer chip is used to carry large amounts of data and replaced from time to time

A single chip solution for closed caption decoding

Abstract: A single CMOS chip for closed caption decoding is described. The performance of this chip in the area of data acquisition was high because of intensive use of digital signal processing techniques. This also reduces the amount of external components. The chip can be operated in a stand-alone mode or under control of a microcomputer found in TV sets. The chip has enough space in the form of ROM capacity and built-in microcontroller for future extensions to the standard. >

Real-time monitoring for software development and testing

Abstract: Proposes a design technique for tracing and monitoring instruction execution where general-purpose registers are used as the main source for manipulating data and results within a RISC (reduced-instruction-set computer)-based microprocessor design. The R3000 MIPS processor will be used as an example of a RISC-based microprocessor target to be monitored in an embedded computer system. The design will be independent of the way the cache memory is implemented on the unit being monitored, i.e., it will monitor on-chip or off-chip cached systems. >

A VLSI chip set for a massively parallel scientific processor

Abstract: The author describes a chip set developed to provide basic building blocks for the APE100 massively parallel SIMD (Single Instruction Multiple Data) processor, designed with ASIC techniques and fabricated in a 1.2 mu m CMOS technology. This chip set contains three devices, which provide three main functions for a SIMD machine, namely the processing element, the controller for the array of processing nodes and the handling of communication among nodes. These functions are respectively provided by the MAD chip (the processing node), the zCpu chip (the controller) and the Commuter chip (communication handler). >

Development of functional simulation model of CMOS memory

Abstract: The development of semiconductor integration has brought with it the system-on-chip era. The small-quantity productions of diversified kinds of IC are required at the stage of ASIC (application specific IC). Thus, it has become important to reduce the design period for the mixed analog/digital circuit. The capacity of the CMOS memory continues increasing and is expected to expand from the Mbit level to the Gbit level. Then the parasitic effect will be a problem. This paper proposes a functional simulator based on the continuous system simulation technique. It is shown that the proposed simulation including the parasitic effect can effectively be applied to the functional design of CMOS memory, which has been unsatisfactory in the early circuit simulator. In the proposed method, CMOS memory is modeled based on the functional element model of the CMOS memory and the functional simulation can easily be realized considering the parasitic functional effect. This helps to improve the design quality and to reduce the design period.

Design of a systolic VLSI chip for computing scale space

Abstract: throughput. The hardware organization of a processor cell is simple enough that the entire systolic arraycan be realized as a single chip system. A prototype CMOS VLSI chip implementing a single processorcell was designed, fabricated and tested. Based on the estimates obtained from the prototype chip, a reallife chip is expected to operate at a rate of 40 MHz. The chip can process a 5

Four layer metal, flip chip, submicron ASIC product designed for advanced multichip module

Abstract: The use of an additional metal layer on a large CMOS ASIC part provides a practical method for converting an existing chip design with wirebond or tape automated bonding (TAB) peripheral pads to an array of flip chip solder bumps across the chip surface. While there are advantages to single chip packages with flip chip interconnect, multichip modules are required to take full advantage of flip chip packing density and performance gains. Compared with single chip packages on a printed circuit board, flip chip multichip modules offer about a 10* surface area reduction. Propagation delays in signal interconnect lines are about three times faster for the module than single chip packages on a printed circuit board. >

An analog VLSI edge detection chip and digital multiprocessor chip for neural-based vision processing

Abstract: A mixed-signal VLSI design for early vision processing, which includes an analog edge detection chip with embedded array photosensors and a digital multiprocessor chip, is described. The system architecture overview shows that the combination of the analog chip and the digital processors can perform highly efficient processing in neural-based vision processing. The analog edge detection chip consisting of 258*258 photosensor cells can be implemented in an area of 13.5 mm*15.5 mm using the MOSIS 0.8- mu m CMOS technology. The digital multiprocessor chip, which includes 64 processing elements, can be implemented in a 15.0-mm*18.0-mm chip using an industrial-scale 0.5- mu m CMOS technology. A system implementation for fingerprint verification is presented as an example of possible applications. >