Showing papers on "Voltage-controlled oscillator published in 1994"

Modulation and frequency conversion by time sharing

Abstract: A time-share mixer circuit and a frequency converter, an I-Q modulator, and an I-Q demodulator. A switching signal drives the time-share mixer circuit to alternate between two output signals. The first output signal represents the output of a mixer having a given signal input and a local oscillator signal with a first phase as its local oscillator input. The second output signal represents the output of the mixer having the same input signal and the local oscillator signal with a second phase that differs from the first phase by 90 degrees as its local oscillator input signal. The frequency converter uses the time-share mixer in combination with a switched output phase shifter that switches in sync with the phase of the local oscillator signal to generate a phase shifted output signal in which the time average of an undesired image signal is substantially reduced compared to time average of the desired signal. The phase shifted output signal is then amplified by a bandpass amplifier. A clocked inverter in series with one of the mixer ports provides improved performance by eliminating the need for two precisely phase-shifted local oscillator signals.

Phase locked loop using a counter and a microcontroller to produce VCXO control signals

Abstract: A digitally controlled phase locked loop generates a derived clock signal that is frequency locked to a reference clock signal. The apparatus is comprised of a microcontroller, counter, digital to analog converter (DAC) and a voltage controlled crystal oscillator (VCXO) connected in a feedback loop arrangement. A frequency output derived from the VCXO periodically samples an incoming reference signal. The sampled count value is compared to an ideal count value associated with the same sampling time period. A microcontroller and software-based algorithm perform the phase comparison and loop filter operations of the phase locked loop (PLL).

On-chip voltage controlled oscillator

Abstract: An on-chip voltage controlled oscillator for use in an analog phase locked loop receives power from a voltage regulator which greatly reduces the noise seen by the voltage controlled oscillator. The voltage controlled oscillator has a DC bias section which supplies a relatively constant current to the multivibrator to assure a minimum operating frequency. A control signal is used to provide additional current which increases the speed of oscillation. The bias current reduces the transfer characteristics (MHz/volt) of the voltage controlled oscillator making it more immune to noise in the control signal.

Phase lock loop with selectable frequency switching time

Abstract: A phase lock loop (PLL) circuit for controlling an oscillator includes a phase comparator, a loop filter, a reference converter and a feedback converter whose performance characteristics are dynamically controlled so as to provide a phase-locked output signal with both high frequency stepping resolution and low phase locking time The phase comparator compares the relative phases of the reference and feedback signals, and outputs a phase difference signal representing such phase comparison The loop filter, in accordance with a filter bandwidth dynamically selected by a filter control signal, filters the phase difference signal to provide a frequency control signal for a voltage controlled oscillator (VCO) The reference converter is a programmable frequency divider which, in accordance with a reference proportionality factor dynamically selected by a reference control signal, reduces the frequency of the PLL reference signal frequency used by the phase comparator The feedback converter is another programmable frequency divider which, in accordance with a feedback proportionality factor dynamically determined by a feedback control signal, reduces the frequency of the VCO feedback signal frequency used by the phase comparator Each combination of a selected filter bandwidth, a reference proportionality factor and a feedback proportionality factor corresponds to a different time interval within which phase lock is achieved

Logic gate with controllable hysteresis and high frequency voltage controlled oscillator

Abstract: A hysteresis circuit comprises a first logic section, a second logic section cascaded with the first logic section, and circuitry for controlling hysteresis threshold voltages of the hysteresis circuit. The hysteresis controlling circuitry conducts current from a source of a first supply voltage to the output lead of the first logic section during a low-to-high transition of an input voltage on an input terminal of the hysteresis circuit. The hysteresis controlling circuitry conducts current from the output lead of the first logic section to a source of a second supply voltage during a high-to-low transition of the input voltage on the input terminal of the hysteresis circuit. A clock generator integrated circuit chip employing the hysteresis circuit in a voltage controlled oscillator can generate squarewave signals of 150 MHz onto a plurality of output terminals when powered from approximately 3.3 volts throughout a 0 to 70 degree Celsius temperature range, a clock skew of less than 0.5 nanosecond existing between the squarewave signals on the output terminals.

Novel current-conveyor-based single-resistance-controlled/voltage-controlled oscillator employing grounded resistors and capacitors

Abstract: A novel single-resistance-controlled/voltage-controlled oscillator using three current conveyors, two grounded capacitors and three grounded resistors is presented. The proposed circuit offers the following advantageous features: employment of three grounded resistors for ease of adjustment, independent oscillation control through a single grounded resistor, independent frequency control through a single grounded resistor, employment of two grounded capacitors ideal for integration, ease of convertibility into a voltage-controlled oscillator, and very good frequency stability.

Voltage controlled oscillator with efficient process compensation

Abstract: A voltage controlled oscillator (VCO) provides an output signal with an output frequency that varies only minimally for any given input control voltage despite variations in the manufacturing process, temperature and supply voltage. The VCO also includes a multistage ring oscillator which includes a plurality of series-connected current-starved inverter stages. The VCO utilizes a first current source to provide a substantially constant current independent of process, temperature and supply voltage and a second current source to provide a variable current that varies in response to process, temperature and supply voltage. Both current sources generate a respective current signal independent of the input signal to the VCO. An attenuator, responsive to the VCO's input voltage signal (typically from a phase-locked loop filter) provides a control current signal to the ring oscillator. The attenuator receives a supply current created by subtracting the second current from the first current, and utilizes a differentiation subcircuit that attenuates the supply current in response to changes in an input voltage to produce a current control signal that sets the current level in the ring oscillator's cells. The frequency of oscillation of the ring oscillator is determined by the control current signal. Additionally, the VCO circuit may include a current mirror for receiving the control current signal from the attenuator and mirroring the control current signal to the ring oscillator.

TDMA mobile unit frequency synthesizer having power saving mode during transmit and receive slots

Abstract: In a frequency synthesizer of a TDMA cellular communication mobile unit, a reference pulse is supplied from a reference pulse source to a phase comparator whose output is coupled through an open/close loop mode switch to a loop filter which is connected to a VCO. A frequency divider produces a submultiple of the VCO frequency and supplies its output to the phase comparator. For power savings purposes, a controller first activates the reference pulse source and the frequency divider and operates the switch to establish a connection between the phase comparator and the loop filter. The controller then operates the frequency divider so that a channel is established between the mobile unit and a first cell site station, and then operates the switch to clear the connection and deactivates the reference pulse source and the frequency divider to allow signals to be exchanged between the mobile unit and the first cell site station during a transmit/receive slot of the channel in a power saving mode. The controller then activates the reference pulse source and the frequency divider, operates the switch to reestablish the connection, and operates the frequency divider during an idle slot of the channel to receive a signal from a second cell site station, and operates the frequency divider so that signals can be exchanged between the mobile unit and the first cell site station during a subsequent transmit/receive slot of the channel.

Wide frequency range CMOS relaxation oscillator with variable hysteresis

Abstract: A voltage controlled oscillator (VCO) which may be adjusted to provide oscillatory signals for a wide range of frequencies includes a relaxation oscillator in which a ramp signal is compared to a reference threshold which exhibits hysteresis. The frequency of the oscillator is changed by varying the hysteresis range of the threshold level and by changing the rate at which the ramp is generated. At higher frequencies, the signal processing delay through the comparator is a factor in determining the frequency of the signal produced by the oscillator. Current sources internal to the oscillator are controlled by a reference potential that is generated from an externally supplied band-gap reference potential. The VCO is used in a phase-locked loop which includes a charge pump circuit that accumulates charge on a capacitor responsive to limited-width pulses applied to a current source which is controlled by the reference potential generated in the VCO.

An 8 GHz silicon bipolar clock-recovery and data-regenerator IC

Abstract: This contribution shows that a monolithic integrated silicon bipolar circuit can provide phase and frequency locked loop (PFLL) based clock recovery and data regeneration up to 8Gb/s. Moreover, phase and frequency detector (PFD) operation up to 15Gb/s (with an external VCO) is demonstrated. Owing to the wide tuning range of the quadrature VCO, the circuit lends itself to operation over a wide range of bit rates. Other applications of the quadrature VCO, e.g. as a synthesizer, are possible. As shown by circuit simulations, the operating frequency can be extended beyond 1OGHz, if a small unbalance between both ring oscillator stages is eliminated by minor design changes. >

A 6 GHz 68 mW BiCMOS phase-locked loop

Abstract: The design of a 6 GHz fully monolithic phase-locked loop fabricated in a 1 /spl mu/m, 20 GHz BiCMOS technology is described. The circuit incorporates a voltage-controlled oscillator that senses and combines the transitions in a ring oscillator to achieve a period equal to two ECL gate delays. A mixer topology is also used that exhibits full symmetry with respect to its inputs and operates with supply voltages as low as 1.5 V. Dissipating 60 mW from a 2 V supply, the circuit has a tracking range of 300 MHz, an rms jitter of 3.1 ps, and phase noise of -75 dBc/Hz at 1 kHz offset. >

Panoramic time delay and integration video camera system

Abstract: One or more time delay and integration camera assemblies (A) are mounted in a housing (100) which is rotated by a motor (40, 106) relative to a vertical axis. A tachometer or encoder (44) produces signals whose frequency or voltage varies in accordance with an angular velocity of the camera assemblies about the vertical axis. A clock generator (46) converts the angular velocity signals into clocking signals for controlling movement of vertical lines of data values (20) along an array (14) of light sensitive elements to a shift register (22). In one embodiment, the clock generator includes a divider (82) which converts the angular velocity signal into a voltage, a comparator (84) which compares the first voltage with a second voltage, and a voltage controlled oscillator (88) which oscillates to generate the clocking signal. A second divider (88) defines a feedback loop between the output of the voltage controlled oscillator and the comparator for generating the second voltage. Each line of data from the array update (64) a corresponding line of a panoramic memory (66). The selectable portion (72) of the data from the panoramic memory is retrieved (70) independently of the memory updating. Scan converters (74) convert retrieved portions of the panoramic memory data into appropriate format for display on video monitor (78). In this manner, the panoramic memory is updated as the array rotates and data is independently retrieved from the panoramic memory to form panable displays.

Method and apparatus for a phase-locked loop circuit with holdover mode

Abstract: A phase-locked loop circuit with holdover mode is formed utilizing a primary (3) and secondary (4) phase-locked loop circuits. Each loop circuit comprises a phase detector (20;60), loop filter (30;20), VCXO (40;80) and frequency divider (50;90). The secondary loop (4) is configured such that its output is very stable. The primary loop (3) is phase-locked on a received reference clock signal (Vref) and the second loop (4) is phase locked on the output (V0,N1) of the primary loop, the scaled output of the secondary loop being parallel to the reference clock signal. If the incoming reference signal is interrupted or lost the circuit is switched (by 8,10) to a holdover mode where the input (21) of the primary loop is switched to the stable scaled output of the secondary loop. In holdover mode, the output of the primary loop is phase-locked to the stable output of the secondary loop. When the reference clock signal is reestablished, the input of the primary loop is switched back (by 8,10) to the reference clock signal.

Low voltage VCO having two oscillator circuits of different frequencies

Abstract: BiCMOS technology is used in the design of a VCO (200) to improve low DC operation. The VCO (200) includes two coupled oscillator circuits (201,219) tuned to different fixed frequencies such that the oscillator resonant frequencies define the tuning range of the VCO (200). The oscillator circuits (201, 219) are coupled such that the frequency of oscillation of the VCO (200) is adjustable via variable resistors (206, 214) by manipulating the bias currents to the two oscillator circuits (201,219). A biasing circuit (208) along with variable resistors (206 and 214) provide the DC bias to the oscillator circuits (201 and 219). The biasing circuit (208) maintains the sum of the biasing currents to the oscillator circuits constant. The oscillator circuits (201, and 219) are interconnected utilizing an RF coupling circuit (211). The VCO (200) is capable of operating at voltages as low as 1.8 volts DC.

Phase noise analysis of the sapphire loaded superconducting niobium cavity oscillator

Abstract: Measured phase noise of two GaAs FET amplifiers and a varactor phase shifter at 9.7 GHz reveal that optimum bias conditions change when cooling from room to liquid helium temperatures. This understanding enables optimisation of the electronic noise in an all cryogenic tunable sapphire loaded superconducting cavity (SLOSC) X-band loop oscillator. The measured phase noise was limited by vibrations of the tuning mechanism. In a fixed frequency SLOSC oscillator the phase noise was limited by the amplifier noise, and has been measured to be /spl minus/140 dBc/Hz at 1 kHz from the unfiltered port of the loop oscillator. Comparison of component and oscillator phase noise allows us to calculate the phase noise at the filtered port to be /spl minus/175 dBc/Hz at 1 kHz offset. >

Response of a Bloch oscillator to a THz-field

Abstract: In this paper we report on the observation of response of a Bloch oscillator at room temperature to a THz-field of a frequency larger than the Bloch frequency. The oscillator consisted of a semiconductor superlattice structure, with an applied dc voltage giving rise to a dc electron drift current. Submitting the oscillator to a field at a frequency of 3.3 THz caused a sizeable reduction of the current; the THz-field was generated by use of intense THz-radiation pulses focused on an antenna coupled to the superlattice. We attribute the THz-field induced reduction of the current to a frequency modulation of the Bloch oscillations of electrons at the frequency of the THz-field, leading to reduction of the electron drift velocity and, consequently, of the current.

Modular radar architecture film (FM/CW or pulse) for automobile collision avoidance applications

Abstract: A modular radar system using both FM/CW and pulse waveforms for automotive collision avoidance applications. The radar system comprises a transmit and a receive antenna for transmitting and receiving, respectively, either one of FM/CW waveform and pulse waveform, a voltage-controlled oscillator (VCO) for generating a pre-set waveform for the transmit antenna, a modulator for modulating the pre-set waveform of the VCO, a switch for allowing the pre-set waveform from the VCO to be transmitted for a predetermined interval so as to generate the pulse waveform, a timing generator for causing the modulator to execute through a pre-set sequence of frequencies for either one of the pulse and FM/CW modes of waveforms with the timing generator controlling the transmission of one of the FM/CW waveform and pulse waveform, a balanced mixer for signal conversion In both FM/CW and pulse modes, an IF/Baseband receiver for amplifying the received FM/CW waveform and for IF-amplifying the received pulse waveform to generate an in-phase and a quadrature baseband output, a coherent oscillator for generating a coherent oscillating signal of a predetermined frequency to the receiver for centering the IF-amplified received pulse waveform at the predetermined frequency during pulse mode, and a frequency control loop for causing the VCO to maintain an offset by a predetermined frequency in the pulse mode between receive and transmit.

Apparatus for extracting an optical clock and apparatus for demultiplexing a time-division multiplexed signal

Abstract: A signal light and a clock light which is generated by a clock light generator are propagated through a non-linear optical medium of, for instance, a silica based single mode optical fiber, from which the signal and clock lights and a four-wave mixing light are obtained. One light, for instance, the four-wave mixing light is extracted from the output lights of the non-linear optical medium, and a control signal which is dependent on a time-mean value in power of the extracted light is applied to a voltage controlled oscillator (VCO) for driving the clock light generator. Thus, a clock light which is locked in phase to the signal light is obtained. In case where the signal light comprises N time-division sequential lights (N=1, 2, 3, - - -), and a clock frequency of the clock light is 1/N of a clock frequency of the signal light, each one of the N time-division seaquential lights is shifted in phase or frequency by the non-linear optical medium, so that the phase or frequency shifted sequential light is switched to be demultiplexed by a switch device such as an optical coupler and a polarization beam splitter.

Communication system having transmitter frequency control

Abstract: A communication system is simpler and conserves power by eliminating the need for a reference frequency oscillator in the transmitter circuit. In a battery operated transceiver of the present invention, the receiver portion includes a tracking oscillator. The tracking oscillator output is used to synchronize received data and as a reference frequency source for the transmitter. In a half duplex communication system a reply signal is transmitted while no command signal is being received. Therefore, the transceiver in such a system includes circuitry for maintaining the reference frequency during transmission. Thus, the frequency accuracy of the transmission is based on the frequency accuracy of the received command signal. The tracking oscillator in one embodiment includes a phase locked loop circuit having a voltage controlled oscillator (VCO), an up-down counter, and a digital to analog converter (DAC) for determining the VCO frequency. A transparent latch in series between the counter and the DAC is used to maintain the VCO frequency as a reference frequency for transmission.

Fast acquisition clock recovery system

Abstract: A transceiver integrated circuit including a transmitter section having a phase-locked loop with an oscillator to provide an output at a predetermined transmission frequency, and a receiver section having a phase-locked loop with an oscillator used to provide a recovered clock from an incoming data signal. In a second mode when no incoming data is being received, the receiver oscillator is controlled in accordance with the transmitter oscillator to operate the receiver oscillator at the expected frequency of future data. Therefore, when data is received, the receiver oscillator is at the same approximate frequency as the incoming data thereby enabling fast acquisition by merely adjusting the phase of the receiver oscillator to the incoming data. In particular, the receiver and transmitter oscillators are identical current controlled oscillators that are operated in the second mode at the same approximate frequency by feeding the receiver oscillator with a current that is substantially equal to the loop current controlling the transmitter oscillator. Further, to provide higher slaving accuracy, a frequency detector is used to compare the outputs of the receiver and transmitter oscillators in the second mode, and to control the receiver oscillator into frequency synchronism with the transmitter oscillator.

Frequency synthesizer for use in radio transmitter and receiver

Abstract: A phase comparator (91) makes a phase comparison between a frequency-divided signal from a frequency divider (98) and a reference oscillation signal from a reference signal oscillator (90). The phase error signal obtained from the comparison is passed through an LPF (92) to yield a frequency control signal, which is applied to a VCO (94). An oscillated signal from is frequency-multiplied by a frequency multiplier (96). The multiplied output oscillation signal SO is frequency-divided by the frequency divider (98) and output to the phase comparator (91). The multiplied output oscillation signal SO is sent out to a receiver circuit (43) and a transmitter circuit (45).

A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique

Abstract: The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 2/sup 23/-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor. >

Autoranging digital analog phase locked loop

Abstract: An autoranging digital/analog (D/A) phase locked loop (PLL) 10 includes a frequency discriminator circuit 12 connected to a shift register 14. Shift register 14 is connected to a voltage controlled oscillator circuit (VCO) 16. VCO 16 is connected to generic counter 17. Counter 17 is optional in this preferred embodiment. Counter 17 is connected to a phase detector 13 and frequency discriminator 12. Phase detector 13 is connected to a charge pump control circuit 15. Charge pump control circuit 15 is also connected to VCO 16. A second generic counter 11 is connected to frequency discriminator 12. Second counter 11 is also optional in this preferred embodiment. First generic counter 17 and second generic counter 11 can be implemented to reduce the phase detector frequency relative to VCO 16 or a reference clock signal frequency. Ratios of M to N allow frequency multiplication or division of VCO 16 relative to the reference clock signal frequency. A method for achieving phase lock between a first signal and a second signal, in accordance with the present invention, comprises the steps of comparing the phases of the first signal and the second signal, adjusting the frequency of the second signal in a digital fashion until the phases of the first signal and second signal are within a predetermined phase relationship; and adjusting the frequency of the second signal in an analog fashion until a phase lock is obtained between the first signal and the second signal.

VCO bias circuit with low supply and temperature sensitivity

Abstract: A novel bias generator circuit for a voltage controlled oscillator is described. The bias generator allows the VCO frequency to be made essentially independent of the supply voltage and temperature.

Ultra low-power integrated circuit for pseudo-baseband down-conversion of GPS RF signals

Abstract: A GPS receiver downconverter combines on a single integrated circuit, a first super-heterodyne mixer, a voltage controlled oscillator, a phase locked loop, a pair of quadrature mixers and a pair of quantizers with in-phase and quadrature-phase sampler outputs operable at twenty-five MHz and 2.5 MHz. Emitter-coupled logic and special low-voltage bipolar semiconductor technology are combined for 3.3 volt operation at under one hundred milliwatts.

Radio frequency telecommunications transceiver

Abstract: A radio frequency (RF) transceiver includes a direct modulation transmitter and single down-conversion receiver for operation in a time-division-duplex (TDD) telecommunications environment A single RF signal source, in the form of a phase-lock-loop (PLL), is used on a time-shared basis to provide both the carrier signal for the transmitter and the local oscillator (LO) signal for the receiver In the transmitter, direct modulation is effected by modulating a voltage-controlled oscillator (VCO) in the PLL with a burst of the transmit data while opening the loop and holding the loop feedback tuning voltage constant In the receiver, a self-adjusting comparator threshold is provided for automatically setting and adjusting a demodulated signal comparison threshold used in retrieving the data and data clock from the demodulated receive signal The interface between the transmitter and receiver and the host controller provides the control signals needed for the time-sharing of the single RF signal source, the proper programming of the PLL for the different transmitter carrier and receiver LO frequencies, the PLL loop control for the direct modulation of the VCO, and the enablement, or powering down, of the transmitter and receiver sections to minimize transceiver power consumption

A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM

Abstract: This paper describes a pair of delay-locked loops (one DLL for transmitting data, one for receiving) that satisfy the requirement for accurate timing (sub-100ps static phase error), even in the noisy environment (substrate and V/sub DD/) of DRAMs, to allow data transfer rates exceeding 500Mb/s/pin at 25V While the application of delay-locked loops to the problem of host-slave synchronization is not new, the loop described in this paper solves several problems of conventional PLLs and DLLs, providing unlimited phase shift (modulo 2/spl pi/) without a VCO, enabling lock in under 200ns and good jitter performance at low supply voltages >

Phase synchronization circuit having a short pull-in time and a low jitter

Abstract: In a phase synchronization circuit including a digital phase comparator 1, a synchronism discrimination circuit 2, a charge pump circuit 3, a loop filter 11, a voltage controlled oscillator 14, and a frequency-division circuit 6, the charge pump circuit 3 is composed of a level comparator 15 comparing the output voltage of the loop filter 11 with a predetermined reference voltage, for outputting a level discrimination signal, an AND circuit 4 for outputting a logical product of an output UP of the phase comparator 1 and the level discrimination signal, an inverter 5 for outputting an inverted signal of an output DOWN of the phase comparator 1, an AND circuit 6 for outputting a logical product of an output signal of the inverter 5 and the level discrimination signal, a PMOS transistor 8 having its source connected to a voltage supply through a constant current source 7, its gate applied with an output signal of the AND circuit 4, and its drain connected to an input of the loop filter 11, and an NMOS transistor 9 having its drain connected to the input of the loop filter 11, its gate applied with an output signal of the AND circuit 6, and its source connected to ground through a constant current source 10.

Write precompensation circuit for compensating nonlinear magnetic effects in a recording channel

Abstract: In accordance with the invention, a system which compensates nonlinear bit shift is provided for a high-rate constant density recording device. The invention's apparatus generates a programmable write precompensation delay that is an accurate percentage of the write current time period, allowing for variations of the write current time period with the track radius. The apparatus utilizes the output tinning signal from a Voltage Controlled Oscillator VCO to generate write precompensation delay that is an accurate percentage of the VCO output timing signal period, equal to the write current time period. Differential ramp voltage signal, also generated in the VCO, is compared to the late threshold voltage regulated by two internal resistors. Trailing edge of the delayed write signal, created at the comparator's output, is varied with the change in late threshold voltage. Frequency of the VCO's output timing signal is varied for different tracks. Since the frequency of the VCO is phase locked to the write current frequency, then the choice of the two internal resistors adjusts the precompensation delay period as a continuous percentage of the write current time period.

Reference frequency generating device

Abstract: PROBLEM TO BE SOLVED: To prevent frequency accuracy in an automatic running from being deteriorated when reception cannot be made, by accumulating phase difference data where an external reference signal is synchronously compared with an internal voltage controlled crystal oscillator(VCXO) in a normal reception state. SOLUTION: A reference frequency generating device for receiving a time signal with high accuracy from a satellite or the like is provided with, for example, an operation means 40 for calculating a steady frequency deviation, a part 45 for generating automatic run frequency correction data, and the like. Then, the part 45 for generating correction data stores frequency deviation D (n) data from the operation means 40 into a memory with time information in a normal reception state. On the other hand, when no signals can be received, the part 45 calculates the amount of transition regarding the aging of oscillation frequency focs of a VCXO 10 at each specific time based on the stored data. Automatic traveling correction data C (h) being calculated according to the operation are added to frequency control data C (n) being outputted by an operation means 23 for controlling steady frequency, and the fluctuation of the oscillation frequency focs of the VCXO 10 in an automatic traveling state is corrected. COPYRIGHT: (C)1999,JPO