Showing papers on "Wafer published in 1978"

Dynamic micromechanics on silicon: Techniques and devices

Abstract: New fabrication procedures ate described for constructing thin, electrostatically deflectable SiO 2 membranes on a silicon wafer in a very controllable manner. Performance parameters of these membranes are analyzed and three examples of typical applications for the micromechanical structures are discussed: a light modulator array, a micromechanical voltage-controlled switch, and the measurement of the mechanical properties of thin insulating films unconstrained by the substrate. Since the lifetimes of the membranes can be very long (>1010cycles), their dimensions very small (8.3 µm long, 950 A thick have been demonstrated), and the fabrication technique is simple and versatile, the potential applicability of such devices seems promising.

Fabrication of novel three-dimensional microstructures by the anisotropic etching of

Abstract: The anisotropic etching of single crystal silicon oil ((loo) and (110) orientation in a solution of pyrocatechol, ethylene di:nnine, and water is reviewed and the fabrication of three novel types of nicro- structures is described in detail. Controlled etching of Si, whicpi is re- quired to fabricate devices with a predictable geometry depends on : an accurately oriented, defect-free substrate, a well-defined and ali.ped pattern geometry, and rigorously clean etching conditions. Chnven- tional IC processing methods were used to fabricate: 1) a high-precision circular orifice in a thin pfSi membrane for use as an ink jet ncmle, 2) a multisocket miniature electrical connector with octahedral 'c wities suitable for cryogenic applications, and 3) multichannel anri;ys in (100) and (110) Si useful in various applications, eg., charge elecdttodes, physical masks, and optical devices. To make some of these strcwlures, a novel bonding technique to fuse silicon wafers with phosphalsilicate glass films was developed.

Micromechanical display logic and array

Abstract: A display device, addressing circuitry, and semiconductor control logic are all portions of an integrated structure formed by thin film technology on a single silicon wafer. The display comprises a thin film micromechanical electrostatic form of light reflective display formed by depositing thin films upon a silicon wafer and selectively etching to form metal-amorphous oxide micromechanical leaves deflected by applying potential thereto to provide electrostatic deflection. MOSFET devices are also formed upon the silicon wafer in juxtaposition with a plurality of micromechanical display elements. Addressing circuitry is connected to the MOSFET devices.

Ion-sensitive electrode and processes for making the same

Abstract: An improved ion-sensitive electrode is described, particularly in terms of the structure of a pH electrode and first and second processes for making the same. The pH electrode includes a substrate, preferably of forsterite, which is configured as a wafer having a substantially planar wafer surface. A continuous conducting layer, formed by either thin-film vapor deposition or thick-film screening processes, is formed on the substantially planar wafer surface in a desired configuration. A first region of the continuous conducting layer, and contiguous portions of the substantially planar wafer surface, are covered by a continuous membrane layer preferably composed of a pH-sensitive glass such as Corning Code 0150 glass. Typically, the membrane layer is formed by a thick-film process which involves the reduction of the glass to a fine powder, the mixing of the powder with an organic vehicle including an organic solvent and an organic binder to form a glass paste, and the application of the glass paste to the wafer through a wire mesh screen having an open region therethrough corresponding in configuration to that of the desired membrane layer. The paste when applied to the wafer is fused into a continuous membrane layer by the application of heat, at a first temperature to drive off the organic solvent and at a second temperature or temperatures to drive off the organic binder and to fuse the glass. An insulated output lead is connected directly to a second region of the conducting layer. Alternatively, an active device chip, such as that including a field effect transistor, is bonded to the wafer and interconnected with the second region of the conducting layer and with the output lead or leads. The exposed conducting elements of the electrode, including the second region of the conducting layer, the active device chip, and all exposed portions of the leads, are covered by a fluid-tight seal. Other ion-sensitive electrodes and variations of the aforementioned processes are described.

Method of cleaving semiconductor diode laser wafers

Abstract: Thick double heterostructure (Al,Ga)As wafers comprising layers of gallium arsenide and gallium aluminum arsenide on a metallized n-GaAs substrate are separated into individual devices for use as diode lasers. In contrast to prior art techniques employed with thinner wafers of mechanically cleaving the wafer in mutually orthogonal directions, the wafer is first separated into bars of diodes by a process which comprises (a) forming channels of substantially parallel sidewalls about 1 to 4 mils deep into the surface of the n-GaAs substrate (b) etching into the n-GaAs substrate with an anisotropic etchant to a depth sufficient to form V-grooves in the bottom of the channels and (c) mechanically cleaving into bars of diodes. The cleaving may be done by prior art techniques using a knife, razor blade or tweezer edge or by attaching the side of the wafer opposite to the V-grooves to a flexible adhesive tape and rolling the assembly in a manner such as over a tool of small radius. The diode bars may then, following passivation, be further cleaved into individual diodes by the prior art technique of mechanically scribing and cleaving. Processing in accordance with the invention results in good length definition and uniformity, high device yields and low density of striations on laser facets. The inventive process permits handling of thicker wafers on the order of 6 to 10 mils or so, which are cleaved only with great difficulty by prior art techniques. Such thicker wafers are less susceptible to breaking during handling and permit fabrication of shorter diode (cavity) length, which in turn is related to lower threshold current for device operation.

Process and material for manufacturing semiconductor devices

Abstract: A process step and material for use in the manufacture of semiconductor devices. To facilitate the etching of unmasked silicon dioxide, silicon nitride, silicon monoxide, bare silicon layers, or various refractory metals on preselected portions of a semiconductor slice, the material is exposed to a low pressure RF generated "cold" plasma (under 325° C.) produced from a homogeneous gaseous binary mixture of oxygen and a halocarbon. The halocarbon is preferably a gas having one carbon atom per molecule and is preferably fully fluorine-substituted.

Reaction kinetics of molybdenum thin films on silicon (111) surface

Abstract: Silicon‐metal systems are highly susceptible to solid‐solid reactions which modify their electrical and mechanical properties. Although many works are dealing with silicide formation, the molybdenum‐silicon system has not yet been investigated in detail to our knowledge. In this paper we present a He+ ion backscattering study of the molybdenum‐silicide formation by interaction of a thin molybdenum layer and a silicon 〈111〉 wafer. The silicide phases Mo3Si and MoSi2 have been identified by x‐ray diffraction and transmission electron microscopy. Surface transformations were observed by scanning electron microscopy. For an 800‐A Mo layer sputter deposited on silicon, we have found a time‐square growth rate for MoSi2 with an average activation energy of 2.4 eV in the temperature range 475–550 °C. The fundamental roles of the cleaning of the silicon surface, of the substrate temperature during sputtering, and of the stresses in the layer are pointed out.

Isolation of integrated circuits utilizing selective etching and diffusion

Abstract: Disclosed is a method of isolating portions of integrated circuits which permits closely packed structures. A semiconductor wafer is provided with a substrate of one conductivity type, a first layer of opposite conductivity type and high impurity concentration formed thereon, and a second layer of either conductivity type but lower concentration formed over the first layer. The major surfaces of the semiconductor layers are parallel to the (110) plane. Narrow grooves with sidewalls in the (111) plane are etched into the first layer. A shallow diffusion of impurities of the same conductivity type as the first layer is performed in the sidewalls and bottom of the grooves which permits the first layer to be contacted from the surface of the second layer. The groove is then etched further until it extends into the underlying substrate. Impurities of the same conductivity type as the substrate are diffused into the bottom and sidewalls of the grooves. The concentration of these impurities is chosen so that a chanstop region is formed in the substrate without appreciably affecting electrical conductivity between the first layer and the regions formed by the previous diffusion.

Multi-spectrum photodiode devices

Abstract: One or more photoelectric device elements are formed beneath the surface of a monolithic semiconductor structure below a surface photoelectric detector device to form a plurality of photoelectric devices having different spectral responses. The surface element is responsive to visible light and the one or more subsurface devices are sensitive to longer wavelength radiation depending upon the depth of the device below the surface of the structure. A two dimensional array of the devices may be formed in a single semiconductor wafer to provide a self-scanning multi-element photosensor array.

Apparatus and method for holding and planarizing thin workpieces

Abstract: An apparatus and method for holding a thin workpiece such as a semiconductor wafer for operations which require the workpiece to have a high degree of planarity such as photolithographic printing includes positioning the workpiece onto a planar holding face comprising the points of a multiplicity of regularly spaced-apart substantially parallel pins with a thin rim encompassing all pins to contain a vacuum in the region adjacent to the workpiece. The small abutting area of each pinpoint abutment reduces the probability of dirt particles collecting on the holding face and provides a high thrust pressure to dislodge dirt particles interposed between the abutment and the workpiece. A small amount of lateral motion is imparted to the workpiece when it first contacts the holding face to brush off any dirt particles on the abutments.

Method and apparatus for laser irradiating semiconductor material

Abstract: A laser system is disclosed for facilitating transient surface heating and/or melting and regrowth of amorphous, polycrystalline or imperfect crystalline semiconductor wafer material. This system also has specific application to gettering of impurities and the annealing-out of defects within a semiconductor wafer. In the system, a number of circular target-wafers are arranged around the periphery of a turntable. The turntable rotates while a simple, slow-moving beam-delivery system moves radially with respect to the turntable delivering a helical scan which may also be in the form of a multiple-track. Use of the turntable with a multiple wafer load allows efficient batch-processing. Blocking masks may be employed when it is desired to irradiate only selected areas of the semiconductor substrates.

Gettering of surface and bulk impurities in Czochralski silicon wafers

Abstract: The ability of SiO2 precipitates to act as a source of process‐induced defects which can either beneficially getter unwanted impurities, or deleteriously interact with surface devices, has led to some confusion in interpreting the role of wafer oxygen content in device processing. This report presents a composite model which explains the many variables involved in oxygen precipitation and gettering phenomena.

Method of connecting semiconductor structure to external circuits

Abstract: A silicon wafer, having a front surface with disjointed contact areas and a uniform rear surface, is provided at the contact areas of its front surface with respective pads each comprising a base layer of aluminum, a first intermediate layer of chromium or titanium, a second intermediate layer of nickel and an outer layer of gold or palladium. The rear surface is covered with a base layer of gold (or of a gold/arsenic alloy in the case of N-type silicon), a first intermediate layer of chromium, a second intermediate layer of nickel and an outer layer of gold or palladium to which a film of low-melting bonding agent (lead/tin solder) is applied. After testing and elimination of unsatisfactory wafer sections, the remaining sections are separated into dies placed on a conductive substrate; an extremity of a respective terminal lead, encased in a similar bonding agent, is then placed on the outer layer of each contact pad. All soldering operations are simultaneously performed in a furnace.

Semiconductor wafer polishing machine and wafer carrier therefor

Abstract: A carrier for semiconductor wafers to be polished is described, as well as mounting structure for securing the carrier within a polishing machine. The carrier is a relatively thick metal plate having on one of its faces, a sheet of material to which wafers can be adhered. An annular flange is on its opposite face to receive pressure loading from the polishing machine during the wafer polishing operation. Radially extending webs connect the annular flange with that area of the plate to distribute the pressure loading over substantially the full area of the plate opposed to the area on the opposite face on which wafers are to be adhered. An arrangement is included in the holder of the polishing machine for the carrier which applies a vacuum to the carrier to maintain the carrier selectively on the polishing machine, which arrangement releases the vacuum during the polishing operation and also enables simple intentional removal of the carrier. The carrier holder also enables the orientation of the carrier relative to the remainder of the polishing machine to be angularly tilted in such a manner that the leverage of any tangential force applied to wafers being polished is minimized.

Apparatus for the treatment of a wafer by plasma reaction

Abstract: An improved apparatus for the automatic handling of wafer materials is proposed for the plasma treatment of the wafers such as high-purity silicon semiconductor wafers. In this apparatus, the wafer carried by a carrier means to a position neighboring to a wafer table is picked up by a movable pick-up means and placed on the wafer table where it is subjected to the plasma treatment after the wafer table is fixed vacuum-tightly to a plasma reaction chamber. After completion of the treatment, the wafer is taken out by a second movable pick-up means and carried away by another carrier means to the succeeding processing step. Thus a possibility of full automatization of wafer processing is provided.

Cooled semiconductor power module including structured strain buffers without dry interfaces

Abstract: A semiconductor electronic device operates at high power levels using structured copper to reduce generation of stress between the elements of the device during thermal cycling in the course of normal operation Structured copper strain buffers are used to attach each side of a silicon wafer to fluid cooled heat sinks to provide efficient removal of heat generated by the device and good electrical connection to the silicon wafer

Process for producing uniform nozzle orifices in silicon wafers

Abstract: Nozzle plates for ink jet recording are produced by etching through silicon and like monocrystalline material wafers which frequently are non-uniform in thickness. The "100" plane surfaces of the wafers are coated with etchant masking material after which a nozzle array pattern is defined on the obverse surface and a similar, but larger and less exacting, aperture array of the same pattern is defined on the reverse surface. The silicon wafer as thus exposed is anisotropically etched from the reverse substantially through to the obverse and thereafter etched completely through the wafer from the obverse by the same anisotropic process. The lateral walls of the nozzles are substantially in the "111" plane of the wafers. The masking material is then stripped from the wafer.

Low-noise GaAs FET's prepared by ion implantation

Abstract: The rapidly improving performance of low-noise GaAs FET's can to a large extent be attributed to advances in the material preparation technology. Ion implantation directly into bulk-grown semi-insulating substrate material represents an optimum approach by providing excellent control and reproducibility over the doping parameters in the active layer. This paper will review development efforts carried out to capitalize on these inherent advantages and discuss the results obtained from transistors fabricated by this method. Device modeling has been used to investigate the effects of profile tailoring and has served as a guide for selecting implant species, doses, and energies. This effort has paralleled the development of the implantation technology, which has addressed the problems of selecting suitable substrate material, deposition of suitable capping material for the post-implantation anneal, the study of doping profiles, and the diffusion during the anneal. The advances made in these areas will be discussed along with the fabrication procedures for the low-noise FET's. Favorable doping profiles were obtained by using Se implants as evidenced by the small variation in the measured transconductance versus gate voltage. The excellent uniformity and reproducibility obtained in the active layer parameters have resulted in tightly distributed transconductances, pinchoff voltages, and S-parameters. Measured parameters from five wafers have given typical standard deviations of less than 10 percent of the mean value. Packaged transistors with a nominal gate length of 1 µm have yielded noise figures of 1.1 dB at 4 GHz with 12- dB associated gain, while 2.5-dB noise figures have been achieved at 15 GHz with 7-dB gain from transistors mounted on a low parasitic carrier. These improved RF results combined with a high level of reproducibility present ion implantation as a very attractive method for fabricating low-noise GaAs FET's.

Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

Method of producing light emitting semiconductor display

Abstract: A method is provided for mass production of a monolithic light emitting semiconductor display utilizing light emitting semiconductor devices formed in a monocrystalline silicon wafer and a covering of silicon dioxide formed into lens structures for controlling the light emitted by the semiconductor devices.

Manufacture of semiconductor device

Abstract: PURPOSE:To prevent the generation of poor opening and bad heat resistance of a semiconductor device by a method wherein at a back face of a substrate wafer a diffused layer having the same conducting type and a higher concentration is formed, and electrodes are prepared in the diffused layer to obtain a semiconductor having a good ohmic contact property. CONSTITUTION:An n -type epitaxial wafer doped with an appointed rate of phosphorus is formed on a substrate wafer 1 to form an epitaxial growth layer 11. Insulating films 7, 13 are prepared respectively on both sides of layer, a p-type base region 3 having electrodes is prepared in the growth layer 11, a diffused layer N having the same conducting type with the wafer 1 and a higher concentration is formed on the back face the wafer 1, the insulating film 13 is removed and a collector electrode 15 is formed in this diffused layer. By this way, a semiconductor having an extremely good ohmic contact property is obtained, and the generation of poor opening and bad heat resistance can be prevented.

Method for making terminal bumps on semiconductor wafers

Abstract: A method is described for making terminal pads, and more particularly solderable bump terminals on a plurality of semiconductor devices formed in a silicon wafer. Two spaced aluminum layers have electrical connection to the P-type region and the N-type region, respectively, of a PN junction of each device. A permanent protective glass layer is deposited over the active face of the wafer, having holes opened over the terminal pads. The wafer is covered with a temporary insulative masking layer except over terminal pad portions of the two aluminum layers, respectively. The wafer is submersed in a zinc plating solution and subsequently in a nickel plating solution to form a nickel bump on the terminal pad portions. A dark environment is provided about the PN junctions to avoid deplating aluminum from some of the aluminum pads due to photo-electric currents in the immersion solution. The masking layer prevents formation of unwanted spurious nickel bumps through cracks in the glass layer during the plating step and further reduces stray current paths to other regions of the wafer.

Diaphragm formation and pressure sensitivity in batch-fabricated silicon pressure sensors

Abstract: The formation of thin silicon diaphragms for batch-fabricated pressure sensors is examined. Several anisotropic silicon etchants are compared with respect to their etch rates and the surface finishes produced. Concentrated potassium hydroxide and ethylene diamine-pyrocatechol are found to be most compatible with sensor requirements. Both V-groove and boron etch-stop techniques are capable of controlling diaphragm thickness to within one micron or better, the latter removing wafer taper as a major source of variability. The effects of several process-induced diaphragm irregularities on the pressure sensitivities of piezoresistive and capacitive structures are examined using a finite-difference computer program. Diaphragm thickness is the most important parameter influencing pressure sensitivity in these structures, with resistor-diaphragm alignment and plate separation important secondary parameters in piezoresistive and capacitive devices, respectively.

Method for making integrated circuit transistors with isolation and substrate connected collectors utilizing simultaneous outdiffusion to convert an epitaxial layer

Abstract: In an integrated circuit structure a subsurface isolation layer is doped by diffusion during wafer processing. A substrate is first doped by ion implantation to create surface layer of the opposite conductivity type. Where substrate connections are to be created a heavier deposit of dopant is established using an impurity that will confer conductivity of the same polarity as the substrate. The wafer is then overgrown with an intrinsic layer that will be subsequently doped by diffusion of the ion implanted dopant. Then conventional integrated circuit processing is employed using buried conductive layers, epitaxy, isolation and device diffusion. The transistors thus produced can be designed to have isolation or substrate connected collectors as determined by the substrate surface doping.

Gate turn-off type thyristor with separate semiconductor resistive wafer providing emitter ballast

Abstract: A gate turn-off type thyristor comprises a semiconductor body having four sequentially contiguous layers, adjacent two of which are of opposite type conductivity and form a PN junction therebetween, one outer layer constituting a cathode layer of said body being divided into a plurality of mutually independent layer portions; and first and second electrodes packing said semiconductor material body. Between the cathode layer and the electrode is disposed a semiconductor wafer formed with high impurity concentration surface layers for permitting the wafer to ohmically contact with said cathode layer and said electrode, respectively.

Multicore connector of optical fiber

Abstract: PURPOSE:To perform axial alignment at the ends of the connectors with high accuracy and achieve the simplification of connecting work by simultaneously working holes for strand arrays and holes for axial alignment of connectors with high accuracy to a silicon single crystal wafer through etching of semiconductor surface treating techniques. CONSTITUTION:Holes 11 of regular quadrangular pyramid form for optical fiber strand arrays (the sizes thereof are about the sizes slightly larger than the strand diameters) and holes 12 of regular quadrangular pyramid form for axial alignment of the ends of the connectors with each other are simultaneously worked at an equal spacing on the surface of a silicone single crystal wafer 10 through crystal face direction selective etching being semiconductor surface treating techniques. For example, square patterns are formed with a mask material for etching such as of oxide film or the like on the surface of a silicon single crystal wafer and etching is done. Thereby, the holes may be worked in the accuracy of micron order.

Integrated solar cell array

Abstract: An integrated, monolithic array of solar cells wherein isolation between cells permits series interconnection of the cells to provide an output voltage for the array equal to the sum of the voltages of the unit cells. Although normal PN junction isolation is ineffective when exposed to light, the present structure includes a form of junction isolation that is effective when exposed to light, or to other radiation. For example, a band of heavily doped P-type silicon, formed by thermomigration of aluminum through an N-type wafer, provides such isolation.

Process of manufacturing semiconductor devices

Abstract: On a common semiconductor wafer constituted by a PN-lamination are formed a number of semiconductor device units. Recessed grooves are formed into this wafer by an etching technique at such sites as one corresponding to the boundaries of the respective adjacent semiconductor device units. To protect the PN-junctions of the wafer exposed on the etched grooves, these surfaces are coated with a thermo-setting resin. Thereafter, the semiconductor wafer is severed apart at the respective recessed grooves into respective individual chips of semiconductor devices.

MOS Semiconductor process utilizing a two-layer oxide forming technique

Abstract: Process for the manufacture of MOS devices by providing wafer of P-semiconductor grade silicon in a deposition reactor. The wafer is heated to a temperature of approximately 950° C. while subjecting the wafer to dry oxygen gas to produce between a very thin layer (50-250A) of silica (SiO 2 ) on a surface of the wafer. While elevating the temperature of the wafer to approximately 1000° C., the chamber is purged with nitrogen and then hydrogen gas. After an introduction of carbon dioxide gas into the chamber, silane (SiH 4 ) or dichlorosilane gas is bled into the chamber. The silane reacts with the CO 2 to deposit SiO 2 on the previously formed thermal SiO 2 . The two layers of SiO 2 may then be annealed to provide a highly coherent, defect-free gate oxide for MOS integrated circuits.

Apparatus for the treatment of wafer materials by plasma reaction

Abstract: An automatic apparatus for the treatment of wafer materials by plasma reaction is proposed in which the wafers are sent into the plasma reaction chamber one by one and yet the atmospheric air is never introduced into the reaction chamber between the successive reaction steps for two wafers by use of two rotary vacuum valves which also serve as wafer transmitters into and out of the reaction chamber and a rotary wafer table inside the reaction chamber, all being installed on an inclined base table to effect the downward spontaneous movement of the wafer under treatment by gravity.