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Alessio Spessot
Researcher at Katholieke Universiteit Leuven
Publications - 124
Citations - 1725
Alessio Spessot is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Metal gate & CMOS. The author has an hindex of 16, co-authored 115 publications receiving 1113 citations. Previous affiliations of Alessio Spessot include Micron Technology & University of Modena and Reggio Emilia.
Papers
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Journal ArticleDOI
Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node
Doyoung Jang,D. Yakimets,Geert Eneman,P. Schuddinck,Marie Garcia Bardon,Praveen Raghavan,Alessio Spessot,Diederik Verkest,Anda Mocuta +8 more
TL;DR: In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFET and nanowire transistors for sub-7-nm node.
Proceedings ArticleDOI
Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration
Hans Mertens,Romain Ritzenthaler,V. Peña,Gaetano Santoro,K. Kenis,Andreas Schulze,Eugenio Dentoni Litta,S. A. Chew,Katia Devriendt,r. Chiarella,Steven Demuynck,D. Yakimets,Doyoung Jang,Alessio Spessot,Geert Eneman,A. Dangol,P. Lagrain,Hugo Bender,Shiyu Sun,Mikhail Korolik,Dimitri R. Kioussis,M. Kim,K-.H. Bu,S. C. Chen,M. Cogorno,J. Devrajan,J. Machillot,Naomi Yoshida,Nam-Sung Kim,Kathy Barla,Dan Mocuta,Naoto Horiguchi +31 more
TL;DR: In this article, a vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFET with in-situ doped source-drain stressors and dual work function metal gates is presented.
Proceedings ArticleDOI
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
D. Yakimets,M. Garcia Bardon,Doyoung Jang,P. Schuddinck,Yasser Sherazi,Pieter Weckx,Kenichi Miyaguchi,Bertrand Parvais,Praveen Raghavan,Alessio Spessot,Diederik Verkest,Anda Mocuta +11 more
TL;DR: In this paper, the authors show how 5.5 tracks standard cells can be enabled at gate pitch 42 nm and metal pitch 21 nm and achieve 60% active power reduction from the 7nm node.
Journal ArticleDOI
Fabrication by electron beam induced deposition and transmission electron microscopic characterization of sub-10-nm freestanding Pt nanowires
TL;DR: In this article, a method to reduce the size and improve the crystal quality of freestanding nanowires grown by electron beam induced deposition from a platinum metal organic precursor in a dual beam system was presented.
Patent
Method for tuning the effective work function of a gate structure in a semiconductor device
TL;DR: In this article, a method for tuning the effective work function of a gate structure in a semiconductor device is described, where an interconnect structure of the integrated circuit on top of the gate structure is provided.