S
Steven Demuynck
Researcher at Katholieke Universiteit Leuven
Publications - 142
Citations - 1995
Steven Demuynck is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Hyperfine structure & Dielectric. The author has an hindex of 21, co-authored 137 publications receiving 1621 citations. Previous affiliations of Steven Demuynck include IMEC.
Papers
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Proceedings ArticleDOI
AC NBTI studied in the 1 Hz -- 2 GHz range on dedicated on-chip CMOS circuits
Roberto Fernández,Ben Kaczer,Axel Nackaerts,Steven Demuynck,Rosana Rodriguez,Montserrat Nafria,Guido Groeseneken +6 more
TL;DR: In this article, on-chip circuits specially designed and fabricated for the purpose of measuring the effect of AC NBTI on an individual, well-defined device in the wide frequency range on a single wafer.
Proceedings ArticleDOI
Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
Hans Mertens,Romain Ritzenthaler,Andriy Hikavyy,Min-Soo Kim,Z. Tao,Kurt Wostyn,S. A. Chew,A. De Keersgieter,G. Mannaert,Erik Rosseel,Tom Schram,Katia Devriendt,Diana Tsvetanova,Harold Dekkers,Steven Demuynck,Adrian Chasin,E. Van Besien,A. Dangol,S. Godny,Bastien Douhard,N. Bosman,O. Richard,J. Geypen,Hugo Bender,Kathy Barla,Dan Mocuta,Naoto Horiguchi,A. V-Y. Thean +27 more
TL;DR: In this paper, gate-all-around (GAA) n-and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs) were reported.
Proceedings ArticleDOI
Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates
Hans Mertens,Romain Ritzenthaler,Adrian Chasin,Tom Schram,Eddy Kunnen,Andriy Hikavyy,Lars-Ake Ragnarsson,Harold Dekkers,T. Hopf,Kurt Wostyn,Katia Devriendt,S. A. Chew,Min-Soo Kim,Y. Kikuchi,Erik Rosseel,G. Mannaert,Stefan Kubicek,Steven Demuynck,A. Dangol,N. Bosman,J. Geypen,Patrick Carolan,Hugo Bender,Kathy Barla,Naoto Horiguchi,Dan Mocuta +25 more
TL;DR: In this paper, the authors report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices.
Proceedings ArticleDOI
Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration
Hans Mertens,Romain Ritzenthaler,V. Peña,Gaetano Santoro,K. Kenis,Andreas Schulze,Eugenio Dentoni Litta,S. A. Chew,Katia Devriendt,r. Chiarella,Steven Demuynck,D. Yakimets,Doyoung Jang,Alessio Spessot,Geert Eneman,A. Dangol,P. Lagrain,Hugo Bender,Shiyu Sun,Mikhail Korolik,Dimitri R. Kioussis,M. Kim,K-.H. Bu,S. C. Chen,M. Cogorno,J. Devrajan,J. Machillot,Naomi Yoshida,Nam-Sung Kim,Kathy Barla,Dan Mocuta,Naoto Horiguchi +31 more
TL;DR: In this article, a vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFET with in-situ doped source-drain stressors and dual work function metal gates is presented.
Proceedings ArticleDOI
The Complementary FET (CFET) for CMOS scaling beyond N3
J. Ryckaert,P. Schuddinck,Pieter Weckx,G. Bouche,Benjamin Vincent,Jeffrey Smith,Yasser Sherazi,Arindam Mallik,Hans Mertens,Steven Demuynck,T. Huynh Bao,Anabela Veloso,Naoto Horiguchi,Anda Mocuta,Dan Mocuta,Juergen Boemmels +15 more
TL;DR: The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework and can eventually outperform the finFET device and meet the N3 targets in power and performance.