K
Katia Devriendt
Researcher at Katholieke Universiteit Leuven
Publications - 85
Citations - 1833
Katia Devriendt is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Metal gate & CMOS. The author has an hindex of 20, co-authored 80 publications receiving 1447 citations.
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Proceedings ArticleDOI
Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
Hans Mertens,Romain Ritzenthaler,Andriy Hikavyy,Min-Soo Kim,Z. Tao,Kurt Wostyn,S. A. Chew,A. De Keersgieter,G. Mannaert,Erik Rosseel,Tom Schram,Katia Devriendt,Diana Tsvetanova,Harold Dekkers,Steven Demuynck,Adrian Chasin,E. Van Besien,A. Dangol,S. Godny,Bastien Douhard,N. Bosman,O. Richard,J. Geypen,Hugo Bender,Kathy Barla,Dan Mocuta,Naoto Horiguchi,A. V-Y. Thean +27 more
TL;DR: In this paper, gate-all-around (GAA) n-and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs) were reported.
Proceedings ArticleDOI
Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates
Hans Mertens,Romain Ritzenthaler,Adrian Chasin,Tom Schram,Eddy Kunnen,Andriy Hikavyy,Lars-Ake Ragnarsson,Harold Dekkers,T. Hopf,Kurt Wostyn,Katia Devriendt,S. A. Chew,Min-Soo Kim,Y. Kikuchi,Erik Rosseel,G. Mannaert,Stefan Kubicek,Steven Demuynck,A. Dangol,N. Bosman,J. Geypen,Patrick Carolan,Hugo Bender,Kathy Barla,Naoto Horiguchi,Dan Mocuta +25 more
TL;DR: In this paper, the authors report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices.
Journal ArticleDOI
Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs
Anne Vandooren,Daniele Leonelli,Rita Rooyackers,Andriy Hikavyy,Katia Devriendt,Marc Demand,Roger Loo,Guido Groeseneken,Cedric Huyghebaert +8 more
TL;DR: In this article, the authors report on the integration of vertical nTunnel FETs (TFETs) with SiGe hetero-junction and analyzes the presence of trap-assisted tunneling impacting the device behavior.
Proceedings ArticleDOI
Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration
Hans Mertens,Romain Ritzenthaler,V. Peña,Gaetano Santoro,K. Kenis,Andreas Schulze,Eugenio Dentoni Litta,S. A. Chew,Katia Devriendt,r. Chiarella,Steven Demuynck,D. Yakimets,Doyoung Jang,Alessio Spessot,Geert Eneman,A. Dangol,P. Lagrain,Hugo Bender,Shiyu Sun,Mikhail Korolik,Dimitri R. Kioussis,M. Kim,K-.H. Bu,S. C. Chen,M. Cogorno,J. Devrajan,J. Machillot,Naomi Yoshida,Nam-Sung Kim,Kathy Barla,Dan Mocuta,Naoto Horiguchi +31 more
TL;DR: In this article, a vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFET with in-situ doped source-drain stressors and dual work function metal gates is presented.
Journal ArticleDOI
Identification of the Sequence CH(2Π) + C2H2 → C3H2 + H (and C3H + H2) Followed by C3H2 + O → C2H + HCO (or H + CO) as C2H Source in C2H2/O/H Atomic Flames
TL;DR: In this paper, the authors established the dominant C2H formation pathway in low-pressure acetylene/atomic oxygen flames at 600 K in an isothermal discharge-flow reactor at a pressure of 2 Torr with He as bath gas.