Showing papers by "Antonio J. Lopez-Martin published in 2004"
TL;DR: In this paper, a design principle for very low-voltage analog signal processing in CMOS technologies is presented, based on the use of quasi-floating gate (QFG) MOS transistors.
Abstract: A novel design principle for very low-voltage analog signal processing in CMOS technologies is presented. It is based on the use of quasi-floating gate (QFG) MOS transistors. Similar to multiple input floating gate (MIFG) MOS transistors, a weighted averaging of the inputs accurately controlled by capacitance ratios can be obtained, which is the basic operating principle. Nevertheless, issues often encountered in MIFG structures, such as the initial charge trapped in the floating gates or the gain-bandwidth product degradation, are not present in QFG configurations. Several CMOS circuit realizations using open- and closed-loop topologies, have been designed. They include analog switches, mixers, programmable-gain amplifiers, track and hold circuits, and digital-to-analog converters. All these circuits have been experimentally verified, confirming the usefulness of the proposed technique for very low-voltage applications.
234 citations
01 Jan 2004
76 citations
TL;DR: Experimental results of a test chip prototype in 0.5-µm CMOS technology are presented that verify the proposed technique and suggest simple schemes to generate the gate control voltages for the MOS transistors implementing large resistors so that they remain in high resistive state with large signal variations.
Abstract: The implementation of large-valued floating resistive elements using MOS transistors in subthreshold region is addressed. The application of these elements to bias wideband AC coupled amplifiers is discussed. Simple schemes to generate the gate control voltages for the MOS transistors implementing large resistors so that they remain in high resistive state with large signal variations are discussed. Experimental results of a test chip prototype in 0.5-µm CMOS technology are presented that verify the proposed technique.
47 citations
TL;DR: In this paper, the authors combined the combined use of local commonmode feedback and class AB input stages to achieve very low static power consumption, bandwidth enhancement, and very high slew rate.
Abstract: Novel class AB OTA topologies result from the combined use of local common-mode feedback and class AB input stages. They can operate at low supply voltage and feature very low static power consumption, bandwidth enhancement, and very high slew rate. Measurement results of a 0.5 /spl mu/m CMOS prototype show slew rate and unity-gain bandwidth enhancement factors of 180 and 4.5, respectively, compared to a conventional one-stage OTA.
46 citations
TL;DR: Novel adaptive biasing techniques, suited for low-voltage operation, are presented, which provide small and accurately controlled quiescent currents, which are automatically boosted when an input signal is applied.
Abstract: Novel adaptive biasing techniques, suited for low-voltage operation, are presented. They provide small and accurately controlled quiescent currents, which are automatically boosted when an input signal is applied. Measurement results of an OTA using these techniques and fabricated in a 0.5 µm CMOS technology show a slew rate of more than 40 V/µs for an 80 pF load capacitance and a static power consumption of only 140 µW.
35 citations
TL;DR: A fully integrated CMOS implementation of a continuous-time analog median filter that uses two compact analog circuits as building blocks to implement the variable delay and median detection and a new fast technique for parallel image processing is presented.
Abstract: A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on current saturating transconductance comparators, while the time delay is implemented using first-order all-pass filters. Both circuits allow modular expansion for the implementation of large median filter array processors. Based on these blocks, a new fast technique for parallel image processing is presented. It is shown that an image of 91/spl times/80 pixels can be processed in less than 8 /spl mu/s using an array of median filter cells. Experimental results of a test chip prototype in 2-/spl mu/m CMOS MOSIS technology are presented.
29 citations
TL;DR: In this article, a four-quadrant analog CMOS multiplier with a wide dynamic range and high linearity is presented, where the capacitive voltage division obtained by the use of floating-gate MOS transistors, and an accurate wide-swing current mirror based on active bootstrapping, allow a wide input range, low harmonic distortion, and highlinearity.
Abstract: A compact, four-quadrant analog CMOS multiplier featuring wide dynamic range is presented. The capacitive voltage division obtained by the use of Floating-Gate MOS (FGMOS) transistors, and an accurate wide-swing current mirror based on active bootstrapping, allow a wide input range, low harmonic distortion, and high linearity. Simulation and measurement results for a 0.8 μm CMOS prototype demonstrate the validity of the proposed approach.
21 citations
23 May 2004
TL;DR: A compact CMOS low-voltage analog four quadrant transconductance amplifier based on flipped voltage followers and transistors operating in triode mode is introduced and experimentally verified and extension of the proposed circuit into a generalized multiplier with "n" input pairs is discussed.
Abstract: A compact CMOS low-voltage analog four quadrant transconductance amplifier based on flipped voltage followers and transistors operating in triode mode is introduced and experimentally verified. The circuit has a feedforward architecture and features high bandwidth, low distortion, and operates with a single supply voltage of 1.5 V in a 0.5 /spl mu/m CMOS technology. Extension of the proposed circuit into a generalized multiplier with "n" input pairs is discussed. Simulations and experimental results are shown that verify the characteristics of the proposed multiplier.
21 citations
TL;DR: In this paper, a low-voltage CMOS square-root domain filter is proposed based on the large-signal behavior of a well-known class-AB linear transconductor.
Abstract: A novel approach to the design of low-voltage CMOS Square-Root Domain filters is presented. It is based on the large-signal behaviour of a well-known class-AB linear transconductor. A first-order filter is built employing three such transconductors, featuring simplicity and compactness. Measurement results for an experimental prototype in 0.8 µm CMOS validate the technique proposed. The filter operates with a single supply voltage of 1.5 V and can be tuned in more than one decade.
18 citations
23 May 2004
TL;DR: A new compact low-voltage differential linear transconductor based on a straightforward modification of a classical scheme that leads to class-AB linear operation that can find applications in low power gm-C filters.
Abstract: This paper presents a new compact low-voltage differential linear transconductor. The proposed transconductor is based on a straightforward modification of a classical scheme that leads to class-AB linear operation. The transconductor has been designed using a 0.8 /spl mu/m CMOS technology (VT /spl sim/ 0.8 V) and it is operated at 1.5 V with only 42 /spl mu/W of quiescent power consumption and 40 MHz bandwidth. This transconductor can find applications in low power gm-C filters.
17 citations
23 May 2004
TL;DR: A low voltage rail to rail highly linear voltage to current conversion technique is presented, based on flipped voltage follower regulated cascode mirror, which shows that the ADC works in range up to 202 KS/s with a single supply of 1.8 V.
Abstract: A low voltage rail to rail highly linear voltage to current conversion technique is presented. This is based on flipped voltage follower regulated cascode mirror. As an example application of this technique, a current mode successive approximation analog-to-digital converter (ADC) architecture is presented. Cadence simulation results of the 8-bit ADC are presented which show that the ADC works in range up to 202 KS/s with a single supply of 1.8 V and 3.21mW static power dissipation in 0.5/spl mu/m CMOS technology.
TL;DR: A new compact CMOS continuous-time analog rank-order filter topology is presented that has low voltage and low power consumption requirements, and experimental results are presented that verify the functionality and accuracy of the circuit.
Abstract: A new compact CMOS continuous-time analog rank-order filter topology is presented. The hardware complexity grows linearly with the number of inputs at the rate of only two transistors per input. The implementation is based on a multiple input differential structure. The rank is programmable with the tail current source for all rank-order values from the Min to the Max case. The circuit has low voltage and low power consumption requirements. Experimental results are presented that verify the functionality and accuracy of the circuit. Simulation results show satisfactory operation in the 100-MHz frequency range for 0.5-/spl mu/m CMOS technology and using a single 1.8-V supply. Two buffered versions of the circuit and efficient techniques for reduction of corner errors are also discussed.
TL;DR: In this article, a technique for operating MOS translinear loops at very low supply voltages is described, based on the use of Flipped Voltage Followers for biasing the loops, which can be successfully applied to a varied repertory of low-voltage analog circuits, such as squarers, multipliers, filters, oscillators, and RMS-DC converters.
Abstract: A novel technique for operating MOS Translinear loops at very low supply voltages is described, based on the use of Flipped Voltage Followers for biasing the loops. The resulting topologies, suited to standard CMOS processes, can be successfully applied to a varied repertory of low-voltage analog circuits, such as squarers, multipliers, filters, oscillators, and RMS-DC converters. Measurement results for a geometric-mean and a squarer/divider circuit demonstrate on silicon the usefulness of this technique.
TL;DR: A practical approach for teaching random signals and noise is described, where theoretical aspects are complemented by several laboratory experiments enriching the student's understanding on basic topics, such as histograms and estimation of probability density function, autocorrelation function, and power spectral density.
Abstract: A practical approach for teaching random signals and noise is described, where theoretical aspects are complemented by several laboratory experiments enriching the student's understanding on basic topics, such as histograms and estimation of probability density function, autocorrelation function, and power spectral density. The equipment required is minimum and inexpensive. In fact, the existing equipment of laboratory benches employed for an electronic instrumentation course has been used. No investment from our institution has been necessary due to the full exploitation of the potentials of the existing instruments and their PC connectivity.
23 May 2004
TL;DR: Electronically programmable current mirrors able to operate in weak or moderate inversion provide a continuous transconductance tuning range of two decades without affecting the large input signal range available.
Abstract: A new CMOS transconductor with wide transconductance tuning range and very low distortion is presented. The input stage features a highly linear conversion of the input voltage into current form. Electronically programmable current mirrors able to operate in weak or moderate inversion provide a continuous transconductance tuning range of two decades without affecting the large input signal range available. Measurement results of a prototype fabricated in a 0.5/spl mu/m CMOS technology shows a THD of -66.5dB for a 100 kHz differential input of 2V/sub pp/.
23 May 2004
TL;DR: New low-voltage two stage fully differential class AB/AB op-amp architectures with high slew rate and rail-to-rail operation with a single supply voltage are introduced.
Abstract: New low-voltage two stage fully differential class AB/AB op-amp architectures with high slew rate are introduced. The proposed circuits are very compact. The output stage does not require a quiescent current control circuit. Simulations are shown verifying high slew rate and rail-to-rail operation with a single supply voltage of 1.5 V and 0.5 /spl mu/m CMOS technology with threshold voltages close to 1 V. The proposed architectures can operate with sub-volt supplies and rail-to-rail output swing in 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies.
TL;DR: In this paper, a first-order CMOS log-domain filter is presented, which allows operation with a single 1 V supply while maintaining at the same time a large input range.
Abstract: A novel first-order CMOS log-domain filter is presented. The internal voltage swing compression due to its instantaneous voltage companding nature, together with the use of Floating-Gate MOS transistors and its class AB differential topology, allows operation with a single 1 V supply while maintaining at the same time a large input range. Moreover, operation in weak inversion leads to very low power consumption. The filter can be tuned in more than one decade through its bias currents. Simulation and measurement results of an experimental prototype fabricated in a 0.8 μm CMOS technology demonstrate on silicon the feasibility of the proposed technique, which can be readily extended to higher-order filters.
TL;DR: In this paper, two nonlinear transconductors that can be employed for building CMOS current-mode filters are presented and their performances compared to previously proposed topologies aimed at the same goal.
Abstract: Two novel nonlinear CMOS transconductors that can be employed for building CMOS current-mode filters are presented and their performances compared to formerly proposed topologies aimed at the same goal. The first one is based on a previous topology proposed by the authors, where a new biasing procedure leads to an improved performance for low supply voltages. The second one follows a novel approach, based on cascading a transresistor and a transconductor. The analysis is complemented with a more general approach based on the identification of translinear loops present in the circuit. Both nonlinear transconductors can operate at supply voltages as low as one V GS plus two V DS of a saturated MOSFET. CMOS current-mode filters based on these blocks are built following companding techniques, and their correct operation is validated by simulation and experimental results.
23 May 2004
TL;DR: In this paper, two schemes for power efficient gain programmable V-I conversion based on class AB CMOS mirrors are introduced, which allow for high-speed programmable precision rectification.
Abstract: Two schemes for power efficient gain programmable V-I conversion based on class AB CMOS mirrors are introduced. These allow for high-speed gain programmable precision rectification. Experimental results from a test chip prototype, in 0.5 /spl mu/m CMOS technology with /spl plusmn/1 V supplies are shown that validate the proposed circuits.
05 Jan 2004
TL;DR: Some techniques for continuous-time operation of low-voltage analog CMOS circuits are revisited based on the utilization of static, dynamic and switched floating voltage sources, on floating and quasi-floating gate transistors and on a versatile cell denoted flipped voltage follower.
Abstract: In this paper some techniques for continuous-time operation of low-voltage analog CMOS circuits are revisited These are based on the utilization of static, dynamic and switched floating voltage sources, on floating and quasi-floating gate transistors and on a versatile cell denoted flipped voltage follower. Circuits based on these techniques operate with a single supply voltage close to a transistor's threshold voltage.
03 Nov 2004
TL;DR: In this article, a low-voltage CMOS class AB OTA with rail to rail input/output swing, low supply voltage and very high slew rate is presented, based on a combination of floating gate transistors, local common-mode feedback and class AB input.
Abstract: A low-voltage CMOS class AB OTA with rail to rail input/output swing, low supply voltage and very high slew rate is presented. The scheme is based on a combination of floating gate transistors, local common-mode feedback and class AB input. The proposed OTA does not suffer from typical reliability problems related with initial charge trapped in the floating gates devices. Simulation and experimental in 0.5 /spl mu/m CMOS technology verify the scheme operating with 1V dual supply and 1.9 Vp-p input and output swing.
23 May 2004
TL;DR: The use of simple and extremely accurate voltage buffers to drive two MOS transistors in triode region is employed to obtain a very linear voltage-to-current conversion.
Abstract: The use of simple and extremely accurate voltage buffers to drive two MOS transistors in triode region is employed to obtain a very linear voltage-to-current conversion. Transconductance can be simply and precisely adjusted using DC level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-/spl mu/m CMOS technology show a -54 dB THD at 100 kHz for 80-/spl mu/A peak-to-peak outputs, using a 2-V supply. Silicon area is 0.07 mm/sub 2/ and static power consumption is 0.92 mW.
23 May 2004
TL;DR: A simple modification to a conventional single-stage OTA based on the combined use of local common-mode feedback and very efficient class AB input stages leads to three proposals for class AB amplifier topologies that operate at low voltage and feature very low static power consumption, bandwidth enhancement, and very high slew rate.
Abstract: A simple modification to a conventional single-stage OTA based on the combined use of local common-mode feedback and very efficient class AB input stages leads to three proposals for class AB amplifier topologies. They operate at low voltage and feature very low static power consumption, bandwidth enhancement, and very high slew rate. Measurement results in a 0.5-/spl mu/m CMOS technology confirm the mentioned improvements.
15 Nov 2004
TL;DR: A family of low-voltage power-efficient class AB CMOS operational transconductance amplifiers (OTAs) is described, based on the combination of adaptive biasing techniques and resistive local common-mode feedback (LCMFB), which provides increased dynamic current boosting and gain-bandwidth product (GBW).
Abstract: A family of low-voltage power-efficient class AB CMOS operational transconductance amplifiers (OTAs) is described. It is based on the combination of adaptive biasing techniques and resistive local common-mode feedback (LCMFB), which provides increased dynamic current boosting and gain-bandwidth product (GBW). The different classes of AB OTA topologies presented result from the combination of various adaptive biasing schemes and LCMFB. A 0.5-/spl mu/m CMOS implementation of three different OTAs shows enhancement factors of slew-rate and GBW up to 280 and 3.6, respectively, for an 80-pF load, compared to a conventional class A OTA with the same quiescent currents and supply voltage. The overhead in area, noise, and static power consumption, is minimal.
01 Jan 2004
TL;DR: In this paper, an undergraduate course in communication theory aimed at Spanish Telecommunication Engineering students was augmented with various experiments introduced to enrich the student's understanding on basic topics such as linear and angular modulations, random signals and noise.
Abstract: An undergraduate course in Communication Theory, aimed at Spanish Telecommunication Engineering students, has been augmented with various experiments introduced to enrich the student's understanding on basic topics such as linear and angular modulations, random signals and noise. The equipment required is minimum and inexpensive. In fact, the equipment already available in lab benches of an Electronic Instrumentation course has been used with some additional inexpensive, off-the-shelf electronics. The full exploitation of the potentials of the existing instruments and their PC connectivity made additional investment unnecessary.
23 May 2004
TL;DR: A technique for implementing class AB differential input stages is proposed, combining the input stage proposed and local common-mode feedback with two-resistors to obtain high slew rate and very low static power consumption.
Abstract: A technique for implementing class AB differential input stages is proposed It is well suited for low voltage operation, and can be applied to single-stage or two-stage OTAs in continuous time or sampled-data systems In order to illustrate this approach an OTA is presented, combining the input stage proposed and local common-mode feedback with two-resistors to obtain high slew rate and very low static power consumption Measurement results from a 05-/spl mu/m CMOS implementation with supply voltages of /spl plusmn/1 V show a slew rate of 50V//spl mu/s for an 80-pF load capacitance, and a static power consumption of only 120 /spl mu/W Silicon area for this OTA is 0024mm/sup 2/
23 May 2004
TL;DR: A new scheme for analog rank order filtering based on analog buffers is presented, characterized by high-speed, high-precision and simple circuit architectures.
Abstract: A new scheme for analog rank order filtering based on analog buffers is presented. This scheme is characterized by high-speed, high-precision and simple circuit architectures. The overall architecture exhibits linear complexity with number of inputs (O(n)) at the rate of one buffer per input. Rank is easily programmable with tail current source for all rank order values from the max to the min case and its precision does not depend on the accuracy of the current copy. Simulation results are presented that verify functionality and accuracy of the proposed circuit.