다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

https://iopscience.iop.org/article/10.35848/1882-0786/abc787/pdf

Defect engineering in SiC technology for high-voltage power devices

Silicon carbide (SiC) power transistors have started gaining significant importance in various application areas of power electronics. During the last decade, SiC power transistors were counted not only as a potential, but also more importantly as an alternative to silicon counterparts in applications where high efficiency, high switching frequencies, and operation at elevated temperatures are targeted. Various SiC device designs have been proposed and excessive investigations in terms of simulation and experimental studies have shown their advantageous performance compared to silicon technology. On a system-level, however, the design of gate and base drivers for SiC power transistors is very challenging. In particular, a sophisticated driver design is not only associated with properly switching the transistor and decreasing the switching power losses, but also it must incorporate protection features, as well as comply with the electromagnetic compatibility. This paper shows an overview of the gate and base drivers for SiC power transistors which have been proposed by several highly qualified scientists. In particular, the basic operating principle of each driver along with their applicability and drawbacks are presented. For this overview, the three most successful SiC power transistors are considered: junction-field-effect transistors, bipolar-junction transistors, and metal-oxide-semiconductor field-effect transistors. Last but not least, future challenges on gate and base drivers design are also presented.

Gate and Base Drivers for Silicon Carbide Power Transistors: An Overview

This letter reports the first implementation of a hydrogen-plasma-based edge termination technique (HPET) in vertical GaN p-n power diodes grown on bulk GaN substrates using metalorganic chemical vapor deposition. The device with a 9- $\mu \text{m}$ -thick drift layer exhibited a high breakdown voltage ( ${V}_{\textsf {bd}}$ ) of 1.57 kV, a low ON-resistance ( ${R}_{\mathrm{ ON}}$ ) of 0.45 $\text{m}\Omega ~ \cdot $ cm2 (or 0.70 $\text{m}\Omega ~\cdot $ cm2 with current spreading considered) and a high Baliga’s figure-of-merit ( ${V}^{\textsf {2}}_{\textsf {bd}}/{R}_{\mathrm{ ON}}$ ) of 5.5 GW/cm2 (or 3.6 GW/cm2) without passivation or field plate, which are close to the theoretical limit of GaN. This technique enabled a significant reduction in leakage current (~106 times at −300 V) and a huge enhancement in ${V}_{\textsf {bd}}$ (from ~300 V to 1.57 kV). Furthermore, the device showed good forward characteristics with a turn-ON voltage of 3.5 V, an ON-current of ~2 kA/cm2 (or 1.3 kA/cm2), an ON/OFF ratio of ~109, and an ideality factor of 1.4. This work shows the HPET can serve as an effective, low cost, and easy-to-implement edge termination technique for high voltage and high power GaN p-n power diodes.

High Performance Vertical GaN-on-GaN p-n Power Diodes With Hydrogen-Plasma-Based Edge Termination

Implantation-free mesa-etched ultra-high-voltage (0.08 mm2) 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured, and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension is utilized to obtain a high and stable breakdown voltage without ion implantation. The open-base blocking voltage of 15.8 kV at a leakage current density of 0.1 mA/cm2 is achieved. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared.

15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain

Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/ $\mathrm{cm}^{2}$ is obtained for the device with an active area of 0.065 $\mathrm{mm}^{2}$ . A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific on-resistance ( $R_{\mathrm{{\scriptstyle ON}}}$ ) of 28 m $\Omega \cdot {\rm cm^{2}}$ was obtained.

/pdf/5-8-kv-implantation-free-4h-sic-bjt-with-multiple-shallow-4j2025208l.pdf

5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension

Constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on recently manufactured commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs) from three vendors. Abrupt changes of the electric field acceleration parameters ( $\gamma $ ) are observed at oxide electric fields ( $E_{ox}$ ) around 8.5 MV/cm to 9 MV/cm for all commercial MOSFETs. Gate leakage currents and threshold voltage shifts are also monitored under different oxide fields ( $E_{ox}= {\mathrm {8 MV/cm}}$ and 10 MV/cm). The results suggest the failure mode under high oxide electric field is modified by impact ionization or Anode Hole Injection (AHI) induced hole trapping. This observation agrees with previously published oxide reliability studies on SiC MOSFETs and suggests that constant-voltage TDDB measurements need to be carefully performed under low oxide fields to avoid lifetime overestimation caused by hole trapping. The extrapolated $t_{63\%}$ lifetimes (times to 63% failures) from TDDB measurements performed at $E_{ox} are longer than 108 hours at 150°C for all vendors. The predicted lifetimes at $E_{ox}= {\mathrm {4 MV/cm}}$ demonstrate more than 105 times increases than the oxide lifetimes reported a decade ago, showing promising progress in SiC technology.

Time-Dependent Dielectric Breakdown of Commercial 1.2 kV 4H-SiC Power MOSFETs

Degradation-free ultrahigh-voltage (>10 kV) PiN diodes using on-axis 4H-SiC with low forward voltage drop (V F = 3.3 V at 100 A/cm2) and low differential on-resistance (R ON = 3.4 mΩ.cm2) are fabricated, measured, and analyzed by device simulation. The devices show stable on-state characteristics over a broad temperature range up to 300 °C. They show no breakdown up to 10 kV, i.e., the highest blocking capability for 4H-SiC devices using on-axis to date. The minority carrier lifetime (τ P ) is measured after epitaxial growth by time resolved photoluminescence (TRPL) technique at room temperature. The τ P is measured again after device fabrication by open circuit voltage decay (OCVD) up to 500 K.

Conductivity modulated on-axis 4H-SiC 10+ kV PiN diodes

High-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (JC), lower on-resistance (RON), and more uniform current distribution. A maximum current gain ( $\beta $ ) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs are measured from room temperature to 500 °C. An open-base breakdown voltage (VCEO) of >50 V is measured for the devices.

Arash Salemi

Papers

15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain

5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension

Time-Dependent Dielectric Breakdown of Commercial 1.2 kV 4H-SiC Power MOSFETs

Conductivity modulated on-axis 4H-SiC 10+ kV PiN diodes

500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits