Journal ArticleDOI
Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications
Reads0
Chats0
TLDR
In this article, the analog performance of a double-gate n-type tunnel field effect transistor (n-TFET) with a relatively small body thickness (10 nm) was investigated.Abstract:
In this paper, the analog performance is reported for the first time for a double-gate (DG) n-type tunnel field-effect transistor (n-TFET) with a relatively small body thickness (10 nm), which shows good drain current saturation. The device parameters for analog applications, such as transconductance gm, transconductance-to-drive current ratio gm/ID, drain resistance RO, intrinsic gain, and unity-gain cutoff frequency fT, are studied for DG n-TFET, with the help of a device simulator, and compared with that for a similar DG n-MOSFET. Although gm is lower, gm/ID is found to be higher in TFET, except for small values of the gate overdrive voltage, indicating that a TFET can produce higher gain at the same power level than a MOSFET. An extremely high RO and, hence, a high intrinsic gain are also observed for a TFET as compared with that for a MOSFET. A complementary TFET amplifier is found to have more than one order of magnitude higher voltage gain than its MOS counterpart. It is also demonstrated that the drain resistance and, hence, the device gain significantly degrade for increasing body thickness of a TFET.read more
Citations
More filters
Journal ArticleDOI
Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET
TL;DR: In this article, the analog performance as well as some new RF figures of merit are reported for the first time of a gate stack double gate (GS-DG) metal oxide semiconductor field effect transistor (MOSFET) with various gates and channel engineering.
Journal ArticleDOI
Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability
Jaya Madan,Rishu Chaujar +1 more
TL;DR: In this article, the impact of interface traps, both donor and acceptor interface charges, present at the Si/SiO2 interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET) was investigated.
Journal ArticleDOI
A 2-D Analytical Model for Double-Gate Tunnel FETs
TL;DR: In this paper, a 2D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2D Poisson's equation is presented.
Journal ArticleDOI
Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET
TL;DR: An attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation.
Journal ArticleDOI
Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications
Qing-Tai Zhao,S. Richter,C. Schulte-Braucks,Lars Knoll,Sebastian Blaeser,G. V. Luong,Stefan Trellenkamp,A. Schafer,A. T. Tiedemann,Jean-Michel Hartmann,Konstantin Bourdelle,Siegfried Mantl +11 more
TL;DR: In this paper, the Wentzel-Kramers-Brillouin approximation for band-to-band tunneling (BTBT) is guided by various performance boosters for Si TFETs.
References
More filters
Book
CMOS Analog Circuit Design
TL;DR: In this article, the authors present a simple MOS LARGE-SIGNAL MODEL (SPICE Level 1) and a small-signal model for the MOS TRANSISTOR.
Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
Tunnel field-effect transistor without gate-drain overlap
TL;DR: In this article, the authors generalized the tunnel field effect transistor configuration by allowing a shorter gate structure, which is especially attractive for vertical nanowire-based transistors, and demonstrated with device simulations that the more flexible configuration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity.
Journal ArticleDOI
Silicon surface tunnel transistor
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.