Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel
TL;DR: In this article, the role of the channel on the drainpotential dependence of double-gate TFET characteristics is investigated, and it is found that a good drain current saturation is observed only for devices in which a relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel.
Abstract: Because of its different current injection mechanism, a tunnel field-effect transistor (TFET) can achieve a sub-60-m/decade subthreshold swing at room temperature, which makes it very attractive in replacing a metal-oxide semiconductor field-effect transistor, particularly for low-power applications It is well known that some specific TFET structures show a good drain current ID saturation in the output characteristics, whereas other structures do not A detailed investigation, through extensive device simulations, of the role of the channel on the drain-potential dependence of double-gate TFET characteristics is presented in this paper for the first time It is found that a good saturation of ID is observed only for devices in which a thin silicon body is used A relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel, which does not allow the drain current to saturate, even at higher drain voltages
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TL;DR: In this article, a short-gate tunneling-field-effect-transistor (SG-TFET) structure has been investigated for the dielectrically modulated biosensing applications in comparison with a full-gate TFET structure of similar dimensions.
Abstract: In this paper, a short-gate tunneling-field-effect-transistor (SG-TFET) structure has been investigated for the dielectrically modulated biosensing applications in comparison with a full-gate tunneling-field-effect-transistor structure of similar dimensions. This paper explores the underlying physics of these architectures and estimates their comparative sensing performance. The sensing performance has been evaluated for both the charged and charge-neutral biomolecules using extensive device-level simulation, and the effects of the biomolecule dielectric constant and charge density are also studied. In SG-TFET architecture, the reduction of the gate length enhances its drain control over the band-to-band tunneling process and this has been exploited for the detection, resulting to superior drain current sensitivity for biomolecule conjugation. The gate and drain biasing conditions show dominant impact on the sensitivity enhancement in the short-gate biosensors. Therefore, the gate and drain bias are identified as the effective design parameters for the efficiency optimization.
141 citations
TL;DR: In this paper, a 2D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2D Poisson's equation is presented.
Abstract: This paper presents a 2-D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2-D Poisson's equation. From the potential profile, the electric field is derived and then the drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the tunneling region. The model well predicts the potential, subthreshold swing (SS), and transfer and output characteristics of DG TFETs. We analyze the dependence of the tunneling current on the device parameters by varying the gate oxide dielectric constant, gate oxide thickness, body thickness, channel length and channel material and also demonstrate its agreement with TCAD simulation results. The SS which describes the switching behavior of TFETs, is derived from the current expression. The comparisons show that the SS of our model well coincides with that of simulations.
132 citations
Cites background from "Drain-Dependence of Tunnel Field-Ef..."
...One of the promising devices to replace the MOSFET for lowpower applications is the tunnel field effect transistor (TFET), which has demonstrated the potential to surmount the SS limit of MOSFETs [1]–[5]....
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...Since the charge concentration near the source-channel junction is negligible [5], the potential distribution along the x-axis can be written as v(x) = VGS − φ....
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TL;DR: In this paper, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications by extracting the threshold voltage of the device using a transconductance change method and a constant current method.
Abstract: In this paper, for the first time, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications. For this purpose, the suitability of the device for low-power applications is investigated by extracting the threshold voltage of the device using a transconductance change method and a constant current method. Furthermore, the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths. A highly doped layer is placed in the channel near the source–channel junction, and this decreases the width of the depletion region, which improves the ON-current ( ${I_{\rm{\scriptscriptstyle ON}}}$ ) and the RF performance. Furthermore, the circuit-level performance assessment is done by implementing a common source amplifier using the H-DGTFET; a 3-dB roll-off frequency of 230.11 GHz and a unity-gain frequency of 5.4 THz were achieved.
113 citations
Cites background from "Drain-Dependence of Tunnel Field-Ef..."
...mainly dominated by tunneling barrier between the source– channel regions [23]....
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TL;DR: In this article, the analog performance of a double-gate n-type tunnel field effect transistor (n-TFET) with a relatively small body thickness (10 nm) was investigated.
Abstract: In this paper, the analog performance is reported for the first time for a double-gate (DG) n-type tunnel field-effect transistor (n-TFET) with a relatively small body thickness (10 nm), which shows good drain current saturation. The device parameters for analog applications, such as transconductance gm, transconductance-to-drive current ratio gm/ID, drain resistance RO, intrinsic gain, and unity-gain cutoff frequency fT, are studied for DG n-TFET, with the help of a device simulator, and compared with that for a similar DG n-MOSFET. Although gm is lower, gm/ID is found to be higher in TFET, except for small values of the gate overdrive voltage, indicating that a TFET can produce higher gain at the same power level than a MOSFET. An extremely high RO and, hence, a high intrinsic gain are also observed for a TFET as compared with that for a MOSFET. A complementary TFET amplifier is found to have more than one order of magnitude higher voltage gain than its MOS counterpart. It is also demonstrated that the drain resistance and, hence, the device gain significantly degrade for increasing body thickness of a TFET.
110 citations
Cites background from "Drain-Dependence of Tunnel Field-Ef..."
...potential and, hence, cause accumulation/depletion/inversion in the entire channel region [16]....
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...To resolve this issue, we have recently reported [16] a detailed investigation on...
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01 Jan 2016
TL;DR: In this paper, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications by extracting the threshold voltage of the device using a transconductance change method and a constant current method, and the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths.
Abstract: In this paper, for the first time, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications. For this purpose, the suitability of the device for low-power applications is investigated by extracting the threshold voltage of the device using a transconductance change method and a constant current method. Furthermore, the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths. A highly doped layer is placed in the channel near the source-channel junction, and this decreases the width of the depletion region, which improves the ON-current (ION) and the RF performance. Fur- thermore, the circuit-level performance assessment is done by implementing a common source amplifier using the H-DGTFET; a 3-dB roll-off frequency of 230.11 GHz and a unity-gain frequency of 5.4 THz were achieved.
88 citations
References
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TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material
1,583 citations
"Drain-Dependence of Tunnel Field-Ef..." refers background in this paper
...bulk TFETs [1], [13], SG SOI TFETs with a relatively thick silicon body [8], [17], and vertical TFETs with a relatively...
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TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.
1,230 citations
"Drain-Dependence of Tunnel Field-Ef..." refers background in this paper
...Although the early reported TFETs suffered from a low ON-state current (ION) ,t he same has been reported to dramatically improve with the use of a delta-layer of SiGe at the edge of source [6], [10], a doublegate (DG) architecture [11], [12], a high-k gate dielectric [ 12 ], [13], and a low-k spacer [13]–[15]....
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...Although the early reported TFETs suffered from a low ON-state current (ION) ,t he same has been reported to dramatically improve with the use of a delta-layer of SiGe at the edge of source [6], [10], a doublegate (DG) architecture [11], [ 12 ], a high-k gate dielectric [12], [13], and a low-k spacer [13]–[15]....
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TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.
428 citations
TL;DR: In this article, the authors generalized the tunnel field effect transistor configuration by allowing a shorter gate structure, which is especially attractive for vertical nanowire-based transistors, and demonstrated with device simulations that the more flexible configuration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity.
Abstract: Tunnel field-effect transistors are promising successors of metal-oxide-semiconductor field-effect transistors because of the absence of short-channel effects and of a subthreshold-slope limit. However, the tunnel devices are ambipolar and, depending on device material properties, they may have low on-currents resulting in low switching speed. The authors have generalized the tunnel field-effect transistor configuration by allowing a shorter gate structure. The proposed device is especially attractive for vertical nanowire-based transistors. As illustrated with device simulations, the authors’ more flexible configuration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity.
390 citations
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
Abstract: A silicon surface tunneling transistor structure, based on lateral band‐to‐band tunneling, is presented The theory, fabrication, and operation of the device is described Band‐to‐band tunneling is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier The operation of the device is confirmed in both experimental results and two‐dimensional computer simulations Dramatic differences in drain current are observed for different gate bias
347 citations
"Drain-Dependence of Tunnel Field-Ef..." refers background or result in this paper
...Two major differences in the VDS dependence of the devices’ characteristics between such TFETs and the structure, as described in Section III-A, are given as follows: 1) the reported transfer characteristics for such structures show a relatively strong dependence on VDS and 2) the reported output characteristics do not show a perfect saturation of ID, although the rate of increase in ID for increasing VDS is small and may often wrongly be interpreted as perfect saturation [16], [17]....
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...The difference in the drain-potential dependence of the device characteristics for different DG n-TFETs has been analyzed....
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...simulation studies of capacitance–voltage characteristics [19], [21], it is still not clear why some other reported devices [1], [9] do not show such saturation....
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...of a conventional MOSFET, shows great promise for further extending the Moores law [1]–[9]....
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...Both the theoretical and the experimental results show that S can be much lower than 60 mV/decade for TFETs [6]–[8]....
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