Journal ArticleDOI
Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel
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TLDR
In this article, the role of the channel on the drainpotential dependence of double-gate TFET characteristics is investigated, and it is found that a good drain current saturation is observed only for devices in which a relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel.Abstract:
Because of its different current injection mechanism, a tunnel field-effect transistor (TFET) can achieve a sub-60-m/decade subthreshold swing at room temperature, which makes it very attractive in replacing a metal-oxide semiconductor field-effect transistor, particularly for low-power applications It is well known that some specific TFET structures show a good drain current ID saturation in the output characteristics, whereas other structures do not A detailed investigation, through extensive device simulations, of the role of the channel on the drain-potential dependence of double-gate TFET characteristics is presented in this paper for the first time It is found that a good saturation of ID is observed only for devices in which a thin silicon body is used A relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel, which does not allow the drain current to saturate, even at higher drain voltagesread more
Citations
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Journal ArticleDOI
Comparative Performance Analysis of the Dielectrically Modulated Full- Gate and Short-Gate Tunnel FET-Based Biosensors
TL;DR: In this article, a short-gate tunneling-field-effect-transistor (SG-TFET) structure has been investigated for the dielectrically modulated biosensing applications in comparison with a full-gate TFET structure of similar dimensions.
Journal ArticleDOI
A 2-D Analytical Model for Double-Gate Tunnel FETs
TL;DR: In this paper, a 2D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2D Poisson's equation is presented.
Journal ArticleDOI
Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping
TL;DR: In this paper, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications by extracting the threshold voltage of the device using a transconductance change method and a constant current method.
Journal ArticleDOI
Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications
TL;DR: In this article, the analog performance of a double-gate n-type tunnel field effect transistor (n-TFET) with a relatively small body thickness (10 nm) was investigated.
Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping Shylendra Ahish, Dheeraj Sharma, Yernad Balachandra Nithin Kumar, and Moodabettu Harishchandra Vasantha
TL;DR: In this paper, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications by extracting the threshold voltage of the device using a transconductance change method and a constant current method, and the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths.
References
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Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
Complementary tunneling transistor for low power application
Peng-Fei Wang,K. Hilsenbeck,Th. Nirschl,M. Oswald,Ch. Stepper,M. Weis,Doris Schmitt-Landsiedel,Walter Hansch +7 more
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Journal ArticleDOI
Tunnel field-effect transistor without gate-drain overlap
TL;DR: In this article, the authors generalized the tunnel field effect transistor configuration by allowing a shorter gate structure, which is especially attractive for vertical nanowire-based transistors, and demonstrated with device simulations that the more flexible configuration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity.
Journal ArticleDOI
Silicon surface tunnel transistor
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
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