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Physical Review B

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

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High-K materials and metal gates for CMOS applications

Conventional charge pumping is demonstrated on triple-gate silicon-on-insulator FinFET gated-diode structures with varying fin widths. A simple technique is proposed and verified allowing to independently estimate fin top and sidewall interface trap density. A higher interface state density on the sidewalls is observed, which is attributed to higher fin sidewall roughness. The methodology is also demonstrated to be sensitive to fin sidewall surface crystallographic orientation. The technique presents a straightforward means of assessing the fin sidewall and topwall interface quality, which can then be directly correlated with both processing influences and reliability effects

Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs

We report extensive experimental results of the negative bias temperature instability (NBTI) reliability of SiGe channel pMOSFETs as a function of the main gate-stack parameters. The results clearly show that this high-mobility channel technology offers significantly improved NBTI robustness compared with Si-channel devices, which can solve the reliability issue for sub-1-nm equivalent-oxide-thickness devices. A physical model is proposed to explain the intrinsically superior NBTI robustness.

SiGe Channel Technology: Superior Reliability Toward Ultrathin EOT Devices—Part I: NBTI

Based on detailed understanding of behavior and statistics of individual defects, we have presented a new methodology to predict the BTI lifetime distributions in deeply scaled FETs. Moreover, we have identified the sources of time dependent variability, some of which can be addressed technologically.

From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation

Data retention in flash memories is limited by anomalous charge loss. In this work, this phenomenon is modeled with a percolation concept. An analytical model is constructed that relates the charge-loss distribution of moving bits in flash memories with the geometric distribution of oxide traps. The oxide is characterized by a single parameter, the trap density. Combined with a trap-to-trap direct tunneling model, the physical parameters of the electron traps involved in the leakage mechanism are determined. Flash memory failure rate predictions for different oxide qualities, thicknesses and tunnel-oxide voltages are calculated.

Analytical percolation model for predicting anomalous charge loss in flash memories

Bias temperature instability (BTI) is a serious reliability concern for MOS transistors. This paper covers theoretical analysis, Monte Carlo simulation, and experimental investigation of the charge trapping component of BTI. An analytical model for both stress and recovery phases of BTI is presented. Furthermore, the model properly describes device behavior under periodic switching, also called AC-BTI or cyclostationary operation. The model is based on microscopic device physics parameters, which are shown to cause statistical variation in transistor BTI behavior. It is shown that a universal logarithmic law describes the time dependence of charge trapping in both stress and recovery phases, and that the time dependence may be separated from the temperature and bias point dependence. Analytical equations for the statistical parameters are provided. The model is compared with experimental data and Monte Carlo simulation results.

B. Kaczer

Papers

Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs

SiGe Channel Technology: Superior Reliability Toward Ultrathin EOT Devices—Part I: NBTI

From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation

Analytical percolation model for predicting anomalous charge loss in flash memories

Statistical Model for MOSFET Bias Temperature Instability Component Due to Charge Trapping