Journal ArticleDOI
Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs
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TLDR
In this paper, a simple technique is proposed and verified allowing to independently estimate fin top and sidewall interface trap density, which can then be directly correlated with both processing influences and reliability effects.Abstract:
Conventional charge pumping is demonstrated on triple-gate silicon-on-insulator FinFET gated-diode structures with varying fin widths. A simple technique is proposed and verified allowing to independently estimate fin top and sidewall interface trap density. A higher interface state density on the sidewalls is observed, which is attributed to higher fin sidewall roughness. The methodology is also demonstrated to be sensitive to fin sidewall surface crystallographic orientation. The technique presents a straightforward means of assessing the fin sidewall and topwall interface quality, which can then be directly correlated with both processing influences and reliability effectsread more
Citations
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Journal ArticleDOI
Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics.
Lijun Liu,Jie Han,Lin Xu,Jianshuo Zhou,Chenyi Zhao,Sujuan Ding,Sujuan Ding,Huiwen Shi,Mengmeng Xiao,Li Ding,Ze Ma,Chuanhong Jin,Chuanhong Jin,Zhiyong Zhang,Zhiyong Zhang,Lian-Mao Peng,Lian-Mao Peng +16 more
TL;DR: A multiple dispersion and sorting process resulted in extremely high semiconducting purity and a dimension-limited self-alignment procedure for preparing well-aligned CNT arrays with a tunable density of 100 to 200 CNTs per micrometer on a 10-centimeter silicon wafer.
Journal ArticleDOI
Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors
Eddy Simoen,Marc Gaillardin,P. Paillet,Robert A. Reed,Ronald D. Schrimpf,Michael L. Alles,F. El-Mamouni,Daniel M. Fleetwood,Alessio Griffoni,Cor Claeys +9 more
TL;DR: In this article, the authors describe the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies.
Proceedings ArticleDOI
Suppressing V t and G m variability of FinFETs using amorphous metal gates for 14 nm and beyond
Takashi Matsukawa,Yongxun Liu,Wataru Mizubayashi,Junichi Tsukada,Hiromi Yamauchi,Kazuhiko Endo,Yuki Ishikawa,Shin-ichi O'uchi,Hiroyuki Ota,Shinji Migita,Yukinori Morita,Meishoku Masahara +11 more
TL;DR: Amorphous TaSiN metal gates (MGs) are successfully introduced in FinFETs to suppress work function variation (WFV) of the MG, which is a dominant contributor to threshold voltage (V t ) variability of the undoped channel MG finFET.
Journal ArticleDOI
Silicide Engineering to Boost Si Tunnel Transistor Drive Current
Daniele Leonelli,Anne Vandooren,Rita Rooyackers,Anne S. Verhulst,Stefan De Gendt,Marc Heyns,Guido Groeseneken +6 more
TL;DR: In this paper, a trap-assisted tunneling (TAT) was used to degrade the subthreshold swing of the sub-10nm TAT-based device, due to an enhanced electric field caused by silicide encroachment and dopant segregation.
Journal ArticleDOI
Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities
Tamara Rudenko,Valeriya Kilchytska,Nadine Collaert,Malgorzata Jurczak,Alexey Nazarov,Denis Flandre +5 more
TL;DR: In this paper, the authors present an extensive experimental study of the effective mobility in the long-channel undoped triple-gate FinFETs, as compared with that in quasi-planar very wide fin FETs made on the same wafers and as a function of the fin width.
References
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Journal ArticleDOI
A reliable approach to charge-pumping measurements in MOS transistors
TL;DR: In this article, a new and accurate approach to charge-pumping measurements for the determination of the Si-SiO 2 interface state density directly on MOS transistors is presented.
Journal ArticleDOI
High performance fully-depleted tri-gate CMOS transistors
Brian S. Doyle,Suman Datta,Mark Beaverton Doczy,Scott Hareland,B. Jin,Jack Portland Kavalieros,Thomas D. Linton,Anand Portland Murthy,Rafael Rios,R. Chau +9 more
TL;DR: Fully depleted tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated in this article, where the transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages.
Journal ArticleDOI
Multiple-gate SOI MOSFETs: device design guidelines
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Nanoscale CMOS
TL;DR: This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime from the point of view of device physics, device technology, and power consumption and speculate on the future ofCMOS for the coming 15-20 years.
Proceedings ArticleDOI
FinFET process refinements for improved mobility and gate work function engineering
Yang-Kyu Choi,Leland Chang,Pushkar Ranade,Jeong-Soo Lee,Daewon Ha,Sriram Balasubramanian,A. Agarwal,M. Ameen,Tsu-Jae King,Jeffrey Bokor +9 more
TL;DR: In this article, the performance of FinFETs using Molybdenum (Mo) as the gate-electrode material for the first time has been investigated and multiple values of V/sub t/ are achieved via gate work function engineering by selective implantation of Mo.