B
Bernard Previtali
Researcher at University of Grenoble
Publications - 117
Citations - 2722
Bernard Previtali is an academic researcher from University of Grenoble. The author has contributed to research in topics: MOSFET & Silicon on insulator. The author has an hindex of 26, co-authored 114 publications receiving 2419 citations. Previous affiliations of Bernard Previtali include Alternatives & French Alternative Energies and Atomic Energy Commission.
Papers
More filters
Proceedings ArticleDOI
Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible Tunnel FET performance
F. Mayer,C. Le Royer,J.-F. Damlencourt,K. Romanjek,Francois Andrieu,Claude Tabone,Bernard Previtali,Simon Deleonibus +7 more
TL;DR: In this article, the Drift Tunnel FET (DTFET) was proposed to solve the TFET bipolar parasitic conduction by a novel TFET architecture, with improved OFF state control, and demonstrated functional TFET and CMOS devices on Si1-xGexOI (x=15-30-100%) co-integrated with the same SOI process flow.
Proceedings ArticleDOI
Advances, challenges and opportunities in 3D CMOS sequential integration
Perrine Batude,Maud Vinet,Bernard Previtali,Claude Tabone,Cuiqin Xu,J. Mazurier,Olivier Weber,Francois Andrieu,L. Tosti,L. Brevard,Benoit Sklenard,Perceval Coudrain,Shashikanth Bobba,H. Ben Jamaa,P.-E. Gaillardon,A. Pouydebasque,Olivier P. Thomas,C. Le Royer,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Laurent Clavelier,G. De Micheli,Simon Deleonibus,O. Faynot,Thierry Poiroux +26 more
TL;DR: This paper addresses the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer and can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices.
Proceedings ArticleDOI
Advances in 3D CMOS sequential integration
Perrine Batude,Maud Vinet,A. Pouydebasque,C. Le Royer,Bernard Previtali,Claude Tabone,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Alain Toffoli,F. Allain,V. Mazzocchi,D. Lafond,Olivier P. Thomas,O. Cueto,N. Bouzaida,D. Fleury,Amara Amara,Simon Deleonibus,O. Faynot +20 more
TL;DR: In this article, a 3D sequential CMOS integration of top Si active layers is presented, and the electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm.
Journal ArticleDOI
Bonded planar double-metal-gate NMOS transistors down to 10 nm
Maud Vinet,Thierry Poiroux,Julie Widiez,J. Lolivier,Bernard Previtali,C. Vizioz,B. Guillaumot,Y. Le Tiec,P. Besson,B. Biasse,F. Allain,Mikael Casse,D. Lafond,J.M. Hartmann,Yves Morand,J. Chiaroni,Simon Deleonibus +16 more
TL;DR: In this paper, the first 10-nm-gate-length DG MOS transistors with metal gates were processed, which exhibited excellent short-channel effects control and high-performance characteristics.
Journal ArticleDOI
GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current
Louis Hutin,C. Le Royer,J.-F. Damlencourt,J.M. Hartmann,H. Grampeix,V. Mazzocchi,Claude Tabone,Bernard Previtali,A. Pouydebasque,Maud Vinet,O. Faynot +10 more
TL;DR: In this article, the most aggressive dimensions reported in Ge-channel transistors are pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm).