P
Perrine Batude
Researcher at University of Grenoble
Publications - 117
Citations - 2212
Perrine Batude is an academic researcher from University of Grenoble. The author has contributed to research in topics: Silicon on insulator & Transistor. The author has an hindex of 23, co-authored 113 publications receiving 1957 citations. Previous affiliations of Perrine Batude include European Automobile Manufacturers Association & Commissariat à l'énergie atomique et aux énergies alternatives.
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Proceedings ArticleDOI
Advances, challenges and opportunities in 3D CMOS sequential integration
Perrine Batude,Maud Vinet,Bernard Previtali,Claude Tabone,Cuiqin Xu,J. Mazurier,Olivier Weber,Francois Andrieu,L. Tosti,L. Brevard,Benoit Sklenard,Perceval Coudrain,Shashikanth Bobba,H. Ben Jamaa,P.-E. Gaillardon,A. Pouydebasque,Olivier P. Thomas,C. Le Royer,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Laurent Clavelier,G. De Micheli,Simon Deleonibus,O. Faynot,Thierry Poiroux +26 more
TL;DR: This paper addresses the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer and can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices.
Proceedings ArticleDOI
Advances in 3D CMOS sequential integration
Perrine Batude,Maud Vinet,A. Pouydebasque,C. Le Royer,Bernard Previtali,Claude Tabone,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Alain Toffoli,F. Allain,V. Mazzocchi,D. Lafond,Olivier P. Thomas,O. Cueto,N. Bouzaida,D. Fleury,Amara Amara,Simon Deleonibus,O. Faynot +20 more
TL;DR: In this article, a 3D sequential CMOS integration of top Si active layers is presented, and the electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm.
Proceedings ArticleDOI
3DVLSI with CoolCube process: An alternative path to scaling
Perrine Batude,Claire Fenouillet-Beranger,L. Pasini,V. Lu,F. Deprat,Laurent Brunet,Benoit Sklenard,F. Piegas-Luce,M. Casse,B. Mathieu,O. Billoint,G. Cibrario,Ogun Turkyilmaz,Hossam Sarhan,Sebastien Thuries,Louis Hutin,S. Sollier,Julie Widiez,L. Hortemel,Claude Tabone,M.-P. Samson,Bernard Previtali,N. Rambal,F. Ponthenier,J. Mazurier,Remi Beneyton,M. Bidaud,Emmanuel Josse,E. Petitprez,O. Rozeau,Maurice Rivoire,C. Euvard-Colnat,A. Seignard,F. Fournel,L. Benaissa,Perceval Coudrain,P. Leduc,J.M. Hartmann,Pascal Besson,Sebastien Kerdiles,C. Bout,Fabrice Nemouchi,A. Royer,C. Agraffeil,G. Ghibaudo,Thomas Signamarcheix,Michel Haond,Fabien Clermidy,O. Faynot,Maud Vinet +49 more
TL;DR: In this paper, the authors propose a 3D VLSI with a CoolCube integration to vertically stack several layers of devices with a unique connecting via density above a million/mm2.
Proceedings ArticleDOI
CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits
Shashikanth Bobba,Ashutosh Chakraborty,Olivier P. Thomas,Perrine Batude,Thomas Ernst,O. Faynot,David Z. Pan,Giovanni De Micheli +7 more
TL;DR: This work proposes two different strategies of stacking standard cells in 3-D without breaking the regularity of the conventional design flow: a) Vertical stacking of diffusion areas (Intra-Cell stacking) that supports complete reuse of 2-D physical design tools and b) vertical stacking of cells over others (Cell-on-Cell stacks).
Journal ArticleDOI
3D monolithic integration: Technological challenges and electrical results
Maud Vinet,Perrine Batude,Claude Tabone,Bernard Previtali,C. LeRoyer,A. Pouydebasque,Laurent Clavelier,A. Valentian,Olivier P. Thomas,S. Michaud,Loic Sanchez,L. Baud,A. Roman,V. Carron,Fabrice Nemouchi,V. Mazzocchi,H. Grampeix,Amara Amara,Simon Deleonibus,O. Faynot +19 more
TL;DR: In this paper, the main technological challenges associated with monolithic 3D integration are reviewed and solutions to assess them are proposed, and the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer.