V
V. Mazzocchi
Researcher at University of Grenoble
Publications - 28
Citations - 752
V. Mazzocchi is an academic researcher from University of Grenoble. The author has contributed to research in topics: Dopant Activation & Wafer bonding. The author has an hindex of 11, co-authored 27 publications receiving 708 citations.
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Proceedings ArticleDOI
Advances in 3D CMOS sequential integration
Perrine Batude,Maud Vinet,A. Pouydebasque,C. Le Royer,Bernard Previtali,Claude Tabone,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Alain Toffoli,F. Allain,V. Mazzocchi,D. Lafond,Olivier P. Thomas,O. Cueto,N. Bouzaida,D. Fleury,Amara Amara,Simon Deleonibus,O. Faynot +20 more
TL;DR: In this article, a 3D sequential CMOS integration of top Si active layers is presented, and the electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm.
Journal ArticleDOI
GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current
Louis Hutin,C. Le Royer,J.-F. Damlencourt,J.M. Hartmann,H. Grampeix,V. Mazzocchi,Claude Tabone,Bernard Previtali,A. Pouydebasque,Maud Vinet,O. Faynot +10 more
TL;DR: In this article, the most aggressive dimensions reported in Ge-channel transistors are pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm).
Journal ArticleDOI
3D monolithic integration: Technological challenges and electrical results
Maud Vinet,Perrine Batude,Claude Tabone,Bernard Previtali,C. LeRoyer,A. Pouydebasque,Laurent Clavelier,A. Valentian,Olivier P. Thomas,S. Michaud,Loic Sanchez,L. Baud,A. Roman,V. Carron,Fabrice Nemouchi,V. Mazzocchi,H. Grampeix,Amara Amara,Simon Deleonibus,O. Faynot +19 more
TL;DR: In this paper, the main technological challenges associated with monolithic 3D integration are reviewed and solutions to assess them are proposed, and the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer.
Proceedings ArticleDOI
3D monolithic integration
Perrine Batude,Maud Vinet,A. Pouydebasque,C. Le Royer,Bernard Previtali,Claude Tabone,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Alain Toffoli,F. Allain,V. Mazzocchi,D. Lafond,Simon Deleonibus,O. Faynot +15 more
TL;DR: A 3D monolithic process flow relying on molecular wafer bonding is proposed and results in all critical steps are given and functional top and bottom transistors as well as 3D structures such as invertors and SRAMs are demonstrated.
Journal ArticleDOI
High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate
K. Romanjek,Louis Hutin,C. Le Royer,A. Pouydebasque,Marie-Anne Jaud,Claude Tabone,E. Augendre,Loic Sanchez,J.M. Hartmann,H. Grampeix,V. Mazzocchi,S. Soliveres,R. Truche,Laurent Clavelier,P. Scheiblin,X. Garros,G. Reimbold,Maud Vinet,Fabien Boulanger,Simon Deleonibus +19 more
TL;DR: In this paper, the authors demonstrate for the first time 70nm gate length gate length TiN/HfO 2 pMOSFETs on 200mm GeOI wafers, with excellent performance: I ON Â= 260μA/μm and I OFF Â = 500 Ã 1.0 Â V (without germanide).